RAVI KIRAN C. R.

___________________________________________________________ E-mail:rkiran@netlogicmicro.com Mobile: 9886830848 PROFESSIONAL EXPERIENCE: Working at Net Logic Semiconductor (Microsystems) Pvt. Ltd, Bangalore. From February 2010 - till date as Layout Design engineer

SKILLS: Virtuoso Layout L editor, Virtuoso Layout XL editor, Virtuoso Schematic editor Calibre DRC, Calibre LVS, and Calibre rule decks and flow Programming Languages: PERL and SKILL

Project details: 1. 80Mb KBP Serial interface, 600MHz manufactured using 28nm, 10 Metals.(ongoing) Layout Design: Designing the Standard Cell Layout library with accordance to the given schematic Floor planning and signal planning of complex control blocks Designed i/p and o/p complex data path and control blocks Planning and implementing core clock tree layout Layout Design Verification: Responsibility of Checking and Correcting DRC, LVS, Antenna violations in the design (using Calibre tool)

2. Multi-core processor: SRAM macros, manufactured using 28nm, 6 Metals.(6months) Layout Design: Designing the Standard Cell Layout library with accordance to the given schematic Floor planning and signal planning of complex control blocks Designed i/p and o/p complex data path and control blocks Layout Verification: Responsibility of Checking and Correcting DRC, LVS in the design (using Caliber tool) Responsibility of Checking and correcting Density Violations, m-boundary checks and (EM) violations

3. PLG-product, ref clk-201.42, the 7x/2z metal stack, in 28nm TSMC node Layout Design: Designing the Standard Cell Layout library with accordance to the given schematic Floor planning and signal planning of complex control blocks Layout Design Verification: Responsibility of Checking and Correcting DRC and LVS in the design (using Calibre tool)

4.

PLG-product:- Performance critical blocks, such as 10GBps PHYs for KR backplane, in 40nm TSMC node. Layout Design: Designing the Standard Cell Layout library with accordance to the given schematic Floor planning and signal planning of complex control blocks Layout Verification: Responsibility of Checking and Correcting DRC and LVS in the design (using Calibre tool)

5. 80Mb KBP Parallel interface, 250MHz manufactured using 40nm, 8 Metals. Layout Design: Designing full-custom Standard Cell Layout library with accordance to the given schematic Floor planning and signal planning of complex control blocks Designed i/p and o/p complex data path and control blocks Designed address decoder and integration of interface blocks Designed core interface blocks Layout Verification: Responsibility of Checking and Correcting DRC, LVS, Antenna violations in the design (using Calibre tool) Responsibility of Checking and correcting Density Violations and EM/IR violations

6. 80Mb KBP - Parallel interface, 400MHz, at 40nm, 8 Metals Layout Design:

 Integrated standard cell blocks according to hierarchy specifications of the design Layout Verification: Responsibility of Checking and Correcting DRC, LVS, Antenna violations in the design (using Calibre) Responsibility of Checking and correcting base-layer and metal Density Violations and EM/IR violations Responsibility of correcting Latch-up violations in the design

EDUCATIONAL QUALIFICATION:

B. E (Electronics & Communication) in 2010 securing 72% from REVA ITM, Bangalore (affiliated to VTU, Belgaum) PUC in 2005 securing 77% from Sheshadripuram (main) College, Bangalore SSLC in 2003 securing 81% from Presidency school, Bangalore

Engineering Project: Worked at Indian Institute of Science (IISc), CGPL Department under the guidance of N.K.S. Rajan (principal research scientist), for a duration of 9 months for the project Switching Control of Load Panel using PCB Designing and implementation using ORCAD software

PERSONAL DETAILS:

Date of Birth: 14th January 1988 Gender: Male Martial status: Single Residence Address: Ganganagar, Bangalore-560032 #3, 4th cross, vasanthappa block, Gopalraj colony,

Hobbies: Reading novels, listening to music, playing cricket, table tennis

DECLARATION I hereby declare that the above information is true to my knowledge.

DATE :- 13/09/2011 PLACE:- Bangalore

(Ravi Kiran C.R)