EEs801 Seminar report

FinFETs
Venkatnarayan Hariharan
Roll# 04407603
28
th
Apr 2005
Electrical Engineering Dept.
IIT Bombay
Spring 2005
Copyright (C) 2005 IIT Bombay
All Rights Reserved
Change Record
Date Author Versio
n
Change Reference
28-Apr-05 vharihar@ee.iitb.ac.in 1.0 No previous document.
Reviewers
Name Location
Prof V. Ramgopal Rao EE Annexe
Prof M.B. Patil EE Annexe
Distribution
Copy
No
Name Location
1. Prof V. Ramgopal Rao EE Annexe
2. Prof M.B. Patil EE Annexe
2
Table of Contents
ACKNOWLEDGMENT.....................................................................................................................................................................4
ABSTRACT.................................................................................................................................................................................5
INTRODUCTION...........................................................................................................................................................................6
What is a DG-MOSFET?.............................................................................................................................................................6
What is a FinFET?.......................................................................................................................................................................9
FINFET FABRICATION...............................................................................................................................................................11
RECENT WORK ON FINFETS.......................................................................................................................................................14
Fabrication efforts.....................................................................................................................................................................14
Anaytical models........................................................................................................................................................................16
Effect of non-vertical fin sidewall.............................................................................................................................................17
Corner effects.............................................................................................................................................................................18
FinFET circuits, layouts............................................................................................................................................................20
Device width quantization.......................................................................................................................................................................21
Layout density optimization....................................................................................................................................................................22
CONCLUSIONS..........................................................................................................................................................................23
REFERENCES............................................................................................................................................................................24
3
Acknowledgment
I would like to thank my guide Prof V. Ramgopal Rao for his guidance directly
related to this work, as well as for the knowledge I received while attending
his concurrently-running lectures in the semester on Nanoelectronics, some
of whose topics coincided with the present work.
4
Abstract
In this report, the basic FinFET structure is described, along with the reasons
behind its introduction. The fabrication steps are briefly discussed. Lastly,
some recent work on FinFETs is presented, along with the outstanding issues
that people have been focusing on.
5
Introduction
As devices shrink further and further, the problems with conventional
(planar) MOSFETs are increasing. Industry is currently at the 90nm node (ie.
DRAM half metal pitch, which corresponds to gate lengths of about 70nm). As
we go down to the 65nm, 45nm, etc nodes, there seem to be no viable
options of continuing forth with the conventional MOSFET. Severe short
channel effects (SCE) such as VT rolloff and drain induced barrier lowering
(DIBL), increasing leakage currents such as subthreshold S/D leakage, D/B
(GIDL), gate direct tunneling leakage, and hot carrier effects that result in
device degradation is plaguing the industry (at the device level; there are
other BEOL (back-end of the line) problems such as interconnect RC delays
which we wont discuss here). Reducing the power supply Vdd helps reduce
power and hot carrier effects, but worsens performance. Performance can be
improved back by lowering VT but at the cost of worsening S/D leakage. To
reduce DIBL and increase adequate channel control by the gate, the oxide
thickness can be reduced, but that increases gate leakage. Solving one
problem leads to another. Efforts are on to find a suitable high-k gate
dielectric so that a thicker physical oxide can be used to help reduce gate
leakage and yet have adequate channel control, but this search has not been
successful to the point of being usable. There are problems with band
alignment (w.r.t Si) and/or thermal instability problems and/or interface
states problems (with Si). The thermal instability problem has led researchers
to search for metal gate electrodes instead of polysilicon (because
insufficient activation leads to poly depletion effects). But metal gates with
suitable work functions havent been found to the point of being usable. In
the absence of this, polysilicon continues to be used, whose work function
demands that VT be set by high channel doping. High channel doping in turn
leads to random dopant fluctuations (at small gate lengths) as well as
increased impurity scattering and therefore reduced mobility. Indeed, it is felt
that instead of planar MOSFETs, a double gate device will be needed at gate
lengths below 50nm [1] in order to be able to continue forth on the shrinking
path.
What is a DG-MOSFET?
Double gate MOSFETs (DG-FET) is a MOSFET that has two gates to control the
channel. Its schematic is shown in Fig. 1.
Fig. 1: Cross section of a generic planar DGFET (from [2])
6
Its main advantage is that of improved gate-channel control. In conjunction
with ultra thin bodies in an SOI implementation (FDSOI DG-FET), it
additionally offers reduced SCE, because all of the drain field lines are not
able to reach the source. This is because the gate oxide has a lower dielectric
constant than Si (assuming the oxide is SiO2), and also because the body is
ultra thin. Because of its greater resilience to SCE and greater gate-channel
control, the physical gate thickness can be increased (compared to planar
MOSFET). Thus it also brings along reduced leakage currents (gate leakage
as well as S/D leakage).
There are 2 kinds of DG-FETs:
Symmetric
Asymmetric
Symmetric DG-FETs have identical gate electrode materials for the front and
back gates (ie. top and bottom gates). When symmetrically driven, the
channel is formed at both the surfaces. In an asymmetric DG-FET, the top
and bottom gate electrode materials can differ (eg. n+ poly and p+ poly).
When symmetrically driven this would end up forming a channel on only one
of the surfaces. Both have their advantages and disadvantages. Recent work
regarding them will be described in a later section in this report.
Energy band diagrams for symmetrical and asymmetrical DG-FETs are shown
in Figures 1 and 2
Fig. 1: Symmetrical DGFET energy band diagram (from [3]) Fig. 2: Asymmetrical DGFET energy band diagram (from [3])
The biggest and perhaps the only stumbling block with DG-FETs is its
fabrication. One can conceive of 3 ways [4, 7] to fabricate a DG-FET, labeled
Types 1, 2 and 3 in Fig. 3.
7
Fig 3: Three possible realizations of DGFETs (from [7])
Types 1 and 2 suffer most from fabrication problems, viz. it is hard to
fabricate both gates of the same size and that too exactly aligned to each
8
other. Also, it is hard to align the source/drain regions exactly to the gate
edges. Further, in Type 1 DG-FETs, it is hard to provide a low-resistance,
area-efficient contact the bottom gate, since it is buried.
What is a FinFET?
Type 3 DG-FETs are called FinFETs. Even though current conduction is in the
plane of the wafer, it is not strictly a planar device. Rather, it is referred to as
a quasi-planar device, because its geometry in the vertical direction (viz. the
fin height) also affects device behavior. Amongst the DG-FET types, the
FinFET is the easiest one to fabricate. Its schematic is shown in Fig. 4.
Fig. 4: FinFET structure, with dimensions marked (from [4])
Because of the vertically thin channel structure, it is referred to as a fin
because it resembles a fishs fin; hence the name FinFET. A gate can also be
fabricated at the top of the fin, in which case it is a triple gate FET. Or
optionally, the oxide above the fin can be made thick enough so that the
gate above the fin is as good as not being present. (This helps in reducing
corner effects, discussed later in this report)
9
It should be noted that while the gate length L of a FinFET is in the same
sense as that in a conventional planar FET, the device width W is quite
different. W is defined as:
fin fin
T H W + 2
where Hfin and Tfin are the fin height and thickness respectively (see Fig. 4
above. Some literature refers to the fin thickness as the fin width). The
reason for this is quite clear when one notices that W as defined above is
indeed the width of the gate region that is in touch with (ie. in control of) the
channel in the fin (albeit with a dielectric in between). This fact can especially
be seen if one unfolds the gate (ie. unwraps it).
The above definition of device width is for a triple gate FinFET. If the gate
above the fin is absent/ineffective, then the Tfin term in the above definition is
taken out.
On the surface, this freedom in the vertical direction (of increasing Hfin) is a
much desired capability since it lets one increase the device width W without
increasing the planar layout area! (Increasing W increases the Ion, a desirable
feature). However, it will be seen in subsequent sections in this report, that
there is a definite range (in relation to Tfin) beyond which Hfin should not be
increased, else one encounters SCE [5, 6].
10
FinFET fabrication
The key challenges in FinFET fabrication are the thin, uniform fin; and also in
reducing the source-drain series resistance.
FinFETs have broadly been reported to have been fabricated in 2 ways [7]:
Gate-first process: Here the gate stack is patterned/formed first, and
then the source and drain regions are formed
Gate-last process (also called replacement gate process): Here source
and drain regions are formed first and then the gate is formed
Fig. 5 illustrates both processes.
Fig. 5: High level FinFET fabrication steps; (a-b): Gate-first process, (c-f): Gate last process (from
[7])
11
FinFETs are usually fabricated on an SOI substrate. It starts by patterning
and etching thin fins on the SOI wafer using a hard mask. The hard mask is
retained throughout the process to protect the fin. The fin thickness is
typically half or one third the gate length, so it is a very small dimension. It is
made by either e-beam lithography or by optical lithography using extensive
linewidth trimming [7].
In the gate-first process, fabrication steps after the fin formation are similar
to that in a conventional bulk MOSFET process. In the gate-last process, the
source/drain is formed immediately after fin patterning. To protect the fin
while forming the other regions, doped poly or poly SiGe [7] or even doped
amorphous Silicon [8] is deposited on the fin. Then the S/D fan-out pads are
patterned, leaving a thin slot between the source and the drain. This distance
determines the gate length, which can be further reduced using a dielectric
sidewall spacer. Finally the gate oxide is grown and the gate material is
deposited and patterned.
To create thin fins very close to each other, the sidewall image transfer (SIT)
technique can be used. This technique can help obtain a fin pitch that is half
the lithography pitch, which is desirable because:
It improves device layout density (done by creating very close fins and
using a trim level to break the gate continuity, thus separating
devices), and
It enables having the fin pitch smaller than the fin height, which is
desirable because it make the FinFET have a greater effective device
width than a planar conventional FET.
The SIT technique is illustrated in Fig. 6.
12
Fig. 6: Sidewall Image Transfer (SIT) technique to create closely spaced, narrow fins (from [7])
13
Recent work on FinFETs
Fabrication efforts
Ultra thin fins result in better SCE, but increased series resistance. So a fine
balance has to be achieved between the two goals. Also, the fabrication
process has to be easily integrate-able into conventional CMOS process to
the extent possible. Keeping such considerations in mind and others, there
have been many efforts to fabricate and characterize FinFETs. Some of them
are listed below.
Hisamoto et al reported a gate-last process [8] where they made FinFETs
with10nm thick and 50nm tall fins, and 30nm gate length. The fins were
patterned using e-beam lithography. The gate material was boron-doped
Si0.4Ge0.6, which has the advantage that it is compatible with poly-Si process
and its work function is continuously controllable by the mole fraction of Ge.
Boron-doped Si0.4Ge0.6 results in a mid-gap work function. The gate was self-
aligned to S/D, which was a raised source drain (RSD) structure to reduce
series resistance. As was reported, a S/D first, gate-last process can be
advantageous when used with a high-k gate dielectric, which mostly have
thermal stability issues.
Using a gate-first process, Collaert, et al fabricated FinFETs [9] having (poly,
not metal) gate lengths (Lpoly) of 25nm for nFETs and 35nm for pFETs, with
60-80nm tall fins, each being 10nm thick with a 1.6nm gate oxide EOT. The
fins were patterned using e-beam lithography. The wafers underwent a H2
anneal to smoothen the fin surface and a 15nm oxidation to round the
corners (more on corner effects later in this report). Selective epitaxy to
create RSD were not used just to simplify the fabrication process, even
though they would have lowered the series resistance.
Kedzierski, et al also fabricated a FinFET using a gate-first process [10] where
they made symmetric as well as asymmetric FinFETs. Polysilicon gates were
used. The symmetric FinFETs were smaller and had dimensions of Lpoly=60nm
(Leff = 30nm), Tfin=10nm and Hfin=65nm. The thin fin was fabricated using
optical lithography and a hard mask trimming technique, whose further
details are unavailable. The asymmetric FinFETs had p+ and n+ poly gates.
They were realizable using gate implant shadowing, because they had a
taller 120nm fin. Selective epitaxy was used to create RSD to create devices
with low series resistance. Figures 7 and 8 show the Id-Vg curves obtained.
14
Fig. 7: Id-Vg plot of asymmetric FinFETs (from [10]) Fig. 8: Id-Vg plot of symmetric FinFETs (from [10])
More recently, Kedzierski, et al fabricated a high performance FinFET using a
gate-first process [11], with a 30nm gate length. Epitaxial RSD, highly angled
S/D implants, and CoSi2 silicidation were used to reduce series resistance.
High performance nFETs and pFETs with ION of 1460uA/um and 850uA/um
were reported. The fin thickness and height was 20nm and 65nm
respectively, with a 1.6nm oxide. Many devices were fabricated to specifically
study the effect of fin thickness and height on the series resistance. Devices
were fabricated in the <100> as well as <110> direction. Fig. 9 shows a
cross section.
Fig. 9: Electron micrographs of a <110> FinFET perpendicular to current flow (from [11])
Choi et al also used a gate-first process [12] and fabricated FinFETs with
Molybdenum (Mo) gates. The fins were 10nm thick. 20nm thick Molybdenum
(Mo) gates were used. Gate work function engineering was demonstrated by
having Mo implanted with Nitrogen (N2). By having the Mo gates on some
nFET devices implanted with N2 while leaving other Mo gated pFETs
unchanged , they increased the |VT| of those pFETs, thus demonstrating
multiple VT devices. It was reported that this technique can be used for nFETs
too. In the Mo gated devices, RSD, silicidation processes and hydrogen
annealing were not used just to keep the fabrication simple, because their
focus was mainly on demonstrating Mo gates with multiple VT. In another
fabrication effort, the same authors used hydrogen annealing on poly gate
devices, and found that it improves the fin surface quality very much. As a
result, surface roughness was reduced, resulting in higher mobility and
therefore currents, as well as reduced noise. Fig. 10 shows the effect of the
Hydrogen anneal.
15
Fig. 10: Effect of H2 anneal (from [12])
Anaytical models
FinFETs are usually made with mid-gap work function metal gates and an
undoped fin, so the threshold voltage expression VT is very simply given by
FB T
V V
where VFB is the flatband voltage.
However, in the absence of an exotic metal gate, most of the work has been
with doped fins and poly gate. In such cases, people have come up with
analytic models for the case of a DGFET, which should apply for a FinFET too
with a few modifications. Neglecting fast surface states, the front and back
gate voltages in the case of a fully depleted thin body DGFET have been
derived [13, 14] as:
( ) ( )
of b of cf sb of b sf of b FBf GfS
C Q C Q C C C C V V 2 / / / / 1 + +
and
( ) ( )
ob b ob cb sb ob b sf ob b FBb GbS
C Q C Q C C C C V V 2 / / / 1 / + +
where:
VGfS and VGbS and front and back gate-to-source voltages;
VFBf and VFBb are the front- and back-gate flatband voltages;
sf and sb are the front and back surface potentials;
Qcf and Qcb are the front- and back-surface inversion charge densities;
Si A b
t qN Q is the depletion charge density;
oxf ox of
t C /
and
oxb ox ob
t C / are the front- and back-gate oxide
capacitances;
16
Si Si b
t C / is the depletion capacitance.
For FinFETs as well as SDDG (symmetrically driven DGFETs), we can set VGfS =
VGbS = VGS. Then, eliminating the sb term, the expression for VGS is derived as:
( )
1
1
]
1

,
_

,
_

+ +
+
+
ob
b
of
b
ob
cb
of
cf
FBb FBf sf GS
C
Q
r
C
Q
C
Q
r
C
Q
rV V
r
V
2 2 1
1

where r , termed as the gate-gate coupling factor, is given by:

( )
ob b of
ob b
C C C
C C
r
+

Considering inversion channel thickness and its capacitance effects, the

threshold voltage for a thin, fully depleted asymmetric DGFET has also been
derived [14] as:
( )
1
1
]
1

,
_

+
+
+
b
b
of
b
FBb FBf sf asymm Tf
C
Q
r
C
Q
rV V
r
V
2 1
1
) (

Besides threshold voltage, analytic models have also been derived for other
parameters such as a quantitative measure of the short channel effects (the
generalized scale length is one such parameter, whose concept is
applicable to bulk, planar MOSFETs as well; when compared to certain
dimensions (eg. channel length), it gives a measure of the extent of SCE).
In [6], Pei et al have made 3D calculations and derived analytical solutions
for subthreshold behaviour of FinFETs. Based on that, they have derived
expressions for VT rolloff and subthreshold swing S, using S/D potential
barrier in the most leaky path considerations, in a 3D model of the fin.
Simulations have been done for a range of fin heights and thicknesses. Using
these models, they have been able to show that for certain
combinations/ratios of dimensions, certain dimensions play a dominant role
in the SCE while not the others. They have gone on to derive a single
universal expression for the VT rolloff that is valid for FinFETs, DGFETs,
rectangular surrounding gate FETs and FD SOI MOSFETs, using
parameterized constants having different values for the 4 device families.
Effect of non-vertical fin sidewall
The fabrication of the uniform, ultra thin fin is one of the key challenges in
FinFET fabrication. Due to non ideal anisotropic over etch, the fins can end up
having a slightly triangular or trapezoidal shape. Concave and convex
surfaces can also end up during the reactive ion etching (RIE) process. In [5],
Wu et al assumed a trapezoidal shape and studied the effect of the various
parameters of the trapezoid (slope of the sidewall, fin height, etc) on the
subthreshold slope S and VT rolloff, using 3D device simulations. Assuming a
constant top thickness (of the fin), S and VTrolloff worsens as the fin height is
increased. This is because the thickness at the bottom increases, resulting in
worsened SCE. It was reported that more than 50% profit from suppression of
SCE can be gained, if the sidewall angle (w.r.t. horizontal) is controlled
between 75 to 85.
17
Corner effects
In ultra thin triple gate (TG) FinFETs with a doped fin, the corners of the fin
get inverted before the sidewalls of the fin get inverted. This is because the
corners are under the influence of 2 gates (the top gate and one of the
sidewall gates). This also makes the corners turn off later, as the gate voltage
is ramped down. As a result, there is increased subthreshold leakage at the
corners. There have been many efforts to study these corner effects and see
how they can be minimized. The unanimous conclusion in all these efforts
has been that to minimize these corner effects, we need FinFETs with:
Undoped fins
Metal gates with appropriate work function for VT control
Corners of fins should be rounded as much as possible (ie. not sharp)
In the papers reviewed, it wasnt categorically mentioned but it is felt (by the
author of the current report) that corner effects can also be minimized if
double gate FinFETs were used (ie. make the gate oxide over the fin very
thick).
Simulations were done in [15] where devices with identical top and bottom
corner radii as well as different top and bottom corner radii were considered.
The device cross sections considered are shown in Fig. 11. The gate material
was N+ polysilicon with a ms = -0.9V. The fin was therefore highly doped in
order to get a workable threshold voltage. The fin thickness Tfin (shown as W
in Fig. 11) was 30nm, and the gate oxide thickness was 2nm. Simulations
were done as the doping was varied from 10
18
to 5x10
18
cm
-3
. It was found
that corner effects degrade the subthreshold slope S when the fin doping is
increased and/or the radius of curvature of the corners is low (ie. sharp
curvature).
Fig. 11: Fin cross section considered in the simulations (from [15])
Fossum et al did simulations as well as quasi 2D analysis in [16]. In the
analysis, N+ poly gates with a fin doping of 8x10
18
cm
-3
was assumed for VT
control, and a 1.1nm thick gate oxide. Quantum Mechanical effects were not
considered but the authors reported that a QM consideration would show
slightly reduced inversion concentrations in the corners but still high enough
to be cause for concern. Narrow fins, while are beneficial in suppressing SCE,
show worsening corner effects. So a fine balance has to be struck between
the two goals. Figures 12 and 13 show the electron concentrations in the fin
cross section in a doped and undoped fin, respectively.
18
Fig. 12: MEDICI predicted 2D electron distribution in a highly
doped TG FinFET (from [16])
Fig. 13: Electron distribution in an undoped TG FinFET (from [16])
Using 2D and 3D simulations, Stadele et al did a comprehensive study [17] of
corner effects with more parameters in the picture. The 3D simulations were
done on many devices with 20nm and 40nm gate lengths, and fin doping NA
ranging from 10
16
to 8x10
18
cm
-3
, with a S/D vertical steepness profile of
11nm/decade. The gate was a metal with a work function of 4.15eV, and the
oxide was SiO2. 2D simulations were done in slices perpendicular to the S/D
axis. Thus, corner effects as a function of the position on the channel was
also studied. However, it was found that the corner effects are a very weak
function of position on the channel, for both 20nm as well as 40nm devices.
Because the fin is very narrow, random dopant fluctuations can also cause
unwanted variations. The effect of this was also studied (statistically), to
highlight the serious nature of random dopant fluctuations. 500 sample
devices were auto-generated for simulation purposes, with NA varying
between 10
18
and 4x10
18
cm
-3
. The result is shown in Fig. 14, where nmax refers
to the maximum attainable value of the electron density in the top corners of
the fin (expressed as a fraction of the total inversion density). The
19
randomness is attributed to the fact that in some cases, the dopants may not
end up being located in the corners, thus showing less severe corner effects.
In other cases, a far greater number of dopants may end up accumulating at
the corners, thus worsening the corner effects.
Fig. 14: Frequency distribution of nmax (from [17])
Some literature [17] also discusses an inverse corner effect, which refers to
the lowering of carrier density in the corners in lightly doped fins, in
subthreshold regime. As is obvious, this is not an undesirable effect.
FinFET circuits, layouts
Along with efforts at the device level, there have been efforts to use FinFETs
in circuits in an economic way (ie. resulting in a quick TTM (time-to-market)
as well as high yield). To this end, there have been efforts to build tools to
convert existing planar CMOS layouts into FinFET layouts. A FinFET with
multiple fins (N) has an effective device width given by:
( )
fin fin eff
T H N W + 2
When the fins are created using the SIT process, the number of fins created N
is always an even number. It may be necessary to have an odd number of
fins, in order to achieve the desired ratios (ratio of ON resistance), or to
break fins to isolate devices. To create the fins using SIT, and to break fin
loops, it is necessary to add 2 more levels in the fabrication process module.
These are called the fin and the trim levels. A tool called FinGEN has been
developed [4] for converting existing planar designs into FinFET designs, to
add the fin and trim levels. The tool is designed to be automatic, but needs
manual intervention in some cases, eg. in cases where the transistors are
severely sensitive for their functioning, such as SRAM cells.
Ludwig et al reported [18] the conversion of an existing SOI microprocessor
design into a 0.1um FinFET design. The fins were 15nm thick and 70nm high.
Issues with SRAM design were highlighted, because the transistors are highly
sensitive. The schematic of an SRAM cell is shown in Fig 15. The sizing of
the transistors labeled Pg and Cc (and their counterparts on the right side) is
very important, else instead of Bitline_Left writing a bit into the SRAM, the
SRAM may end up changing the voltage at node L in the figure. To see this,
assume L is initially low (hence R is high). If BitLine_High is high, and if the
Wordline is enabled, then there are 2 competing processes trying to affect
node L. The strength of these two competing processes is dictated by the ON
resistances of the transistors labeled Pg and Cc.
20
Fig. 15: Schematic of an SRAM cell (from [4])
Since ON resistance is directly related to Weff, which in turn is directly related
to the number of fins, such a circuit needs careful design. There are some
circuits that need a good ON resistance for good performance (eg. an
inverter), and there are others that need a good ON resistance for basic
functionality. The above circuit is an example of the latter kind. If the desired
ON resistance is not realized, it just wont work.
Rainey et al fabricated a 4-stage inverter chain [19] using FinFETs in 180nm
technology, with Lgate=200nm, TFin=60nm, HFin=100nm, tox=2.2nm and
Vdd=1.5V. Over 300 fins were created. It was also shown that shorter FinFETs
with 140nm gate lengths exhibited severe SCE, and this was attributed to the
fact that it didnt adhere to the rule that the preferred fin thickness should be
about 1/4
th
the gate length.
More recently, Collaert et al fabricated [9] a 41 stage ring oscillator having a
60ps stage delay at Vdd=1.5V, using metal gated FinFETs with 25nm gate
lengths, 10nm fin thickness and 60-80nm fin heights. The pFETs and nFETs
had 92 and 60 fins respectively. It was reported that had selective epitaxy
been used to create RSD, the performance would have been even better due
to lower ON resistance.
Device width quantization
Because Weff varies in integral multiples of 2HFin + TFin, FinFET circuits
inherently have a device width quantization problem [4]. To illustrate this,
suppose HFin and TFin are 30nm and 10nm respectively. Thus, Weff can be
70nm, 140nm, 210nm, etc. This renders it hard to get W/L ratios of say, 2.5
between 2 devices (eg. pFET and nFET in an inverter are usually sized such,
to account for the mobility differences, in order to get equal rise/fall times). It
is not clear how this is tackled in the literature. To cater to the cases where
the fractional W/L ratio requirements are simply due to mobility differences
as in the above example, there have been unpublished proposals to lighten
this requirement by enhancing the mobility of pFETs in an alternate way,
such as fabricating them in a <110> direction.
Another way to solve the problem is to increase the gate length, which is
lithographically controlled and hence doable. However this potentially
reverses the benefits of shrinking.
21
Layout density optimization
Anil et al have come up [20] with ground rules that relate various layout
dimensions, such as fin height and thickness, fin pitch, effective device
width, and design rule margins. Equations giving minimum/maximum values
have been derived, for both direct lithography patterning as well as SIT
technique (spacer lithography). It was concluded that direct lithography puts
more stringent demand on the required fin height, in order to be competitive
with planar CMOS. This is not surprising because it is a known fact that the
SIT technique can help create more fins in the same active area, compared to
direct lithography.
22
Conclusions
FinFETs appear to be the device of choice in sub-50nm designs, because of
their reduced short channel effects (SCE) and relative ease of integration into
existing fabrication processes. They seem well suited to help us stay on track
with Moores law, for a little while longer.
A gate-first method of fabricating FinFETs is advantageous in that it is more
akin to the conventional CMOS process. This is probably the reason why there
is more literature on this method. On the other hand, a gate-last method of
fabricating FinFETs is advantageous from a thermal stability point of view
when introducing metal gates and high-k gate dielectrics.
Tall, thin fins help minimize SCE, but tend to increase series resistance. For
best SCE, keeping manufacturability in mind, the ideal dimensions reported
are a fin thickness of one third the channel length [6]. Tall fin heights are
desirable because they yield higher ON currents (increased Weff), but it gets
more difficult to manufacture them with uniformly steep sidewalls. So a fine
balance needs to be struck.
FinFETs need to be used with metal gates with appropriate work function, for
yielding desired VT. Also, undoped fins need to be used to minimize corner
effects. It was shown that Molybdenum with controlled Nitrogen doping is
suitable for this.
Fabrication techniques need to be improved to create thin fins with uniform
thickness (uniformity across devices) as well as smooth, vertical sidewalls.
These are necessary for consistent and high ON currents.
Also, the parasitic series resistance needs to be brought down to acceptable
levels. People have shown lowered series resistance with raised source-drain
(RSD) using selective epitaxy, and also with high angle S/D implants.
On the modeling front, compact models for FinFETs need to evolve more.
Lastly, self heating problems, which are inherent in SOI devices and not
limited to FinFETs, need to be handled before FinFETs can be adopted on a
large scale.
23
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