EE141- Spring 2003

Lecture 7

Propagation Delay
Power Dissipation

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CMOS Inverter Propagation Delay

VDD

tpHL = f(R on.CL )

= 0.69 RonCL

Vout
Vout ln(0.5)
CL
1 VDD
Ron

0.5
0.36

Vin = V DD
t
RonCL

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 Transient Response
3

2.5
?
2

tp = 0.69 CL (Reqn+Reqp)/2
1.5
(V )
o ut

tpLH tpHL
V

0.5

-0.5
0 0.5 1 1.5 2 2.5
t (sec) -10
x 10

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Design for Performance

Keep capacitances small

Increase transistor sizes
» watch out for self-loading!

Increase VDD (?)

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 Delay as a function of VDD
5 .5

4 .5

4
t (norm alized)

3 .5

3
p

2 .5

1 .5

1
0 .8 1 1 .2 1 .4 1 .6 1 .8 2 2 .2 2 .4
V (V)
DD

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Device Sizing
- 11
x 10
3.8

3.6 (for fixed load)

3.4

3.2
t (sec)

3
p

2.8
Self-loading effect:
2.6 Intrinsic capacitances
dominate
2.4

2.2

2
2 4 6 8 10 12 14
S
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 NMOS/PMOS ratio
-11
x 10
5

tpLH tpHL
4.5

tp β = Wp/Wn
t (sec)

4
p

3.5

3
1 1.5 2 2.5 3 3.5 4 4.5 5
β

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Impact of Rise Time on Delay

0.35

0.3
tpH L (nsec)

0.25

0.2

0.15
0 0.2 0.4 0.6 0.8 1
trise (nsec)

tp = tstep(i) + ηtstep(i-1)

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The Sub-Micron MOS Transistor

Threshold Variations

Subthreshold Conduction

Parasitic Resistances

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Threshold Variations
VT VT

Long-channel threshold Low VDS threshold

VDS
L

Threshold as a function of Drain-induced barrier lowering (DIBL)

the length (for low VDS ) (for low L)

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 Sub-Threshold Conduction
-2
10 The Slope Factor
Linear qVGS
CD
, n = 1+
-4 nkT
10 I D ~ I 0e
Cox
-6
10 Quadratic
S is ∆VGS for ID2/ID1 =10
I D (A)

-8
10

-10 Exponential
10

-12
VT Typical values for S:
10
0 0.5 1 1.5 2 2.5 60 .. 100 mV/decade
VGS (V)

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Sub-Threshold ID vs VGS
qVGS qV
 − DS 
I D = I 0e nkT 1 − e kT



 

VDS from 0 to 0.5V

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 Sub-Threshold ID vs VDS
qVGS qVDS
 − 
I D = I 0 e nkT 1 − e kT

(
 1 + λ ⋅ VDS )
 

VGS from 0 to 0.3V

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Power Dissipation

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Where Does Power Go in CMOS?

• Dynamic Power Consumption

Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors

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Dynamic Power Dissipation

Vdd

Vin Vout

CL

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Not a function of transistor sizes!

Need to reduce CL, Vdd, and f to reduce power.

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Modification for Circuits with Reduced Swing

Vdd
Vdd

Vdd -Vt

CL

E0 = C L • V dd • ( V dd – Vt )
→1

Can exploit reduced swing to lower power

(e.g., reduced bit-line swing in memory)
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Adiabatic Charging

2 2

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 Adiabatic Charging

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Node Transition Activity and Power

Consider switching a CMOS gate for N clock cycles
E N = C L • V d d2 • n (N )

EN : the energy consumed for N clock cycles

n(N): the number of 0->1 transition in N clock cycles
EN n (N ) 2
Pa vg = lim -------- • fclk =  lim ------------  • C • Vdd • f clk

N→∞ N N→∞ N  L

n(N )
α0 → 1 = lim ------------
N→∞ N

Pav g = α0 V 2 f
→ 1 • L • dd • clk
C

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 Short Circuit Currents
Vdd

Vin Vout

CL

0.15

0.10
IVDD (mA)

0.05

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

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How to keep Short-Circuit Currents Down?

Short circuit current goes to zero if tfall >> trise,

but can’t do this for cascade logic, so ...
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 Minimizing Short-Circuit Power
8

7
Vdd =3.3
6

5
Vdd =2.5
norm
4
P

2
Vdd =1.5
1

0
0 1 2 3 4 5
t /t
sin sout

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Leakage
Vdd

Vout

Drain Junction
Leakage

Sub-Threshold
Current

Sub-threshold current one of most compelling issues

in low-energy circuit design!
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 Reverse-Biased Diode Leakage
GATE

p+ p+
N

Reverse Le akage Current

+
V
- dd

IDL = JS × A

JS = 10-100 pA/µµm2 at 25 deg C for 0.25µ

µm CMOS
JS doubles for every 9 deg C!

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Subthreshold Leakage Component

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 Static Power Consumption
Vdd

Istat
Vout

CL
Vin =5V

Pstat = P(In=1).Vdd . Istat

Wasted energy …
Should be avoided in most cases,
but could help reducing energy in others (e.g. sense amps)
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Principles for Power Reduction

Prime choice: Reduce voltage!
» Recent years have seen an acceleration in
supply voltage reduction
» Design at very low voltages still open
question (0.6 … 0.9 V by 2010!)

Reduce switching activity

Reduce physical capacitance

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 Next Lecture

Optimizing for Performance and Power

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