Slua 371

Application Report
SLUA371 – September 2006
Closed-Loop Compensation Design of a Synchronous

Switching Charger Using bq2472x/3x
Lingyin Zhao........................................................................................................ PMP Portable Power
ABSTRACT
Design of the loop compensator is one of the key challenges in the circuit design of a
switching charger. This application report presents the internal control loop operation of
the bq2472x/3x as well as the external compensator design guideline. The modeling of
the nonlinear behavior of a switching charger is based on the state space average
model. A design example based on practical specifications is demonstrated.
Contents
1 Buck-Type Charger Power Stage Small-Signal Model ........................................ 2
2 bq2472x/3x Control-Loop Model and Compensation Design ................................. 6
3 Design Example .................................................................................... 9
4 Reference .......................................................................................... 19
List of Figures
1 The Power Stage of a Buck-Type Charger ..................................................... 2
2 Three-Terminal Model of a PWM Switch in CCM .............................................. 2
3 Control-to-Output Small-Signal Model in CCM ................................................. 3
4 Three-Terminal Model of a PWM Switch in DCM .............................................. 4
5 Control-to-Output Small-Signal Model in DCM ................................................. 5
6 PWM and Error Amplifiers Block of bq2472x/3x................................................ 6
7 Simplified Control-Loop Block Diagram.......................................................... 7
8 A Typical Bode Plot of the Converter Control-to-Output Gain Under CCM Conditions ... 8
9 A Type III Compensator ........................................................................... 8
10 Bode Plot of a Typical Type III Compensator ................................................... 8
11 Control-to-Output-Voltage Transfer Function .................................................. 10
12 Control-to-Charge-Current Transfer Function ................................................. 11
13 Control-to-Input-Current Transfer Function .................................................... 12
14 Transfer Function of Gvd, the Compensator and the Entire Voltage Loop Gain .......... 13
15 Single-Cell Li-Ion Battery Equivalent Circuit Model (18560)................................. 14
16 Output-Voltage Loop Gain TV (CCM) ........................................................... 15
17 Charge-Current Loop Gain Tis (CCM) .......................................................... 16
18 Input-Current Loop Gain Tii (CCM) .............................................................. 17
19 Output-Voltage Loop Gain TV (DCM) ........................................................... 18
20 Input-Current Loop Gain Tii (DCM) ............................................................. 19
SLUA371 – September 2006 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x 1
Submit Documentation Feedback
www.ti.com
Buck-Type Charger Power Stage Small-Signal Model
1 Buck-Type Charger Power Stage Small-Signal Model

A typical stage of a synchronous buck-type switching battery charger is shown in Figure 1.
Q1
VIN RL L IL RSNS IS VO
RC1 RC2 ZL
Q2
C1 C2
Figure 1. The Power Stage of a Buck-Type Charger
The small-signal model is obtained from the relationships among the perturbation in average terminal
quantities at a given dc operating point. The model is different under continuous conduction mode (CCM)
and discontinuous conduction mode (DCM).
1.1 Continuous Conduction Mode (CCM) Small-Signal Model

The average values of the switch network terminal waveforms can be determined in terms of the converter
state variables and the converter independent inputs. The basic assumption is made that the natural time
constants of the converter network are much longer than the switching period Ts. This assumption
coincides with the requirement for small switching ripple. The resulting averaged model predicts the
low-frequency behavior of the system, while neglecting the high-frequency switching harmonics [1]. The
three-terminal model for a PWM switch network in CCM is illustrated in Figure 2.
Q1 Vap
ˆ
d
a c D
a c
^
ICd 1 1 D
Q2
p p
(a) a PWM Switch (b) Small-Signal Model
Figure 2. Three-Terminal Model of a PWM Switch in CCM
To perform the CCM small-signal analysis, the PWM switch in the buck converter is substituted with the
three-terminal model in CCM and Vin is shorted, as shown in Figure 3.
2 Closed-Loop Compensation Design of a Synchronous Switching Charger Using bq2472x/3x SLUA371 – September 2006
www.ti.com
Vin
d̂
î i D RL L î L RSNS î s v̂ o
RC1 RC2
1 D ZL
C1 C2
Figure 3. Control-to-Output Small-Signal Model in CCM
The open-loop control-to-output-voltage transfer function is given as:

ƞ
Vo
ǒws z1
)1 Ǔ ǒws z2
)1 Ǔ
G (s) + +V Z
vd ƞ in L l3s 3 ) l 2s2 ) l 1s ) l 0
d (1)
Compared to a regular buck-type converter, this topology results in one more zero and one more pole,
both at high frequencies under normal conditions.
The open-loop control-to-charge-current transfer function is given as:
ƞ
is
ǒws z1
)1 Ǔ ǒws z3
)1 Ǔ
G (s) + +V
isd ƞ in l 3s 3 ) l 2s2 ) l1s ) l 0
d (2)
The open-loop control-to-input-current transfer function is given as:
ƞ
i a 2s2 ) a 1s ) 1
G (s) + ƞi + I ) V
iid L in l3s 3 ) l 2s2 ) l 1s ) l 0
d (3)
in which,
w z1 + 1
RC1 C1
(4)
w z2 + 1
RC2 C2
(5)
w z3 + 1
ǒRC1 ) ZLǓ C2
(6)
l 3 + ƪRC2 Z L ) ǒRSNS ) R C1ǓǒRC2 ) Z LǓƫ L C1 C2
(7)
l 2 + ǒRL ) RC1ǓƪR C2 Z L ) ǒRSNS ) RC1Ǔ ǒR C2 ) Z LǓƫ C1 C2 ) ǒZ L ) RSNS ) R C1Ǔ
L C1 ) ǒRC2 ) Z LǓ ǒL * R 2C1 C 1Ǔ C2
(8)
l 1 + ƪRC2 Z L ) ǒRSNS ) R LǓǒRC2 ) Z LǓƫ C2 ) ǒZ L ) R SNS ) R LǓ ǒRL ) RC1Ǔ C 1 ) L * R2L C1
(9)
l 0 + Z L ) RSNS ) RL (10)
a 2 + ƪRC2 Z L ) ǒRSNS ) R C1Ǔ ǒRC2 ) Z LǓƫ C1 C2
(11)
a 1 + ǒZ L ) RSNS ) RC1Ǔ C1 ) ǒR C2 ) Z LǓ C2
(12)
Approximately, Gvd (s) and Gisd (s) can be presented as
www.ti.com
ZL
ǒws
z1
Ǔǒ
) 1 ws ) 1
z2
Ǔ
G vd(s) [ Vin
Z L ) RSNS ) R L
ǒws ) w s Q ) 1Ǔǒws ) 1Ǔ
2
2
0 0 p1
(13)
1
ǒws
z1
Ǔǒ
) 1 ws ) 1
z3
Ǔ
G isd(s) [ Vin
Z L ) RSNS ) R L
ǒws ) w s Q ) 1Ǔǒws ) 1Ǔ
2
2
0 0 p1
(14)
in which,
ǒZL ) R SNS ) R LǓ ǒC1 ) C2Ǔ
w p1 +
ƪRC2 Z L ) ǒRSNS ) R C1Ǔ ǒRC2 ) Z LǓƫ C1 C2
(15)
w0 + 1
ǸǒL C 1 ) C 2Ǔ
(16)
Q+ 1
w0 ǒR L ) R C1Ǔ ǒC1 ) C 2Ǔ
(17)
1.2 Discontinuous Conduction Mode (DCM) Small-Signal Model

Under DCM conditions, assume the dc voltage gain is
V
M+ o
V in (18)
The duty cycle is given by
D+ 2
(M*2)2
*1
Ǹƪ K
(M * 2) 2
M2
*1 ƫ
M2 (19)
in which,
2L f s
K+
Vo
Io (20)
The three-terminal model for a PWM switch network in CCM is illustrated in Figure 4.
v̂ ac
gi
Q1
a c
a c
ki d̂
gf v̂ac ko d̂ go v̂cp
Q2
p p
(a) a PWM Switch (b) Small-Signal Model
Figure 4. Three-Terminal Model of a PWM Switch in DCM
www.ti.com

2I a
ki +
D (21)
2I p
ko +
D (22)
Ia
gi +
Vac (23)
Ip
go +
Vcp
(24)
2I p
gf +
Vac (25)
To perform the DCM small-signal analysis, the PWM switch in the buck converter is substituted with the
three-terminal model in DCM and Vin is shorted, as shown in Figure 5.
gi
k i d̂ RL L îL RSNS îs v̂ o
RC1 RC2
îi gf kod̂ go ZL
C1 C2
Figure 5. Control-to-Output Small-Signal Model in DCM
In a buck converter operating in DCM, the following equations can be obtained:

gi + D
2
2L f s (26)
2I oM
ki +
D (27)
2I o
k d + ki ) ko +
D (28)
1 V
r+ + o (I * M)
gi ) go ) gf Io (29)
The open-loop, control-to-output-voltage transfer function is given as:
ƞ
vo
ǒws z1
)1 Ǔ ǒws z2
)1 Ǔ
G vd_DCM(s) + ƞ + kd ZL
l3s 3 ) l 2s2 ) l 1s ) l 0
d (30)
The open-loop, control-to-input-current transfer function is given as:
ƞ
i e 2s 2 ) e 1s ) 1
G iid_DCM(s) + ƞi + k i * g i kd r ) gi Kd r
l3s 3 ) l2s 2 ) l 1s ) l 0
d (31)
in which,
L C1 C2
g3 + r
ƪR C2 Z L ) ǒRSNS ) RC1ǓǒR C2 ) Z LǓƫ
(32)
www.ti.com
bq2472x/3x Control-Loop Model and Compensation Design

C1 C2
g2 + r
ƪRC2 Z L ) ǒR SNS ) R C1ǓǒRC2 ) Z LǓƫ ) R C1 R SNS ǒR C2 ) Z Lǋ
) Lr ƪǒR SNS ) R C1 ) Z LǓ C1 ) ǒRC2 ) Z LǓ C2ƫ
(33)
C
g 1 + r1 ƪǒRL ) rǓ ǒR SNS ) R C1 ) ZLǓ ) RC1 RSNS ) RC1 Z Lƫ
ƪǒR L ) r ) RSNSǓ ǒR C2 ) Z LǓ ) R C2 Z Lƫ ) Lr
(34)
R ) r ) R SNS ) Z L
g0 + L r (35)
e 2 + C1 C2 ƪRC2 Z L ) ǒR SNS ) R C1ǓǒRC2 ) Z LǓƫ
(36)
e 1 + ǒRSNS ) RC1 ) Z LǓ C 1 ) ǒR C2 ) Z LǓ C2
(37)
2 bq2472x/3x Control-Loop Model and Compensation Design
2.1 bq2472x/3x Control-Loop Model

The PWM and error amplifiers block of bq2472x/3x is illustrated in Figure 6. It consists of three feedback
loops: output-voltage loop, charge-current loop, and input-current loop (DPM loop). However, only one of
them dominates at one time. The simplified control-loop block diagram is depicted in Figure 7.
Figure 6. PWM and Error Amplifiers Block of bq2472x/3x
www.ti.com
v̂ i v̂ iˆ iˆ
Power Stage o s i
d̂
G vd, G isd, G iid
dˆ
v̂ c
FM -A(s ) FG
Figure 7. Simplified Control-Loop Block Diagram
In Figure 7, FG is the feedback gain whose value depends on which loop is operating.
For the output-voltage loop,
ȡ1 6+1
6
(for 3 * cell)
FG + g rd g v + 1 ȥ 6 + 0.75 (for 4 * cell)
Ȣ8
(38)
in which grd and gv are the resistor divider gain and the voltage amplifier gain, respectively. For the
charge-current loop,
FG + R SNS g SR T damp1 + 40 R SNS T damp1
(39)
in which RSNS and gSR are the charge-current-sense resistor value and the charge-current amplifier gain,
respectively. Tdamp1 is the transfer function of the network added to damp the high-frequency harmonics
for this loop. It contains a pole at 60 kHz and another at 150 kHz.
T damp1(s) + 1
ǒ s Ǔǒ s
whfp1 ) 1 whfp2 ) 1 Ǔ (40)
For the DPM loop,
FG + R SNS g AC T damp2 + 40 R SNS T damp2
(41)
in which RSNA and gAC are the adapter input current-sense resistor value and the input current amplifier
gain, respectively. Tdamp2 is the transfer function of the network added to damp the high-frequency
harmonics for this loop. It contains a pole at 60 kHz and another at 150 kHz.
T damp2(s) + T damp1(s)
(42)
In Figure 7, A(s) is the compensator transfer function and FM is the control voltage to duty-cycle transfer
function. To generate a PWM drive signal, the control voltage Vc is compared with a ramp waveform, as
shown in Figure 6. The ramp peak voltage Vp = Vcc/10. Thus, the value of FM can be obtained as:
FM + 1
Vp
(43)
The three loop gains are given by
T v + G vd FG A(s) FM (44)
T is + G isd FG A(s) FM (45)
T ii + G iid FG A(s) FM (46)
www.ti.com

2.2 bq2472x/3x Compensator Design
From Equation 13 and Equation 14, it can be seen that the power stage CCM open-loop transfer functions
are basically a three-pole-two-zero system. A typical Bode plot of the converter control to output gain
under CCM conditions is shown in Figure 8. However, it can be simplified as a double-pole system
because ωz1, ωz2, and ωp1 are normally located at high frequencies where the average model is not valid
any longer.
Magnitude - dB
f - Frequency
Figure 8. A Typical Bode Plot of the Converter Control-to-Output Gain Under CCM Conditions
A Type III compensator is a promising candidate for this application. The typical realization of a Type III
compensator is demonstrated in Figure 9. Its typical frequency response is depicted in Figure 10.
C1_com R 3_com
C 2_com R 2_com
C 3_com EAI
FBO
EAO
R 1_com
Figure 9. A Type III Compensator
Integrator
Magnitude - dB
Pole 1 Pole 2
Zero 1 Zero 2
f - Frequency
Figure 10. Bode Plot of a Typical Type III Compensator
www.ti.com
Design Example
An integrator is needed for a high dc gain. Two zeroes need to be put below the loop gain crossover
frequency fc to compensate the excessive phase lag due to the integrator and the power stage complex
pole pair. In order to attenuate the high-frequency noise, two high frequency poles are added to ensure
the magnitude of the loop gain keeps decreasing after the 0-dB crossover. The two poles must be placed
below half of the switching frequency.
The transfer function of the compensator is given as:
ǒs s Ǔǒ
wz1_com ) 1 wz2_com ) 1 Ǔ
A(s) + K
ǒ
s w s )1 w s )1
p1_com
Ǔǒ p2_com
Ǔ
(47)
where
K+ 1
R 1_com ǒC1_com ) C3_comǓ (48)
w z1_com + 1
R3_com C1_com
(49)
w z2_com + 1
ǒR1_com ) R2_comǓ C2_com
(50)
w p1_com + 1
R2_com C2_com
(51)
w p2_com + 1
C1_com C3_com
R3_com
C1_com)C3_com
(52)
3 Design Example
3.1 Specifications
Vin = 19 V, L = 10 µH, C1 = C2 = 20 µF, RSNS = RSNA = 10 mΩ, RC1 = RC2 = 10 mΩ, RL = 20mΩ,
Vbat = 9 V – 12.6 V (3s2p), Ichrg = 4 A, fs = 300 kHz
www.ti.com
Design Example
3.2 Power Stage Open-Loop Transfer Functions (CCM)
The transfer functions of the converter in CCM are illustrated in Figure 11, Figure 12, and Figure 13.
60
ZL = 17.8 W
Magnitude - dB 20
ZL = 2.25 W
-20
-60
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(a) Gain
180
Phase - Deg
ZL = 17.8 W
0
ZL = 2.25 W
-180
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(b) Phase
Figure 11. Control-to-Output-Voltage Transfer Function
www.ti.com
Design Example
100
ZL = 2.25 W
Magnitude - dB 0
ZL = 17.8 W
-100
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(a) Gain
100
ZL = 17.8 W
Phase - deg
ZL = 2.25 W
0
-180
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(b) Phase
Figure 12. Control-to-Charge-Current Transfer Function
www.ti.com
Design Example
100
20 ZL = 2.25 W
Magnitude - dB 0 ZL = 17.8 W
-20
-100
1 10 100 1k 10 k 100 1M
f - Frequency - Hz
(a) Gain
180
ZL = 17.8 W
Phase - deg
ZL = 2.25 W
-180
1 10 100 1k 10 k 100 1M
f - Frequency - Hz
(b) Phase
Figure 13. Control-to-Input-Current Transfer Function
3.3 Compensator Design Procedure

From the preceding calculation, the following parameters can be obtained:
w z1 + 1 + 796 kHz
RC1 C1
(53)
w z2 + 1 + 796 kHz
RC2 C2
(54)
w0 + 1 + 8 kHz
ǸǒL C 1 ) C 2Ǔ
(55)
Place the two compensator zeros before the resonant frequency of the converter (f0) to improve the DCM
stability.
www.ti.com
Design Example
Select
w z1_com + 2p 0.5 f 0 + 25 kHz
(56)
w p1_com + wp2_com + 1 2pf s + 943 kHz
2 (57)
Because ωz1, ωz2 are higher than half of the switching frequency, place the two high-frequency poles at
0.5fs:
w p1_com + wp2_com + 1 2pf s + 943 kHz
2 (58)
Set a crossover frequency fc (voltage loop) of 10 kHz – 20 kHz. Select K = 2500 to make fc≈ 15 kHz with
about 60° phase margin. Normally, a phase margin greater than 40° is desirable. The transfer function of
Gvd, the compensator and the entire voltage loop gain Tv are shown in Figure 14.
80
TV(S)
Gvd(S)
Magnitude - dB
A(S)
-80
1 10 100 1k 10 k 100 1M
f - Frequency - Hz
(a) Gain
180
A(S)
Phase - deg
TV(S)
Gvd(S)
-180
1 10 100 1k 10 k 100 1M
f - Frequency - Hz
(b) Phase
Figure 14. Transfer Function of Gvd, the Compensator and the Entire Voltage Loop Gain
www.ti.com
Design Example
Assuming R1_com = 200k, based on equations (48)–(52), the preliminary compensator component values
can be determined as:
R1_com = 200kΩ, R2_com = 7.5kΩ, R3_com = 20kΩ, C1_com = 2000pF, C2_com = 130pF, C3_com = 51pF.
3.4 Check Loop Gains With Various Loads
3.4.1 Li-Ion Battery Equivalent Circuit Model

Figure 15 shows the typical Li-ion battery equivalent circuit model used for the small-signal analysis. lt is
approximately correct for charged state from 100% of SOC to 20% of SOC. Impedance varies from
manufacturer to manufacturer up to two times and from cell to cell up to ±15%. For a discharged state
below 20% of SOC, the impedance starts to increase rapidly. The particular value the impedance reaches
depends on manufacturer, but it can be roughly modeling by multiplying R1 and R2 by 3.
R hf R1 R2
R SER L C1 C2
NOTE: R1 = 13.77 mW, C1 = 0.337672 F, R2 = 47.15 mW,

C2 = 1.79935 F, RSER = 65.18 mW, Rhf = 5.8 W, L = 0.637 mH
NOTE: R1=13.77 mΩ, C1=0.337672 F, R2=47.15 mΩ, C2=1.79935 F, RSER= 65.18 mΩ, Rhf=5.8 Ω, L=0.637 µH
Figure 15. Single-Cell Li-Ion Battery Equivalent Circuit Model (18560)
3.4.2 CCM Loop Gains With Various Loads (Including Battery Load)
Plot the output-voltage loop gain, and check the stability and bandwidth with a 3s2p battery load, as
shown in Figure 16.
Plot the charge-current and input-current loop gains, and check the stability and bandwidth. The entire
charge-current and input-current loop gains Tis and Tii are shown in Figure 17 and Figure 18, respectively.
www.ti.com
Design Example
100
ZL = 17.8 W
Magnitude - dB
ZL =2.25 W
0
ZL = Zbat(s)
-100
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(a) Gain
100
Phase - deg
ZL = 17.8 W
0
ZL =2.25 W
ZL = Zbat(s)
-100
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(b) Phase
Figure 16. Output-Voltage Loop Gain TV (CCM)
www.ti.com
Design Example
Figure 17. Charge-Current Loop Gain Tis (CCM)
www.ti.com
Design Example
100
ZL = Zbat(s)
ZL =2.25 W
Magnitude - dB
0
ZL = 17.8 W
-100
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(a) Gain
180
ZL = 17.8 W
Phase - deg
ZL =2.25 W
ZL = Zbat(s)
-180
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(b) Phase
Figure 18. Input-Current Loop Gain Tii (CCM)
www.ti.com
Design Example
3.5 Check Loop Gains Under DCM Condition
Plot the output-voltage and input-current loop gains, and check the stability and bandwidth. The entire
output-voltage and input-current loop gains Tv and Tii are shown in Figure 19 and Figure 20, respectively.
100
IO = 40 mA
ZL =315 W
IO = 700 mA
Magnitude - dB
ZL = 17.8 W
IO = 40 mA
ZL = Zbat(s)
-100
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(a) Gain
180
IO = 40 mA
ZL = Zbat(s)
Magnitude - dB
IO = 700 mA
0 ZL = 17.8 W
IO = 40 mA
ZL =315 W
-180
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(a) Gain
Figure 19. Output-Voltage Loop Gain TV (DCM)
www.ti.com
Reference
50
IO = 40 mA
ZL =315 W
IO = 700 mA
ZL = 17.8 W
0
Magnitude - dB IO = 40 mA
ZL = Zbat(s)
-100
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(a) Gain
180
Magnitude - dB
IO = 700 mA
0
IO = 40 mA ZL = 17.8 W
ZL =315 W
IO = 40 mA
ZL = Zbat(s)
-180
1 10 100 1k 10 k 100 k 1M
f - Frequency - Hz
(b) Phase
Figure 20. Input-Current Loop Gain Tii (DCM)
From the transfer function Bode plots obtained, it is seen that this compensator design offers adequate
phase margins and bandwidths for all three loops. If not, the parameters (K, ωz1_com, ωz2_com) can be
adjusted to get a reasonable design.
4 Reference
1. R. W. Erickson, D. Maksimvić, Fundamentals of Power Electronics (Second Edition), Kluwer Academic
Publishers, Sixth Printing 2004.
2. Fred C. Lee, Modeling and Control Design of DC/DC Converters, CPES Lecture Notes, Virginia Tech,
2004.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless
Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265
Copyright  2006, Texas Instruments Incorporated

Slua 371

Загружено:

Сведения о документе

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

Slua 371

Загружено:

Авторское право:

Доступные форматы

Application Report

SLUA371 – September 2006

Closed-Loop Compensation Design of a Synchronous

Buck-Type Charger Power Stage Small-Signal Model

1 Buck-Type Charger Power Stage Small-Signal Model

Figure 1. The Power Stage of a Buck-Type Charger

1.1 Continuous Conduction Mode (CCM) Small-Signal Model

Figure 2. Three-Terminal Model of a PWM Switch in CCM

Buck-Type Charger Power Stage Small-Signal Model

Figure 3. Control-to-Output Small-Signal Model in CCM

The open-loop control-to-output-voltage transfer function is given as:

Buck-Type Charger Power Stage Small-Signal Model

1.2 Discontinuous Conduction Mode (DCM) Small-Signal Model

Figure 4. Three-Terminal Model of a PWM Switch in DCM

Buck-Type Charger Power Stage Small-Signal Model

k i d̂ RL L îL RSNS îs v̂ o

Figure 5. Control-to-Output Small-Signal Model in DCM

In a buck converter operating in DCM, the following equations can be obtained:

bq2472x/3x Control-Loop Model and Compensation Design

2 bq2472x/3x Control-Loop Model and Compensation Design

2.1 bq2472x/3x Control-Loop Model

Figure 6. PWM and Error Amplifiers Block of bq2472x/3x

bq2472x/3x Control-Loop Model and Compensation Design

bq2472x/3x Control-Loop Model and Compensation Design

Figure 11. Control-to-Output-Voltage Transfer Function

Figure 12. Control-to-Charge-Current Transfer Function

Figure 13. Control-to-Input-Current Transfer Function

3.3 Compensator Design Procedure

3.4 Check Loop Gains With Various Loads

3.4.1 Li-Ion Battery Equivalent Circuit Model

NOTE: R1 = 13.77 mW, C1 = 0.337672 F, R2 = 47.15 mW,

Figure 15. Single-Cell Li-Ion Battery Equivalent Circuit Model (18560)

Figure 16. Output-Voltage Loop Gain TV (CCM)

Figure 17. Charge-Current Loop Gain Tis (CCM)

Figure 18. Input-Current Loop Gain Tii (CCM)

Figure 19. Output-Voltage Loop Gain TV (DCM)

Figure 20. Input-Current Loop Gain Tii (DCM)

Mailing Address: Texas Instruments

Copyright  2006, Texas Instruments Incorporated

Вам также может понравиться