EL 426 – Lab Assignment – 1

Date : 18-01-2006

Students of Digital System Architecture (EL – 426) have to carry out following
exercises as per their lab assignments. All the exercise should be coded in Verilog
HDL programming language, and simulated using Xilinx ISE toolset. Target
device is SPARTAN 3 XC3S300PQ208

1. (a) Design a 4:1 Multiplexer using case statement.

(b) Design a positive edge triggered D flip-flop using behavioral coding style
of Verilog.

The submission day for this exercise will be 31 – 01 – 2006.

2. (a) Design a 3:8 decoder.

(b) Design a 4 – bit counter using the flip-flop that has been designed in
previous exercise.

The submission day for this exercise will be 06 – 02 – 2006.

3. Design a simplified version of ALU in Verilog which can perform following

operations:
Arithmetic operations:
ADD, SUBTRACT, MULTIPLICATION

Logical Operations:
AND, OR, NAND, NOR, XOR

The submission day for this exercise will be 20– 02 – 2006.

4. Design a FIFO of length of 16 storage spaces, each of location is 16 – bit

long.

The submission day for this exercise will be 27– 02 – 2006.

5. Design an elevator controller which can control the elevator of 8 storied

building. Design a FSM for the same. Write the Verilog code for the same
FSM.

The submission day for this exercise will be 06 – 03 – 2006.

Submission Report:

• Please maintain a separate Lab Book for the course, as it would be

a part of evaluation.
• The TAs will check the simulation results in the lab.

At the end of exercise, all the students have to produce a brief report which
comprises of following three things:

1. Description of the system that has been designed along with the RTL
diagram of the system.
2. Synthesis results and Synthesis report for each exercise. A particular
emphasis should be given on timing report and area report.
3. Analyses of work that had been done, along with the any comments and
observation done by students.

PG M Tech First Year Students

1. Getting acquainted with the Xilinx ISE tool set. Along with it, modifying
the RTL code of “Ridiculously Simple Computer [RiSC]” [designed last
semester] compatible to Xilinx synthesizable constructs.
2. Importing the modified design to Xilinx ISE using Coregen. Will be
explained in the lab
3. Observing and analyzing various synthesis results.
4. For Mtech the deadline for submissions of lab assignments is 20-02-2006

Resources for DSA course in the folder of Prof. Rahul Dubey

[1] Evita Verilog Tutorial.

[2] Xilinx ISE 8.1 Quick Start Guide.
[3] Xilinx XST document related to synthesis.