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JAZELLE TECHNOLOGY

w w w . a r m . c o m

For Java Applications


In the rapidly developing market for Java enabled appliances, ARM Jazelle technology offers a unique combination of high performance, low system cost and low power demand, that cannot be matched by JIT compilation, coprocessor or dedicated Java-processor methods. ARM Jazelle technology provides an extension to the worlds leading 32-bit embedded RISC architecture, enabling ARM processors to execute Java bytecode directly in hardware and delivering unparalleled Java performance on the ARM architecture. Platform developers now have the freedom to run Java applications alongside established OS, middleware and application code all on a single processor.

Typical Jazelle Technology Applications


Wireless Voice handset, smartphone, communicator and PDA devices with connection to Java-enabled m-commerce, games or information services Home Entertainment Set-top box, home gateway and internet appliances offering Java-enabled shopping, banking, e-commerce, games and information services Home Automation Intelligent appliances, building management systems, security, heating/cooling Automotive Driver information, delivery of local guides and information Audio / video entertainment systems

Features
High-efficiency Java bytecode execution, >1000 Caffeine Marks @ 200MHz Ultra-low Java system cost Low power consumption for battery operated wireless embedded devices Single chip MCU, DSP and Java solution No duplication of on-chip memory, bussing, debug or trace resources ARM support code causes no increase in VM size Java JIT compiler performance without the disadvantages Integrated into a number of ARM CPU cores Complete development kit including documentation and reference Run existing OS and middleware Supported by leading OS Supports leading Java run-times Rapid ASIC or ASSP integration with reduced time-to-market

Jazelle Technology Enabled Cores


1 Subject to compile overhead 2 Plus RAM cache

ARM has integrated Jazelle technology into three cores: the ARM1026EJ-S core, the ARM926EJ-S core and the ARM7EJ core, to provide a fully compatible roadmap for Jazelle technologyenabled products.

Performance Without Penalty


High Performance
Jazelle technology offers significantly improved performance when compared to typical software JVMs. This improvement is achieved by accelerating some 95% of executed bytecodes directly in Jazelle hardware, while less frequently used bytecodes are supported with highly optimized sequences of ARM instructions. This delivers a performance figure of 6.0 CM/MHz representing more than 1000 CaffeineMarks in a typical 200MHz 0.18m reference implementation. without the associated penalties. A JIT compiler typically consumes a memory footprint of 100 KBytes and then demands RAM cache as the compiled code expands by a factor of up to 8 times.

The ARM1026EJ-S macrocell is a fully synthesizable processor featuring extensive 64-bit internal bussing combined with configurable instruction and data caches, configurable tightly coupled memories (TCM), support for parity protection on SRAM arrays, memory management and protection units (MMU and MPU). It also includes a vector interrupt controller interface, advanced vector floating point support and dual 64/32-bit configurable AMBA AHB system interfaces. The ARM1026EJ-S core implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier, capable of single cycle MAC operations. The ARM926EJ-S soft macrocell is a fully

Low Power Consumption


The Jazelle technology-enabled core uses 87% less energy per CaffeineMark than an equivalent non-accelerated ARM core. This figure is at least 10 times better than co-processor solutions and far less than JIT compilation techniques that are CPU intensive with correspondingly higher power demands.

Low Silicon Cost


ARM Jazelle technology has been engineered for minimum system cost. The hardware bytecode decoder logic is implemented in less than 12k gates much smaller than dedicated processors or co-processors that typically consume 60k to 100k gates. Similarly, Jazelle does not require the additional memory resources demanded by JIT techniques. Jazelle achieves a single-chip MCU, DSP and Java capable solution that allows full reuse of all on-chip memory, bussing, debug and trace resources.

Ease of System Integration


Jazelle technology is fully integrated into the industry-leading ARM RISC architecture and is completely compatible with the ARM interrupt and exception model giving easy design and integration with existing operating systems, Java run-times, middleware and applications. These factors, together with rapid single processor ASIC or ASSP integration, allow a short time-to-market and make Jazelle technology the ideal solution for phones, appliances and home-gateway products.

synthesizable, high-performance 32-bit RISC processor comprising a Jazelle technologyenhanced processor core, instruction and data caches, tightly coupled memory (TCM) interfaces, memory management unit (MMU), and separate instruction and data AMBA AHB bus interfaces. The size of the instruction and data cache, and instruction and data TCMs can all be independently selected, providing complete flexibility and enabling the ARM926EJ-S solution to be tailored to specific application needs. The ARM7EJ solution is a compact CPU without cache memory, specifically designed for applications demanding the lowest power consumption and where absolute performance is less critical. It has a memory interface identical to that of the ARM7TDMI-S, and features an enhanced multiplier design for improved DSP performance. Ideal for Java-enabled voice handsets, intelligent appliances and home automation applications.

Compact Memory Footprint


The Jazelle technology support code replaces part of the standard JVM code without increasing the overall size of the virtual machine. This extraordinary level of efficiency, combined with the minimal gate count, makes Jazelle technology ideal for products where low system cost is of paramount importance. Jazelle technology acceleration of Java execution approaches the performance levels achieved with just-in-time (JIT) compilation techniques but

Real-Time Performance
Applications like home gateway and phone solutions demand excellent real-time performance from a processor to run the network protocol software and middleware. The Jazelle architecture extensions enable the processor to maintain fast interrupt response and provide real-time performance.

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The Jazelle Technology/Virtual Machine Interface


Jazelle technology-enabled cores are complemented by Jazelle Support Code that manages the interface between the core hardware, the virtual machine and the operating system. bytecode, to the capability of the

Product Roadmap
The Jazelle Support Code provides a simple, progressive method for integrating Jazelle technology into any system. The VTK support code achieves excellent levels of Java performance with non-Jazelle cores by using software Java acceleration. When a Jazelle enabled core with hardware Java acceleration is targeted, then the JTEK version of the support code is used to enable maximum Java performance. This permits a phased approach where by existing designs can be transferred to the full benefits of Jazelle technology.

Java Application
Remote Native Network Graphics Methods Methods

Native Application

processor, together with a new Java state. When presented with Java bytecode, the Jazelle Support Code switches the processor into Java state using a dedicated branch instruction. In Java state, the processor reassigns several ARM registers to accommodate Jazelle machine state and Java operands ensuring compatibility with existing

JTEK Porting Guide

Standard Java Environment: KVM, CVM...


Verifier Class Loader Garbage Collector Process Manager Memory Manager

Native OS

Instruction TCM Interface Instruction Cache MMU/MPU

ETM10C Interface

Data TCM Interface Data Cache MMU/MPU

Jazelle Support Code Jazelle Accelerated ARM Processor

ARM1026EJ-S core

ARM1026EJ-S

Write buffer Control Logic and Bus Interface Unit

The Jazelle Support Code, which will only be available to Sun licensees, permits the virtual machine to access the full benefits of Jazelle technology by replacing the interpreter and invoker methods within the VM. The support code is highly optimized for both speed and size and greatly simplifies the task of porting a virtual machine to the Jazelle platform. The Jazelle Technology Enabling Kit (JTEK) comprises all the necessary support code source, documentation and tools that are required to integrate Jazelle technology into a virtual machine and operating system. JTEK is available for CLDC and CDC, and can be ported to all popular OS. ARM processors traditionally support two instruction sets; ARM state, with 32-bit instructions and Thumb state which compresses the most commonly used instructions into 16-bit format. The Jazelle technology extends this concept by adding a third instruction set, Java

operating systems, interrupt handlers and exception code. Up to four stack elements are maintained in ARM registers to reduce memory access to a minimum; this is an important contributor to the excellent performance of the processor when executing a Java application. Stack spill and underflow is handled automatically by the hardware. Minimum interrupt latency is maintained across both ARM state and Java state. An interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. Since bytecode execution can be restarted, no special provision has to be made for handling interrupts while executing bytecode whether in hardware or software.

VFP10 Interface

VIC Interface

AMBA AHB Interface


Instruction Data

Instruction TCM Interface Instruction Cache MMU

ETM9 Interface

Data TCM Interface Data Cache MMU

ARM9EJ-S core

ARM926EJ-S

Write buffer Control Logic and Bus Interface Unit

Coprocessor Interface

AMBA AHB interface


Instruction Data

ETM Interface

ARM v5TEJ CPU core

Coprocessor Interface

ARM7EJ-S
Bus Interface Unit

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ARM A Complete Solution


ARM provides developers with intellectual property (IP) in the form of processor core designs, platforms, related software and development tools everything you need to create an innovative product design based on industry-standard components that are next generation compatible. ARM processor. Meeting the needs of the broad market requirements, the RealView Developer Suite flexible software tools provide the future-proof solution for system-on-chip (SoC) developers, product developers and application developers. The RealView Developer Suite consists of: Fully optimizing ISO C/C++ compiler C++ standard template libraries Powerful macro assembler Linker to support placement of code and data in complex memory maps OS aware debugger (with built-in project manager and editor) Multi-core debug, available as an add on option Instruction set simulator RealView Developer Suite Compilation The RealView Developer Suite RVCT compiler has been researched and developed for over 15 years to provide optimum support for the ARM architecture. The result is a robust and mature C/C++ compiler which continues to evolve with the expanding portfolio of ARM processor cores. The RVCT compiler provides advanced C++ features which have little or no memory requirements when not in use, which include: Real-Time Type Information (RTTI) Namespaces Full Template Support Exception handling RealView Developer Suite Debug The RealView Developer Suite RVD debugger provides C and Assembler source level debugging via an easy-to-use, context sensitive, mouse driven GUI. Advanced features include multi-core debug, OS awareness and extended target visibility. The debugger connects to RealView ICE JTAG emulator/run control units and optionally RealView Trace capture hardware (or to the RVISS instruction set simulator for code development prior to silicon availability). RealView ICE RealView ICE is a network connected (10/100 Ethernet) JTAG run control device that supports high speed program download of up to 500kbytes/sec with a 10MHz JTAG clock. RealView ICE supports a wide range of JTAG clock frequencies from <100Hz (in FPGA emulators) to 50MHz (in real silicon). RealView Trace RealView Trace is an expansion module for RealView ICE. RealView Trace interfaces with ARM on chip Embedded Trace Macrocell components (ETM) for the ARM7, ARM9, ARM10 and ARM11 and in conjunction with RVD debugger provides nonintrusive real-time tracing of instructions, data and profiling for performance analysis. Trace port clock speeds of up to 250MHz are supported. RealView Hardware Platforms The RealView Integrator family is a range of baseboards and flexible development modules designed to meet the needs of SoC developers. The modular approach allows engineers to build custom development environments from known working sub-systems, therefore accelerating the design cycle. The RealView Versatile family is a new range of modular components comprising a platform baseboard and flexible development tiles. Characterised by high density, high speed and high levels of interconnect, the modular approach allows engineers to build custom development environments around the ARM PrimeXsys Platform architecture.

RealView Development Solution

ARM SoC Design Tools


AMBA Compliance Testbench AMBA is an open standard, on chip bus specification that describes the interconnection and management of functional blocks in a SoC. Rapidly emerging as a standard for SoC construction and IP library development, the AMBA bus provides the digital glue that binds IP cores together and is a key component of ARMs reuse strategy. ARMs AMBA Compliance Testbench (ACT) provides a high-quality development environment for IP developers to implement and test components without prior knowledge of the SoC into which the component will be finally integrated. ACT enables the developer to demonstrate that the testing of the AMBA component will integrate seamlessly into an AMBA bus-based SoC design. AMBA Design Kit (ADK )

The ADK provides a generic, stand-alone environment to enable the rapid creation of AMBAbased components and System-on-Chip (SoC) designs. Containing a rich set of basic components for the interconnect, peripherals and verification of an SoC, and several example system designs, the ADK reduces time-to-market by providing the common foundations for product design based upon the AMBA interface. RealView Developer Suite The ARM RealView Developer Suite provides a fully integrated software solution with leading edge tools for creating efficient software to run on any

ARM, ARM Powered, StrongARM, Thumb, Multi-ICE, PrimeCell, ARMulator, RealView, Move, Jazelle and ARM7TDMI are registered trademarks of ARM Limited. ARM7TDMI-S, ARM7EJ, ARM720T, ARM740T, ARM9TDMI, ARM920T, ARM922T, ARM940T, ARM9E, ARM926EJ-S, ARM946E-S, ARM966E-S, ARM1020E, ARM1022EJ-S, EmbeddedICE, EmbeddedICE-RT, AMBA, MultiTrace, ModelGen, ARM Developer Suite, ETM, ETM7, ETM9, ETM10, Embedded Trace Macrocell, PrimeXsys and JTEK are trademarks of ARM Limited. All other brand names or product names are the property of their respective holders. "ARM" is used to represent ARM holdings plc (LSE: ARM and NASDAQ: ARMHY); its operating company ARM Limited and the regional subsidiaries ARM, INC.; ARM KK; ARM Korea Ltd. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. All warranties implied or expressed, including but not limited to implied warranties of satisfactory quality or fitness for purpose are excluded. This document is intended only to provide information to the reader about the product. To the extent permitted by local laws ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information.

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Jazelle Technology | ARM DOI 0114-5/03.04(1)