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ECE4514 Fall 2011 Homework 7: A Static RAM Controller

Assignment posted on 13 October 8AM Solutions due on 20 October 8AM Asynchronous Static RAM memory modules are commonly used for o-chip bulk storage. Accessing data in an SRAM requires the user to provide address- and data-signals with a timing according the specication provided by the SRAM manufacturer. In this homework, you will study the data sheet of the static RAM module present on your DE2-115 board, and you will develop a controller for it. The controller is a module that can translate a generic digital memory interface (used by on-chip components) into an interface that follows the specications of the static RAM manufacturer. You will receive a simple testbench that enables you to verify the correct operation of the SRAM controller. However, the design of the SRAM controller is entirely up to you; only the input/output specication is a given. The result of this homework will the Verilog le that you have developed for this SRAM controller. It is not allowed to use any external code for this assignment. You cannot make use of IP modules, code provided through the Altera toolkit, and so forth. Every single line of Verilog must be your own.

Section 1: Study the SRAM datasheet


The objective of this section is to learn enough about the SRAM on your DE2-115 board so that you are able to write Verilog code for the following SRAM interface.

module sram( input wire [19:0] sram_addr, inout wire [15:0] sram_dq, input wire sram_ub_n, input wire sram_lb_n, input wire sram_ce_n, input wire sram_oe_n, input wire sram_we_n );

// // // // // // //

SRAM SRAM SRAM SRAM SRAM SRAM SRAM

address bidirectional data upper byte control lower byte control chip enable output enable write enable

On your DE2-115 CDROM, there is a subdirectory called DE2 115 datasheets. Find the datasheet for the SRAM component on your board. Youll need to use the datasheet to understand the operation of this component. You will also need to determine the timing of a read operation and a write operation. A few crucial remarks are as follows. According to the datasheet, this particular SRAM comes in three dierent speed grades. Look at the component on the board to identify the exact speed grade for your case. There are several dierent timing diagrams present, corresponding to dierent use cases of the SRAM. Choose the use case that ts most closely to your particular board conguration.

Once you have studied the SRAM datasheet, you have to dene a write-access operation, and a read-access operation for this component. Since we will be developing a synchronous SRAM controller, you have to specicy the read-access and write-access in terms of clock cycles. To describe the behavior of the SRAM controller, you need to create two tables: one which shows what will happen when your interface performs a read-access, and a second table which shows what will happen when your interface performs a write-access.

cycle 1 sram sram sram sram sram sram sram addr dq ub n lb n ce n oe n we n

cycle 2

cycle 3

cycle ...

You can extend each table with as many columns (clock cycles) you need to implement a write-access and a read-access to the SRAM. In the cells of the table, describe the communication between the SRAM chip and your SRAM controller. For SRAM inputs, express the logic values of the signals which your SRAM controller will provide. For SRAM outputs, express the logic values of signals which your SRAM controller will receive from the SRAM. For the read operation, assume the value of the address is ADDRESS, and the data read from ram is READDATA. For the write operation, assume the value of the address is ADDRESS, and the data written into ram is WRITEDATA. The SRAM input/output sram dq is special: it can be either an SRAM input or an SRAM output. Your SRAM interface will need to treat this bus as a tri-state bus. In your tables, indicate if sram dq is used, in each cycle, as an input our as an output. For this section, you need to turn in a PDF which shows both tables (one for read access and one for write access) to the SRAM. Note that this section does not specify the amount of clock cycles you need for the SRAM access; the important point is that your SRAM controller will be able to follow the constraints of the timing diagram. You can assume that the controller will operate at 50MHz.

Section 2: Design the SRAM controller


In Section 1, you have studied the SRAM, and you developed a high-level model of a synchronous controller that can read from, and write into this asynchronous SRAM. Now, you need to develop an implementation for the controller. The outline for this SRAM controller looks as follows. module sramctl( input wire input wire input wire input wire output wire input wire input wire output reg output inout output output output output output ); The ports starting with sram are connected to the SRAM; the ports starting with f are for the SRAM user. These latter ports are asserted at the upgoing clock edge, and they have the following meaning. faddr holds the RAM address. fwdata holds the data going from the user to the RAM. frdata holds the data going from the RAM to the user. faccess is a RAM-access control signal, and should be 1 when the user wants to initiate a RAM-access operation. frwn is a RAM-read/write control signal, and should be 1 for a read operation, and 0 for a write operation. fready is a RAM-access status signal. The signal is 1 to indicate that the current clock edge terminates a RAM-access operation. 4

clk, rst, [19:0] faddr, [15:0] fwdata, [15:0] frdata, faccess, frnw, fready,

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fpga fpga fpga fpga fpga fpga SRAM SRAM SRAM SRAM SRAM SRAM SRAM

address write-data read-data memory access read/not-write control ready signal address bidirectional data upper byte control lower byte control chip enable output enable write enable

wire [19:0] sram_addr, wire [15:0] sram_dq, wire sram_ub_n, wire sram_lb_n, wire sram_ce_n, wire sram_oe_n, wire sram_we_n

An example of the operation of this interface is illustrated in the timing diagram above. At clock edge 1, a read-access operation is started by providing (faddr=ad1, faccess=1, frnw=1). Assume that read operations into the SRAM would take two clock cycles, then the RAM controller should put the fready signal low at the next clock edge. At clock edge 3, the data is then returned to the user. A single-cycle read operation is illustrated at clock edge 3 (faddr=ad2, faccess=1, frnw=1). The data from RAM is valid at clock edge 4, single fready is high at that clock edge. A single-cycle write operation is illustrated at clock edge 5. In this case, the user needs to provide an address as well as data (faddr=a3, fwdata=d3, faccess=1, frnw=0). Note that the access cycle time for the RAM is determined by the timing specication of the SRAM according to the data sheet. Your task is to develop this SRAM controller as a synthesizable Verilog program. An important challenge is that you dont have a behavioral model of the SRAM; you only have the SRAM datasheet. Its up to you to decide how to handle this. For example, you could try to build a behavioral SRAM model for debugging purposes, or you could try to implement your design and instrument it with a SignalTap-II logic analyzer.

To help you test the SRAM controller on the DE2-115 board, a test bench is provided on Scholar. The testbench works as follows. After downloading your design to the FPGA, you can control your design by means of the buttons and the slider switches. By pressing push button 0, you will reset the design. By pressing push button 1, you will program the bit pattern of slider switches 0 to 15 into a data register. By pressing push button 2, you will write the value from the data register into the SRAM. The address used for the write operation is given by the bit pattern of slider switches 0 to 15. The upper 4 bits of the SRAM address are held at 0. By pressing push button 3, you will read the value from the SRAM at the address given by the bit pattern on the slider switches. The data stored at that location will be displayed on red led 0 to 15.

Thus, this simple test bench enables you to read and write values into the SRAM. For this section, you need to turn in a Verilog description of the SRAM controller, sramctl.v. The SRAM controller needs to work properly with the provided test bench.

What to turn in
Turn in the following data on the scholar website. 1. For Section 1, a PDF le with the two tables describing a synchronous read operations and a synchronous write operation into the SRAM. 2. For Section 2, a Verilog design of the SRAM controller. Call this le sramctl.v and call the top-level module of the controller sramctl.