CHAPTER-1 INTRODUCTION

In the past there have been similar research efforts to develop embedded systems to alleviate similar problems. The Talking Signs identification system consists of infrared (IR) transmitters incorporated in the destination panels of buses that transmit route information. Since, an IR beam is highly directional, the visually challenged user must point the handheld receiver towards the transmitter. Hence, RFID technology is used.

A RFID transponder tags are placed on bus stops that transmit information about the route numbers of buses that ply through the stop. The user pre-selects the bus number of interest and is given a cue when the bus arrives. However, the system does not give the user an active choice to select between multiple buses that may be present at the bus stop and problem of boarding the bus remains unresolved. Further, the system is expensive and unaffordable for a large number of users in less developed and developing countries. Step-Hear, a RF based system comprises of a transmitter and a receiver. Installed at strategic locations, the base sends out continuous signals.

All systems currently available possess one or more of the following limitations:(i) unaffordable cost. (ii) Non availability of sales, marketing or servicing in developing countries. (iii) unsuitability for complex unstructured traffic and bus stop conditions indeveloping countries where multiple buses arrive and line up arbitrarily at random positions. (iv) dependence on electricity or structural support available on bus stops.The project aims mainly at developing an affordable system for developing countries with the following specific objective:

To design and implement an affordable user enabled system to obtain the route number of buses approaching a bus stop.

CHAPTER-2 BLOCK DIAGRAM

CHAPTER-3

REQUIREMENTS
3.1 HARDWARE REQUIREMENT: Microcontroller RFID TRANSCEIVER RTC UART serial communication MAX232 IC Voice Analyzer circuit(APR 9600) 12V Power supply

3.2 SOFTWARE REQUIREMENT: Embedded C CCS compiler

CHAPTER-4 MICRO CONTROLLER PIC16F877A

4.1 CORE FEATURES:

High-performance RISC CPU Only 35 single word instructions to learn All single cycle instructions except for program branches which are two cycle Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM data memory Pinout compatible to the PIC16C73B/74B/76/77 Interrupt capability (up to 14 sources) Eight level deep hardware stack Direct, indirect and relative addressing modes Power-on Reset (POR) Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation Programmable code-protection Power saving SLEEP mode Selectable oscillator options

 Low-power, high-speed CMOS FLASH/EEPROM technology Fully static design In-Circuit Serial Programming (ICSP) via two pins Single 5V In-Circuit Serial Programming capability In-Circuit Debugging via two pins Processor read/write access to program memory Wide operating voltage range: 2.0V to 5.5V High Sink/Source Current: 25 mA Commercial and Industrial temperature ranges Low-power consumption: - < 2 mA typical @ 5V, 4 MHz - 20 mA typical @ 3V, 32 kHz - < 1 mA typical standby current

4.2 PERIPHERAL FEATURES:

Timer0: 8-bit timer/counter with 8-bit prescaler

Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler Two Capture, Compare, PWM modules - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit 10-bit multi-channel Analog-to-Digital converter Synchronous Serial Port (SSP) with SPI (Master Mode) and I2C (Master/Slave) Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44-pin only)

CHAPTER-5 PIN DIAGRAM

5.1 PORT A AND TRIS A REGISTER: PORT A is a 6-bit wide bi-directional port. The corresponding data direction register is TRIS A. Setting a TRIS A bit (=1) will make the corresponding PORT A pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRIS A bit (=0) will make the corresponding PORT A pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORT A register reads the status of the pins, whereas writing to it will write to the port latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other PORT A pins have TTL input levels and full CMOS output drivers

5.2 PORT B AND TRIS B REGISTER: PORT B is an 8-bit wide, bi-directional port. The corresponding data direction register is TRIS B. Setting a TRIS B bit (=1) will make the corresponding PORT B pin an input. Clearing a TRIS B bit (=0) will make the corresponding PORT B pin an output. Three pins of PORT B are multiplexed with the Low Voltage Programming function; RB3/PGM, RB6/PGC and RB7/PGD. Each of the PORT B pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>).

5.3 PORT C AND TRIS C REGISTER: PORT C is an 8-bit wide, bi-directional port. The corresponding data direction register is TRIS C. Setting a TRISC bit (=1) will make the corresponding PORT C pin an input. Clearing a TRIS C bit (=0) will make the corresponding PORT C pin an output. When the I2C module is enabled, the PORTC (3:4) pins can be configured with normal I2C levels or with SMBUS levels by using the CKE bit (SSPSTAT <6>).

5.4 PORT D AND TRIS D REGISTERS: PORT D is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORT D can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRIS E<4>). In this mode, the input buffers are TTL.

5.5 PORT E AND TRIS E REGISTER: PORT E has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. I/O PORT E becomes control inputs for the microprocessor port when bit PSPMODE (TRIS E<4>) is set. In this mode, the input buffers are TTL. PORT E pins are multiplexed with analog inputs. When selected as an analog input, these pins will read as 0s. TRIS E controls the direction of the RE pins, even when they are being used as analog inputs.

CHAPTER-6 MICROCONTROLLER OPERATION

BLOCK DIAGRAM OF PIC 16F877A

10

6.1 MEMORY ORGANIZATION:

There are three memory blocks in each of these PICmicro MCUs. The Program Memory and Data Memory have separate buses so that concurrent access can occur. 6.2 PROGRAM MEMORY: The PIC16F87X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F877/876 devices have 8K x 14 words of FLASH program memory and the PIC16F873/874 devices have 4K x 14. Accessing a location above the physically implemented address will cause a wraparound. The reset vector is at 0000h and the interrupt vector is at 0004h.

Program memory and Stack memory 6.3 DATA MEMORY: The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1(STATUS<6>) and RP0 (STATUS<5>) are the bank select bits.

11

6.3 Table Register bank selection 6.4 GENERAL PURPOSE REGISTER FILE: The register file can be accessed either directly or indirectly through the File Select Register FSR. 6.5 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. The Special Function Registers can be classified into two sets; core (CPU) and peripheral. 6.6 STATUS REGISTER The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. 6.7 OPTION_REG REGISTER The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB.

12

6.8 INTCON REGISTER The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. 6.9 PIE1 REGISTER & PIE2 REGISTER The PIE1 register contains the individual enable bits for the peripheral interrupts. The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write operation interrupt. 6.10 PIR1 REGISTER & PIR2 REGISTER The PIR1 register contains the individual flag bits for the peripheral interrupts. The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the EEPROM write operation interrupt. 6.11 PCON REGISTER The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watch-dog Reset (WDT) and an external MCLR Reset.

6.12 ADDRESSING MODES: 6.12.1 DIRECT ADDRESSING Direct Addressing is done through a 9-bit address. This address is obtained by connecting 7th bit of direct address of an instruction with two bits (RP1, RP0) from STATUS register as is shown on the following picture. Any access to SFR registers can be an example of direct addressing.

13

6.12.2 INDIRECT ADDRESSING Indirect unlike direct addressing does not take an address from an instruction but makes it with the help of IRP bit of STATUS and FSR registers. Let's say, for instance, that one general purpose register (GPR) at address 0Fh contains a value of 20. By writing a value of 0Fh in FSR register we will get a register indicator at address 0Fh, and by reading from INDF register, we will get a value of 20, which means that we have read from the first register.

6.12.3 INDIRECT ADDRESSING, INDF AND FSR REGISTERS The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = 0) will read 00h.

14

6.12.4 DATA EEPROM AND FLASH PROGRAM MEMORY The Data EEPROM and FLASH Program Memory are readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers (SFR). There are six SFRs used to read and write the program and data EEPROM memory. hese registers are: EECON1, EECON2, EEDATA, EEDATH, EEADR and EEADRH.The EEPROM data memory allows byte read and writes. EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. The registers EEDATH and EEADRH are not used for data EEPROM access. These devices have up to 256 bytes of data EEPROM with an address range from 0h to FFh 6.13 TIMER MODULES: 6.13.1 TIMER0 MODULE 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h and Edge select for external clock.

6.13.1.1 PRESCALER A prescaler assignment for the Timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.

15

Block diagram of the TIMER0/WDT Prescaler

6.13.2 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE

(PIE1<0>).Timer1 can operate in one of two modes 1) As a timer, 2) As a counter.

Block diagram of TIMER1

16

6.13.3 TIMER2 MODULE: Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for thePWM mode of the CCP module(s). The TMR2 register is readable and writable and is cleared on any device Reset.The input clock (FOSC/4) has a prescale option of 1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit,TMR2IF (PIR1<1>))..

TIMER2

6.14 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: Serial Peripheral Interface (SPI) Inter-Integrated Circuit (I2C)

17

6.15 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D conversion of the analog input signal results in a corresponding 10-bit digital number. To operate in sleep, the A/D clock must be derived from the A/Ds internal RC oscillator. The A/D module has four registers. These registers are: A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register0 (ADCON0) A/D Control Register1 (ADCON1) 1. Configure the A/D module. 2. Configure A/D interrupt (if desired). 3. Wait the required acquisition time. 4. Start conversion. 5. Wait for A/D conversion to complete, by either. 6. Read A/D Result register (ADRES), clear the ADIF bit, if required. 7. For next conversion, go to step 1 or step 2 as required. 6.16 OSCILLATOR CONFIGURATIONS The PIC16F87X can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: LP Low Power Crystal XT Crystal/Resonator

18

 HS High Speed Crystal/Resonator RC Resistor/Capacitor 6.17 RESET The PIC16F87X differentiates between various kinds of reset: Power-on Reset (POR) MCLR reset during normal operation MCLR reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR)

6.18 INTERRUPTS The PIC16F87X family has up to 14 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts or disables (if leared) all interrupts. INT INTERRUPT TMR0 INTERRUPT 6.19 WATCHDOG TIMER (WDT) The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components.

19

Block diagram of watch dog timer 6.20 INSTRUCTION SET SUMMARY Bit-oriented operations Literal and control operations 6.21 CLOCK / INSTRUCTION CYCLE : Clock is microcontroller's main starter, and is obtained from an external memory component called an "oscillator". If we were to compare a microcontroller with a time clock, our "clock" would then be a ticking sound we hear from the time clock.

20

CHAPTER-7

RADIO FREQUENCY IDENTIFICATION DEVICE (RFID) RFID is Radio Frequency Identification Device. It is a fast, affordable and automatic identification technology that uses radio frequency (RF) to transfer data between a RFID reader and a RFID tag. Usually the RFID circuit is a single solid-state memory chip. The data can be read from a distance no contact or even line of sight necessary RFID technology uses RFJD tags, which is a small object, that can be attached to or incorporated into a product. RFID tags contain antennas to enable them to receive and respond to radio-frequency queries. 7.1 MODULES OF RFID The RFID system basically consists of three components: 1. A RFID tag(Transponder) 2. An Interrogator or a tag reader 3. Computer or Processor(Application system with data base) 7.2 RFID TAGS An RFID tag is a small object, such as an adhesive slicker, that can be attached to or incorporated into a product. RFID tags contain antennae to enable them to receive and respond to radio-frequency queries from the interrogator. The tag is generally made of an 1C. The IC will include memory and some form of processing capability. 7.2.1 ACTIVE TAGS Active RFID tags may have longer ranges and larger memories than passive tags, as well as the ability to store additional information sent by the transceiver. Many active tags have practical ranges of tens of meters, and a battery life of up to several years. Active tags -With internal power supply Passive tags -Without internal power supply

21

Battery

~100m

Components of active RFID System There are four different kinds of tags commonly in use. They are categorized by their radio frequency: Low frequency tags (between 125 to 134 kilohertz) High frequency tags (13.56 megahertz) UHF tags (868 to 956 megahertz) Microwave tags (2.45 gigahertz).

7.2.2 PASSIVE TAGS Passive RFID tags do not have their own power supply. The minute electrical current induced in the antenna by the incoming radio-frequency scan provides enough power for the tag to send a response. Due to power and cost concerns, the response of a passive RFID tag is necessarily brief, typically just an ID number (GUID). Lack of its own power supply makes the device quite small: commercially available products exist that can be embedded under the skin. As of 2004, the smallest such devices commercially available measured 0.4 mm x 0.4 mm. Passive tags have practical read ranges that vary from about 10 mm up to about 5 meters.

22

Components of a passive RFID system 7.3 BASIC WORKING OF TAGS When the tag is brought in the range of the interrogator or the reader, it receives the signal which is sent by the reader (interrogator). In case of a passive tag, it receives all the power it needs from the signal itself. As well as using this radio wave to carry the data, the tag is able to convert it into power. The tag then uses a technique called backscatter to reply to the interrogator. This does not involve a transmitter on the tag, but is a means of reflecting the carrier wave and putting a signal into that reflection Battery assisted tags are just like passive tags (they use backscatter) but they have a battery to provide the power to the chip. READER TALKS FIRST (RTF) With a RTF system, the tag just sits there, until it hears a request from the interrogator.

This means that even though a tag may be illuminated (receiving power) from the interrogator, it does not talk until it is asked a question. TAG TALKS FIRST (TTF) The tag talks as soon as it gets power, or in the case of a battery assisted tag or active tag, it talks for short periods of time, all the time. This gives you a much faster indication of a tag within

23

sight of the interrogator, but it also means that the airwaves have constant traffic. The antenna in a tag is the physical interface for the RF to be received and transmitted. Its construction varies depending on the tag itself and the frequency it operates on. Low frequency tags often use coils of wire, whereas high frequency tags are usually printed with conducting inks. 7.4 RFID FREQUENCIES RFID operates in several frequency bands. The exact frequency is controlled by the Radio Regulatory body in each country. The generic frequencies for RFID are:125 - 134 kHz , 13.56 MHz, UHF (400- 930 MHz),2.45 GHz,5.8 GHz. Although there are other frequencies used, these are the main ones. In the UHF band, there are two areas of interest. Several frequencies in the 400 MHz band and then the band 860 930 MHz Each of the frequency bands have advantages and disadvantages for operation. The lower frequencies 125-134k Hz and 13.56 MHz work much better near water or humans than do the higher frequency tags. Comparing passive tags, the lower frequencies usually have less range, and they have a slower data transfer rate. The higher frequency ranges have more regulatory controls and differences from country to country.

24

RFID TRANCEIVER:

RFID TRANCEIVER:

7.5 RFID PERFORMANCE CRITERION The performance of a Read/Write RFID system is dictated by the following criteria: Tags Memory Capacity, Data Transfer Speed, Operating Range, Multiple-Tags-in-Field Capability, Operating Temperatures, RF Carrier Frequency of the Tag-to-Antenna Link, RFID System Connectivity.

25

7.6 MEMORY CAPACITY The amount of memory available on Read Only Tags is 20 bits of information. Active Read/Write Tags vary from 64 Bytes to 32KB, meaning that several pages of type-written text can be stored in a Read/Write Tag. This is usually sufficient to carry build manifests and test

data, as well as allowing room for system growth. The memory of Passive Read/Write Tags ranges from 48 Bytes to736 Bytes and provides many distinct benefits over Active Systems. 7.7 DATA TRANSFER SPEED Speed is an important factor for most data capture systems. With todays decreasing production cycle times, the amount of time needed to access or update the RFID pallet identification system must fit within a very small time window. 7.7.1 READ ONLY SPEED The speed of a Read Only RFID system is dictated by the length of the code, the speed of data transfer from the Tag, the range at which they will operate. Antenna Link, and the modulation technique used to transfer daa. This speed will vary according to the specific products used in each application. For instance, the EMS Read Only system transmits its data in a 20-bit frame at a rate of 8750 bits per second. 7.7.2 PASSIVE READ/WRITE SPEED The speed of a Passive Read/Write RFID system is based on the same criteria as Read Only systems, except now one must consider the speed of data transfer both to and from the Tag. Speed will again vary according to the specific products used in each application. For instance, the EMS HMS system transfers data at a rate of 1000 bytes per second. 7.7.3 ACTIVE READ/WRITE SPEED The speed of an Active Read/Write system is based on the same criteria as a Passive Head/Write system, unless the Passive system relies on charging a capacitor in the fag to enable Communication. Importantly, a typical low-frequency Read/Write system will operate at speeds of only 100 or 200 bytes transferred per second.

26

7.8 OPERATING RANGE The Read/Write range for presently available systems varies from less than one inch to over 29 inches; increased Read/Write ranges of up to eight feet using low frequency 13.56 MHz. (Contact an EMS Sales Engineer for further details). 7.9 OPERATING TEMPERATURES EMS is considered the foremost expert on high-temperature RFID applications, and has numerous high-temperature installations throughout the world. EMS field-proven history in high-temperature applications-originated with the Passive Read Only ES-Series Tags. Designed to survive up to 401F (240C), in addition to sub-freezing levels of -40F (-40C). 7.10 CURRENT USES OF RFID

RFID tags are used in library book or bookstore tracking, pallet tracking, building access control, airline baggage tracking, and apparel item tracking.These badges need only be held within a certain distance of the reader to authenticate the holder. UHF RFID
tags are commonly used commercially in pallet and container tracking, and truck and trailer tracking in shipping yards. Microwave RFID tags are used in long range access control for vehicles, an example being General Motors on Star system. Some toll booths, such as Californias Fast Talk and Illinois I-Pass system, use RFID tags for electronic toll collection. The tags are read as vehicles pass; the information is used to debit the toll from a prepaid account. The system helps to speed traffic through toll plazas. Sensors such as seismic sensors may be read using RFID transceivers, greatly simplifying remote data collection.

27

CHAPTER-8 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER 8.1 USART (Universal Synchronous Asynchronous Receiver Transmitter) start|< five to eight data bits >| stop bit(s) 0 | ---- - - - - - - - - - | | | | | | | | | | | Space (logic low)

|S|1|2|3|4|5|6|7|8|S|S| | 1 | | | | | | | | | | | Mark (logic high)

- - - - - - - - - - - --------

ASYNCHRONOUS CODE FORMAT. The right-most bit is always transmitted first. If parity is present,the parity bit comes after the data bits but before the stop bit(s).UART stands for the Universal Asynchronous Receiver/Transmitter. In asynchronous transmitting, teletype-style UARTs send a "start" bit, five to eight data bits, least-significant-bit first, an optional "parity" bit, and then one, one and a half, or two "stop" bits. The start bit is the opposite polarity of the data-line's idle state. The stop bit is the data-line's idle state, and provides a delay before the next character can start. (This is called asynchronous start-stop transmission). In mechanical teletypes, the "stop" bit was often stretched to two bit times to give the mechanism more time to finish printing a character. A stretched "stop" bit also helps resynchronization. The parity bit can either make the number of "one" bits between any start/stop pair odd, or even, or it can be omitted. Odd parity is more reliable because it assures that there will always be at least one data transition, and this permits many UARTs to resynchronize.

28

In synchronous transmission, the clock data is recovered separately from the data stream and no start/stop bits are used. This improves the efficiency of transmission on suitable channels since more of the bits sent are usable data and not character framing. An asynchronous transmission sends nothing over the interconnection when the transmitting device has nothing to send; but a synchronous interface must send "pad" characters to maintain synchronism between the receiver and transmitter. The usual filler is the ASCII "SYN" character. This may be done automatically by the transmitting device. USART chips have both synchronous and asynchronous modes. 8.2 TRANSMITTER (USART) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI). The USART can be configured in the following modes: Asynchronous (full duplex) Synchronous Master (half duplex) Synchronous Slave (half duplex) 8.3 USART BAUD RATE GENERATOR (BRG) The BRG supports both the asynchronous and synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In synchronous mode, bit BRGH is ignored. Table shows the formula for computation of the baud rate for different USART modes which only apply in master mode (internal clock).

29

8.3 Table Baud Rate Formula 8.4 USART ASYNCHRONOUS MODE In this mode, the USART uses standard non-return-to zero (NRZ) format (one start bit, eight or nine data bits, and one stop bit). The most common data format is 8 bits. An on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSB first. The USARTs transmitter and receiver are functionally independent. Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver 8.5 USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in fig. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This can be enabled/disabled by setting/clearing enable bit TXIE.

30

USART transmission bock diagram 8.6 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Fig. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. The heart of the receiver is the receive (serial) shift register (RSR). After sampling the STOP bit, the received data in the RSR is transferred to the RCREG register (if it is empty

USART Receive block diagram

31

8.7 USART SYNCHRONOUS SLAVE MODE Synchronous slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 8.8 USART SYNCHRONOUS SLAVE TRANSMISSION The operation of the synchronous master and slave modes are identical except in the case of the SLEEP mode. 8.9 USART SYNCHRONOUS SLAVE RECEPTION The operation of the synchronous master and slave modes is identical, except in the case of the SLEEP mode. Bit SREN is a don't care in slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h).

32

CHAPTER-9 MAX232 IC 9.1 COMMUNICATING WITH THE PC - THE MAX232 IC

Now that we have the 8 bit value in the 16F877A , we want to send that value to the PC. The 16F877A has a built in serial port that makes it very easy to communicate with the PC's serial port but the 16F877A outputs are 0 and 5 volts and we need +10 and -10 volts to meet the RS232 serial port standard. The easiest way to get these values is to use the MAX232. The MAX232 acts as a buffer driver for the processor. It accepts the standard digital logic values of 0 and 5 volts and converts them to the RS232 standard of +10 and -10 volts. It also helps protect the processor from possible damage from static that may come from people handling the serial port connectors.

33

CHAPTER-10 VOICE ANALYZER CIRCUIT (APR9600)

10.1 FEATURES : Single-chip, high-quality voice recording & playback solution - No external ICs required - Minimum external components Non-volatile Flash memory technology - No battery backup required User-Selectable messaging options - Random access of multiple fixed-duration messages - Sequential access of multiple variable-duration messages User-friendly, easy-to-use operation - Programming & development systems not required - Level-activated recording & edge-activated play back switches current: 1 uA typical - Automatic p Low power consumption - Operating current: 25 mA typical - Standby ower-down Chip Enable pin for simple message expansion

34

10.2 GENERAL DESCRIPTION : The APR9600 device offers true single-chip voice recording,non-volatile storage, and playback capability for 40 to 60 seconds.The device supports both random and sequential access of multiple messages.Sample rates are user-selectable,allowing designers to customize their design for unique quality and storage time needs.Each memory cell can store 256 voltage levels.

35

CHAPTER-11 OVERALL PROCESS DESCRIPTION 11.1 FLOW SEQUENCE:

Stage 1: Acquisition of Bus Information

Stage 2: Transmission of Bus Information

Stage 3: Reception of Bus Information Stage 4:

Processing of Bus Information

Stage 5:

Audio Output for VIP

36

11.2 EXECUTION STEPS:

37

11.3 DISCUSSION:
Reliable access to the bus transport system is a key challenge for enhancing mobility and socio-economic opportunities for the visually challenged persons, particularly in developing countries. The user-triggered bus identification and homing system is anentirely user-controlled system that requires no driver involvement. It is aimed at providing independence to the user and reduces anxiety and uncertainty in boarding the right bus. It may also benefit the senior citizens and individuals with low vision. The installation of the system requires minimal modifications in the bus. The system design is highly modular and language independent thereby allowing usage in any language or dialect. The user module can potentially be integrated into a mobile phone. The system described for the bus transport system is generic and can be used for trams, trains, metro rail etc. where multiple route vehicles are boarded from the same location. It can also be adapted for a building navigation system for the visually challenged wherein identification modules can be placed at important landmarks like fire-exits, staircases etc. that transmit auditory cues once selected by the user.

38

CHAPTER-12 APPLICATIONS

This project is a cost efficient and it can be purchases easily and designing technique is also user-friendly. It can be used to for private buses or vehicles which are in need to of this type of method. In this project we use the RFID technology in which each bus has its own code so that it will be more security to all.. The project contains the keypad through this we can find the bus timing accurately and where the bus comes at that time.

39

CHAPTER-13 COST ESTIMATION

S.NO

COMPONENTS

COST (In rupees)

RFID MODULE

2000

PIC DEVELOPMENT BOARD

1300

VOICE ANALYZER MODULE

700

TOTAL

4000

40

CHAPTER-14 CONCLUSION

Reliable access to bus transport system is essential for enhancing socio-economic opportunities for the visually challenged. The system is entirely usercontrolled (without any driver involvement) and ameliorates the anxiety of boarding the right bus. The system is language-independent, requires minimal modifications in the busand would also benefit senior citizens and individuals with low vision. Projected cost of the user/bus module is under 25 USD each.

FUTURE SCOPE: In future, a barrier-free transport system will be provided for the visually impaired people and those VIPs will be able to catch public buses with the same ease, convenience. As visual cues no longer constrain the distance required to identify a bus, VIPs will benefit from the additional notification time. Such a system will directly influence the quality of life of VIPs, by providing the freedom to travel independently.

41

CHAPTER-15 REFERENCES

1 . World Health Organization 2009. Fact Sheet No. 282: Visual impairment and blindness. [Online] http://www.who.int/mediacentre/factsheets/fs282/en/ [May 2009]. 2. B. Olufemi Odufuwa, Towards Sustainable Public Transport for Disabled People in Nigerian Cities,Stud. Home Comm. Sci.,1(2): 93-101 (2007). 3. Bones Inc. Personal Assistant for Visually Impaired People. [Online] http://www.bones.ch/pages/eng/pavip/pavip.html [January 2008] 4. Talking Signs Inc. 2000. Talking Signs Locations in San Francisco. [Online] http://www.ski.org/Rehab/WCrandall/introts.html [June 2007]. 5. Step Hear, Guiding your way. [Online] http://www.step-hear.com/ [February 2010].

42