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Program Concept
Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of control signals
What is a program?
A sequence of steps For each step, an arithmetic or logical operation is done For each operation, a different set of control signals is needed
A hardware segment accepts the code and issues the control signals We have a computer!
Components
The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit Data and instructions need to get into the system and results out
Input/output
Thumb drive Printer Hard disk CD-ROM Network adapter Graphic card Etc..
Instruction Cycle
Two steps:
Fetch Execute
Fetch Cycle
Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC
Unless told otherwise
Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions
Execute Cycle
Processor-memory
data transfer between CPU and main memory
Processor I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations e.g. jump
Combination of above
? The easier way for us to write instruction is to use hexadecimal 1940 3370
Interrupts
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Program
e.g. overflow, division by zero
Timer
Generated by internal processor timer Used in pre-emptive multi-tasking
I/O
from I/O controller
Hardware failure
e.g. memory parity error
Interrupt Cycle
Added to instruction cycle Processor checks for interrupt
Indicated by an interrupt signal
Multiple Interrupts
Disable interrupts
Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur
Define priorities
Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt
William Stallings Computer Organization and Architecture 8th Edition Chapter 10 Instruction Sets: Characteristics and Functions
What is an Instruction Set? (2) The complete collection of instructions that are understood by a CPU Machine Code Binary
Operation
8 bits
Operand
24 bits
Operation field
Addressing information
Instruction Representation (1) In machine code each instruction has a unique bit pattern For human consumption (well, programmers anyway) a symbolic representation is used
e.g. ADD, SUB, LOAD
?
The easier way for us to write instruction is to use hexadecimal 1940 3370
LOAD
Instruction Types Data processing Data storage (main memory) Data movement (I/O) Program flow control
Operation
Source/Destination
Fewer addresses
Less complex (powerful?) instructions More instructions per program Faster fetch/execution of instructions
Characters
ASCII etc.
Logical Data
Bits or flags
Case study: x86 Data Types 8 bit Byte 16 bit word 32 bit double word 64 bit quad word 128 bit double quadword Addressing is by 8 bit unit Words do not need to align at evennumbered address Data accessed across 32 bit bus in units of double word read at addresses divisible by 4 Little endian
Types of Operation Data Transfer Arithmetic Logical Conversion I/O System Control Transfer of Control
Arithmetic Add, Subtract, Multiply, Divide Signed Integer Floating point May include
Increment (a++) Decrement (a--) Negate (-a)
Input/Output May be specific instructions May be done using data movement instructions (memory mapped) May be done by a separate controller (DMA)
Skip
e.g. increment and skip if zero ISZ Register1 Branch xxxx ADD A
Subroutine call
c.f. interrupt call
Branch Instruction
Byte Order Names The problem is called Endian The system on the left has the least significant byte in the lowest address This is called big-endian The system on the right has the least significant byte in the highest address This is called little-endian
William Stallings Computer Organization and Architecture 8th Edition Chapter 11 Instruction Sets: Addressing Modes and Formats
Immediate Addressing
Operand is part of instruction Operand = address field e.g. ADD 5
Add 5 to contents of accumulator 5 is operand
Instruction
Opcode Operand
Direct Addressing
Address field contains address of operand Effective address (EA) = address field (A) e.g. ADD A
Add contents of cell A to accumulator Look in memory at address A for operand
Single memory reference to access data No additional calculations to work out effective address Limited address space
Instruction
Opcode Address A Memory
Operand
Indirect Addressing (1) Memory cell pointed to by address field contains the address of (pointer to) the operand EA = (A)
Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator
Opcode
Address A
EA = (A) Look in A, find address (A) and look there for operand
Operand
Indirect Addressing (3) Large address space 2n where n = word length May be nested, multilevel, cascaded
e.g. EA = (((A)))
Draw the diagram yourself
Register Addressing (1) Operand is held in register named in address filed EA = R Limited number of registers Very small address field needed
Shorter instructions Faster instruction fetch
Instruction
Opcode Register Address R Registers
Operand
C.f. indirect addressing EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2n) One fewer memory access than indirect addressing
Instruction
Opcode Register Address R Memory
Registers
Pointer to Operand
Operand
Instruction
Opcode Register R Address A Registers Memory
Pointer to Operand
Operand