CXA2149Q

I2C-Bus-Compatible Audio/Video Switch For the availability of this product, please contact the sales office.
Description The CXA2149Q is a video and audio switch IC featuring I2C bus compatibility for TVs. The IC has input pins that are compatible with the SCART protocols. It offers other features such as an electronic mute function with switching noise reduction (zero cross detection), electronic volume control, automatic SYNC pulse detection, and group delay control. Features 3 CVBS inputs. 2 CVBS outputs. Group delay control on TV and CVIN1. SYNC ID on TV and CVIN1. 3 Y/C inputs. 2 Y/C outputs. 6 L/R/2 inputs. 3 L/R/2 outputs. Mode inputs compatible with the SCART protocol. 3 Y/C mixer circuits. Audio muting via software control. External muting input. Audio switching noise elimination circuit. Volume adjustment via software control on L/R channel 3. Wide band video amplifiers (20 MHz, 3 dB). Wide audio dynamic range (3 Vrms typ) Serial control via I2C bus. Separate control of video and audio switches. High impedance maintained by I 2C lines (SDA, SCL) even when power is off. Configurable dual slave address 90/92. I2C bus 5 and 3.3 V compatible. Applications TVs Structure Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

64 pin QFP (Plastic)

Absolute Maximum Ratings (Ta=25 C unless stated) Supply voltage VCC 12 V Storage temperature Tstg 65 to +150 C Allowable power dissipation PD 900 mW Operating Conditions Supply voltage Typical supply current Operating temperature

VCC Topr

9+/0.5 75 20 to +75

V mA C

E99946A9Y-TE

CXA2149Q

Block Diagram
SYNC DETECT I 2C TV CVIN1 CVIN2 REXT RGD1 RGD2 RGD3 RGD4 Y1 Y2 Y3 TRAP3 64 62 60 6dB GROUP DELAYS I 2C 6dB 63 61 TC1 TC2 TVOUT

1 7 6 4 3
58 56 54 0dB

CVOUT1

11

YOUT1

10 53 0dB 13

TRAP1 COUT1

C1 C2 C3 DVCC MODE1 MODE2 MODE3 MUTE SDA SCL ADR DGND LO0 LO1 LTV LV1 LV2 LV3 LV4 LV5 RTV RV1 RV2 RV3 RV4 RV5

52 51 49 44 18 19 20 17 15 14 16 42 I 2C LOGIC

6dB 43 CVOUT2

0dB 45 YOUT2

46 0dB 47 59, 12 BIAS 55 57, 48 BIAS 21 22 31 6dB 39

TRAP2 COUT2 VVCC1, 2 VBIAS VGND1, 2 AVCC ABIAS AGND LOUT1

5 8
25 30 29 28 27 26 32 37 36 35 34 33 6dB 6dB 6dB 6dB 6dB

38

ROUT1

41

LOUT2

40

ROUT2

6dB 23
0 to 63dB

LOUT3

6dB 24
0 to 63dB

ROUT3

CXA2149Q

Pin Configuration

VGND2

CVOUT2

COUT2

ROUT2

ROUT1

YOUT2

TRAP2

LOUT2

LOUT1

DGND

DVCC

RV1

RV2

RV3

RV4 34

51 C1 TRAP3 Y3 VBIAS Y2 VGND1 Y1 VVCC1 CVIN2 TC2 CVIN1 TC1 TV 52 53 54 55 56 57 58 59 60 61 62 63 64

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

33 32 RTV 31 AGND 30 LV1 29 LV2 28 LV3 27 LV4

CXA2149Q

RV5 26 LV5 25 LTV 24 ROUT3 23 LOUT3 22 ABIAS 21 AVCC 20 MODE3 19 MODE2

NC

C2

1
REXT

2
TVOUT

3
RGD4

C3

4
RGD3

5
LO0

6
RGD2

7
RGD1

8
LO1

9
CVOUT1

10 TRAP1

11 YOUT1

12 VVCC2

13 COUT1

14 SCL

15 SDA

16 ADR

17 MUTE

18 MODE1

CXA2149Q

Pin Description Pin No 64 62 60 Symbol Pin voltage (V) Equivalent circuit Description

TV CVIN1 CVIN2
64 58

VCC

Video signal inputs.

147

3.9 58 56 54 Y1 Y2 Y3

62 56 60 54 0.5

Luminance signal inputs.

VCC 5.2V

52 51 49

C1 C2 C3

52

20k

4.5

51 49 147 100

Chrominance signal inputs.

25 30 29 28 27 26 32 37 36 35 34 33 9 43 11 45 13 47 2

LTV LV1 LV2 LV3 LV4 LV5 RTV RV1 RV2 RV3 RV4 RV5 CVOUT1 CVOUT2 YOUT1 YOUT2 COUT1 COUT2 TVOUT

VCC 25 32 30 37 4.5V 33k 33k

4.5

29 36 28 35 27 34 26 33

Audio signal inputs.

3.8 3.5 4.5

1.8m

VCC

Composite video signal outputs.

45 13 47

9
43 11

Luminance signal outputs. Chrominance signal outputs. TV signal group delayed output.

3.8

CXA2149Q

Pin No

Symbol

Pin voltage (V)

Equivalent circuit

Description

VCC

7 3

RGD1 RGD4

4.5

7 3
0.5m

Group delay output to external filter.

VCC

6 4

RGD2 RGD3

4.5

1.7k

6 4

Group delay inputs from external filter.

VCC

3.8V

REXT

1.7

Pin connection for 39 k group delay setting resistor. Pin voltage is group delay control dependent.

44 59 12 21 42 57 48 31

DVCC VVCC1 VVCC2 AVCC DGND VGND1 VGND2 AGND

Digital supply. Video supply. Video supply. Audio supply. Digital ground. Video ground. Video ground. Audio ground.

CXA2149Q

Pin No

Symbol

Pin voltage (V)

Equivalent circuit

Description

VCC

39 41 23 38 40 24

LOUT1 LOUT2 LOUT3 ROUT1 ROUT2 ROUT3

39 56

4.5

20k

41 23 38 40 24

Audio signal outputs.

VCC

20k

22

ABIAS

4.5

22

4.5V 20k

Internal reference bias for audio circuits. A capacitor is connected from this pin to GND.

VCC

55

VBIAS

4.5

55

4.5V

Internal reference bias for video circuits. A capacitor is connected from this pin to GND.

14

SCL

4k 14 15

I2C bus clock line.

15

SDA

I2C bus data line.

VCC

16

ADR

Slave address control.

16 17 72k 28k

17

MUTE

Audio signal output mute.

CXA2149Q

Pin No

Symbol

Pin voltage (V)

Equivalent circuit

Description

VCC

5 8

LO0 LO1

I 2C control

5 8

Open collector logic outputs.

18

18 19 20

MODE1 MODE2 MODE3

19 20 25k 25k

Function SCART inputs from SCART connectors.

VCC

63 61

TC1 TC2

63 61 147

Video detect time constant capacitor connection pins.

VCC

10 46 53

TRAP1 TRAP2 TRAP3

10

3.5

200 200

46 53

Connects trap circuit for subcarrier.

Note. Pin voltages indicated the approximate DC voltage levels with no signals inputs.

CXA2149Q

Electrical Characteristics Item Supply voltage Supply current Symbol VCC ICC Conditions

(Ta=25 C, VCC=9 V unless stated.) Min. 8.5 40 Typ. 9.0 75 Max. 9.5 100 Unit V mA

I2C (Operation of the I2C using either a 3.3 or 5 V supply on the external controller is possible) Item High level input voltage Low level input voltage Low level output voltage Max. clock frequency Min. waiting time for data change Min. waiting time for data transfer start Low level clock pulse width High level clock pulse width Min. waiting time for start preparation Min. data hold time Min data preparation time Rise time Fall time Min. waiting time for stop preparation Symbol VIH VIL VOL fSCL tBUF tHDSTA tL tH tSUSTA tHDDAT tSUDAT tR tF tSUSTO Conditions Min. 2.3 0 0 0 4.5 4 4.7 4 4.7 5 250 4.7 Typ. 50 Max. 5 1.5 0.4 100 1 300 Unit V V V kHz s s s s s s ns s ns s

SDA 3 mA sink

CXA2149Q

Audio System Item Gain Channel 1/Channel 2 Channel 3 (max.) Channel 3 (min.) 3 dB bandwidth Total harmonic distortion Input dynamic range Crosstalk Ripple rejection ratio Output DC offset Input impedance Output impedance Phase difference S/N ratio Mute Volume control Fine Coarse Symbol FGVA1 VGVAF VGVA0 FBWA THD VDRA VCtA RRA Voff Zin Zout VPDA S/NA Amute FEVC CEVC f=1 kHz, 1 Vrms input. Compare left and right channels. f=1 kHz, 1 Vp-p input with a 20 Hz to 20 kHz passband. See note 1. f=1 kHz, 1 Vp-p input. f=1 kHz, 0.5 Vp-p input. 1 Vp-p I/P, 1 kHz serving as 0 dB ref. f=1 kHz, 0.5 Vp-p I/P with a 400 Hz to 80 kHz passband. f=100 kHz, distortion at O/P less than 0.3 % f=1 kHz, 1 Vp-p I/P, measure other outputs. f=100 Hz, 0.3 Vp-p signal applied to AVCC Offset voltage between I/P and O/P. Conditions f=1 kHz, 1 Vp-p I/P. Min. 0.5 0.5 68 2.8 30 85 0.6 7.6 Typ. 0 0 63 1 0.01 3.0 90 55 0 66 20 0.1 90 90 1 8 Max. 0.5 0.5 58 0.05 76 30 70 1.4 8.4 Unit dB dB dB MHz % Vrms dB dB mV k Deg dB dB dB dB

Audio System Notes 1. Channel 3 should be set at maximum volume.

CXA2149Q

Video System Item CVOUT1/2 gain Y/COUT1/2 gain 3 dB bandwidth 3 dB bandwidth Y/C mixer Input level, TV and CVIN1 Input dynamic range, CVIN2 and Y inputs. Crosstalk Symbol GVCV GVYC FBWV1 FBWV2 VRIV VDRV VCtV Conditions f=200 kHz, 0.3 Vp-p I/P. f=200 kHz, 0.3 Vp-p I/P. 0.3 Vp-p I/P. See note 1. 0.3 Vp-p I/P. See note 1. f=200 kHz, distortion at O/P less than 1 %, GD=OFF f=200 kHz, distortion at O/P less than 1.0 %. f=4.43 MHz, 0.7 Vp-p I/P, measure other outputs. Ratio of 0.7 Vp-p white level to black line noise. 5 kHz to 5 MHz passband. See note 2. 1.4 Vp-p 5 step staircase, modulated with 150 mVp-p 4.43 MHz. As above. f=200 kHz, 0.7 Vp-p. See figure 1 and note 3. See note 4. Min. 5.5 0.5 15 10 1.4 1.7 Typ. 6 0 20 15 55 Max. 6.5 0.5 Unit dB dB MHz MHz Vp-p Vp-p dB

S/N ratio

S/NV

72

dB

Differential gain Differential phase Group delay SYNC identification detected when SYNC amplitude SYNC duty cycle not detected when SYNC amplitude SYNC duty cycle

DG DP GD

1.5 1.5 200

0 0 250

1.5 1.5 350

% Deg ns

SYNC1

64 s period.

100 91

30 84

mV % mV %

64 s period.

10 4.5 4 Group delay (seconds) 3.5 3 2.5 2 1.5 1 0

Figure 1 Group delay characteristic

3 Frequency (Hz)

10

10

CXA2149Q

Video System Notes 1. 200 kHz is taken to be 0 dB for the purpose of this measurement. Where applicable, the group delay function will be turned off to make this measurement. 2. Weighted using CCIR567. 3. This group delay characteristic, figure 1, is for the B, G specifications. It does not take into account the input and output delays inherent within the AV switch. 4. The sync detection circuits operate on the video sources that have been switched into the TV and CVIN1 channels, respectively. The internal SYNC discriminator circuit functions in the following way. The SYNC tip of the incoming video input is clamped to a fixed level and the signal is then compared in magnitude with an internal threshold voltage. If the signal is smaller than the threshold level the IC determines that the SYNC does not exist. Conversely, if the signal is found to be greater than the threshold then the duty cycle of signal is passed to the duty discrimination circuit. The discriminator circuit will identify whether the duty cycle of the signal is above 91 % at which point SYNC is detected, or below 84 % when SYNC is not detected. To prevent occasional video disturbances such as IF noise from the tuner causing malfunctioning of the SYNC detector, a time constant of approximately 14 line periods is applied during which the status of the SYNC detection is maintained.

11

1k
BC547B

+12V 1k
BC547B

+12V Measurement Point 1k

V
BC547B

75 +12V +9V 100nF 100nF

75

51
C2 NC C3 RV1 RV2 RV3 RV4 DVCC DGND TRAP2 LOUT2 YOUT2 ROUT2 LOUT1 VGND2 COUT2 ROUT1 RV5

Video Test Configuration

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

52 C1
AGND 31 LV1 30 LV2 29 LV3 28 LV4 27

CVOUT2

75 RTV 32

100nF

75

53 TRAP3

10F 100nF

54 Y3

100nF

55 VBIAS

75

100nF

56 Y2

57 VGND1 CXA2149Q
LTV 25 ROUT3 24 LOUT3 23 ABIAS 22 AVCC 21 MODE3 20 TRAP1 YOUT1 VVCC2 COUT1 SCL SDA ADR MUTE MODE1 MODE2 +9V LV5 26

75

100nF

58 Y1

+9V 100nF 75

59 VVCC1

REXT

TVOUT

RGD4

RGD3

LO0

RGD2

RGD1

LO1

CVOUT1

200

Input Signal

3.3k 3.3k

I 2C

Video System Test Configuration (gain, dynamic range, bandwidth, signal to noise, crosstalk, differential gain, differential phase, sync ID, group delay) Signals applied to inputs on Pins 64, 62, 60, 58, 56, 54, 52, 51, 49 Output signal measured form Pins 9, 11, 13, 43, 45, 47 Notes: 1) All +9 V supplies de-coupled close to supply Pins 21, 44, 59 with 10 nF ceramic capacitor. 2) Refer to application schematic for external pin configuration of sync detect circuits. 3) Input signal assumes 75 ohm video driver. All video outputs are loaded with an emitter follower during tests.

200

12
10F

60 CVIN2

+12V

+12V

+12V

+12V

61 TC2

75

1F

BC547B

BC547B

BC547B

BC547B

62 CVIN1

1k

1k

1k

1k

63 TC1

75

1F

64 TV

100nF

1 3
10 11 12 13 14

2 4 6 7

15

16

17

18

19

39k

CXA2149Q

V
10F 1k 1k 1k 1k +9V 10F 1F 1F 1F 1F 1F 10F 1k 10F

10k Measurement Point

51
C2 NC C3 RV1 RV2 RV3 RV4 RV5 DVCC DGND TRAP2 LOUT2 YOUT2 ROUT2 LOUT1 VGND2 COUT2 ROUT1

Audio Test Configuration

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

52 C1
RTV 32 1k AGND 31 LV1 30 1k 1F 1k 1F 1k 1F 1k 1F 1k 1F 1k 10F LV2 29 LV3 28 LV4 27 1F

53 TRAP3 54 Y3 55 VBIAS 56 Y2 57 VGND1 58 Y1 CXA2149Q

LTV 25 ROUT3 24 LOUT3 23 10F ABIAS 22 AVCC 21 MODE3 20 TRAP1 YOUT1 VVCC2 COUT1 SCL SDA ADR MUTE MODE1 MODE2 +9V LV5 26

10F

100nF

+9V

59 VVCC1 60 CVIN2 61 TC2 62 CVIN1 63 TC1 64 TV

REXT TVOUT RGD4 RGD3 LO0 RGD2 RGD1 LO1 CVOUT1

CVOUT2

1F

200

200

13
1
10 11 12 13

10F

100nF

14

15

16

17

18

19
SW1 HW mute Input Signal I 2C +5V

Audio System Test Configuration (gain, dynamic range, signal to noise, crosstalk, distortion, volume control, ZCD and mute) Signals applied to inputs on Pins 25, 26, 27, 28, 29, 30, 32, 33, 34, 35, 36, 37 Output signal measured form Pins 23, 24, 39, 40, 41 Notes: 1) All +9 V supplies de-coupled close to supply Pins 21, 44, 59 with 10 nF ceramic capacitor. 2) When muting audio using hardware mute, SW1 is closed.

CXA2149Q

Video Output Signal Measurement

V
+9V

DC Test Configuration

51
C2 NC C3 RV1 RV2 RV3 RV4 RTV 32 AGND 31 LV1 30 LV2 29 LV3 28 LV4 27 LV5 26 LTV 25 ROUT3 24 LOUT3 23 ABIAS 22 AVCC 21 MODE3 20 TRAP1 YOUT1 VVCC2 COUT1 SCL SDA ADR MUTE MODE1 MODE2 +9V DVCC DGND TRAP2 LOUT2 YOUT2 ROUT2 LOUT1 VGND2 COUT2 CVOUT2 ROUT1 RV5

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

52 C1

53 TRAP3

10F

54 Y3

100nF

55 VBIAS

56 Y2

57 VGND1 CXA2149Q

58 Y1

+9V

59 VVCC1

60 CVIN2

REXT

TVOUT RGD4

RGD3 LO0

RGD2

RGD1 LO1

CVOUT1

200

200

14
1 3
10 11 12 13 14

61 TC2

62 CVIN1

63 TC1

64 TV

Video Input Signal Measurement

10F

100nF

2 4 6 7

15

16

17

18

19

I2 C

Audio Input Signal V Measurement

Audio Output Signal V Measurement

DC Tests (Audio and Video System)

CXA2149Q

Notes: 1) All +9 V supplies de-coupled close to supply Pins 21, 44, 59 with 10 nF ceramic capacitor. 2) All video outputs are loaded with an emitter follower during test.

CXA2149Q

I2C Bus Register Assignment Status Register Slave Address Data1 1 SYNC1 Status 0 SYNC2 status 0 1 0 Mode Status 0 ADR R/W POR

Control Registers Slave Address Data1 Data2 Data3 Data4 Data5 Data6 LO0 Control ZCD Switch 1 0 CVOUT1 LO1 Control AOUT3 Mute YCOUT1 AOUT1 0 1 0 0 ADR CVOUT2 YCOUT2 AOUT2 AOUT3 AOUT3 Volume Control Fine SYNC2 Switch AOUT3L/R Switch R/W

Group Delay AOUT3 Volume Control Coarse GD1 GD2 SYNC1 Switch Switch Switch

Note. 1. The names CVOUT1, YCOUT1, AOUT1 etc., refer to the particular output or outputs that the register controls. 2. Register undefined.

Status Register Descriptions SYNC Detection Circuits Data1 Bit 6 (SYNC1) and Bit 7 (SYNC2) Indicates whether a video signal is present or not. SYNC1 takes its input from TV and YOUT1. SYNC2 takes its input from CVIN1 and YOUT2. SYNC1 or SYNC2 bit 0 1 Meaning no SYNC SYNC present

15

CXA2149Q

Mode Status Data1 Bits 1 to 5 The mode inputs from the SCART ports are driven at three different voltage levels to indicate the mode format of the port. These inputs are detected and then encoded to the status register in the following manner. Input pin voltage 0 to 2 V 4.5 to 7 V 9.5 to 12 V Meaning Internal TV External 16:9 External 4:3

Mode status bits 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 to 11111

Meaning for MODE1 Internal TV External 16:9 External 4:3 Internal TV External 16:9 External 4:3 Internal TV External 16:9 External 4:3 Internal TV External 16:9 External 4:3 Internal TV External 16:9 External 4:3 Internal TV External 16:9 External 4:3 Internal TV External 16:9 External 4:3 Internal TV External 16:9 External 4:3 Internal TV External 16:9 External 4:3 Not used

Meaning for MODE2 Internal TV Internal TV Internal TV External 16:9 External 16:9 External 16:9 External 4:3 External 4:3 External 4:3 Internal TV Internal TV Internal TV External 16:9 External 16:9 External 16:9 External 4:3 External 4:3 External 4:3 Internal TV Internal TV Internal TV External 16:9 External 16:9 External 16:9 External 4:3 External 4:3 External 4:3 Not used

Meaning for MODE3 Internal TV Internal TV Internal TV Internal TV Internal TV Internal TV Internal TV Internal TV Internal TV External 16:9 External 16:9 External 16:9 External 16:9 External 16:9 External 16:9 External 16:9 External 16:9 External 16:9 External 4:3 External 4:3 External 4:3 External 4:3 External 4:3 External 4:3 External 4:3 External 4:3 External 4:3 Not used

16

CXA2149Q

Power on Reset Data1 Bit 0 After power on this bit will be set to 1 when DVCC, Pin 44, passes through a defined threshold level. The control registers are then defined as below. After the first write command the bit will be reset to 0. CVOUT1=CVOUT2=1001, LO0 switch=LO1 switch=1, YCOUT1=YCOUT2=111, ZCD switch=AOUT3 mute=1, AOUT1=AOUT2=111, Group delay=10000, AOUT3=111, AOUT3 volume control coarse=AOUT3 volume control fine=111, AOUT3L/R switch=00, GD1 switch=GD2 switch=1, SYNC1 switch=SYNC2 switch=1.

Control Register Descriptions Video Inputs CVOUT1 Data1 Bits 4 to 7 These bits select the input signal that will be output on the CVOUT1 pin. CVOUT1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 to 1111 Input or function selected TV CVin1 CVin2 Y1 Y2 Y3 Y1+C1 Y2+C2 Y3+C3 Mute Not used

CVOUT2 Data1 Bits 0 to 3 These bits select the input signal that will be output on the CVOUT2 pin. CVOUT2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 to 111 Input or function selected TV CVin1 CVin2 Y1 Y2 Y3 Y1+C1 Y2+C2 Y3+C3 Mute Not used 17

CXA2149Q

YCOUT1 Data2 Bits 3 to 5 These bits select the input signals that will be output on the YOUT1/COUT1 pins. YCOUT1/2 000 001 010 011 100 101 110 111 Input or function selected TV and Mute CVin1 and Mute CVin2 and Mute Mute and Mute Y1 and C1 Y2 and C2 Y3 and C3 Mute and Mute

YCOUT2 Data2 Bits 0 to 2 These bits select the input signals that will be output on the YOUT2/COUT2 pins. YCOUT2 000 001 010 011 100 101 110 111 Input or function selected TV and Mute CVin1 and Mute CVin2 and Mute Mute and Mute Y1 and C1 Y2 and C2 Y3 and C3 Mute and Mute

18

CXA2149Q

Audio Inputs AOUT1 Data3 Bits 3 to 5 These bits select the input signal that will be output on the ROUT1 and LOUT1. AOUT1 bits 000 001 010 011 100 101 110 111 Input or function selected Mute LTV and RTV LV1 and RV1 LV2 and RV2 LV3 and RV3 LV4 and RV4 LV5 and RV5 Mute

AOUT2 Data3 Bits 0 to 2 These bits select the input signal that will be output on ROUT2 and LOUT2 AOUT2 bits 000 001 010 011 100 101 110 111 Input or function selected Mute LTV and RTV LV1 and RV1 LV2 and RV2 LV3 and RV3 LV4 and RV4 LV5 and RV5 Mute

AOUT3 Data4 Bits 0 to 2 These bits select the input signal that will be output on ROUT3 and LOUT3 AOUT3 bits 000 001 010 011 100 101 110 111 Input or function selected Mute LTV and RTV LV1 and RV1 LV2 and RV2 LV3 and RV3 LV4 and RV4 LV5 and RV5 Mute

19

CXA2149Q

Group Delay Switches Data1 Bit 7 (GD1 Switch) and Bit 6 (GD2 Switch) Switch the respective group delay function on or off. GD2 switches on and off the group delay on the TV input and GD1 switches on and off the group delay on the CVIN1 input. GD1 or GD2 bit 0 1 Group delay function off on

Group Delay Control Data4 Bits 3 to 7 Used to control the variation in group delay. If no adjustment is required then set a value 10000. Group Delay bits 00000 11111 Change in the Max. delay frequency 800 kHz +800 kHz

AOUT3 Volume Control Coarse Data5 Bits 5 to 7 Selects the gain for the internal audio amplifiers in 8 dB steps. Coarse bits 000 111 Gain of AOUT3 channels 0 dB 56 dB

AOUT3 Volume Control Fine Data5 Bits 2 to 4 Selects the gain for the internal audio amplifiers in 1 dB steps. Fine bits 000 111 Gain of AOUT3 channels 0 dB 7 dB

AOUT3L/R Switch Data5 Bits 0 and 1 Controls which of channel 3s left or right channels is output to LOUT3 and ROUT3, respectively. AOUT3L/R bits 00 01 10 11 Output to LOUT3 and ROUT3 Normal Left channel Right channel Inverted

20

CXA2149Q

AOUT3 Mute Switch Data3 Bit 6 Mutes the LOUT3 and ROUT3 channels at the electronic volume control output so that a click free audio channel change can take place. AOUT3 mute bit 0 1 Meaning Mute off Mute on

The normal sequence for a click free channel change is as follows:1. Mute the channel 3 outputs (AOUT3 mute=1) with zero cross detection on (ZCD switch=1). 2. Change the channel 3 audio source, AOUT3L/R control. 3. Un-mute the channel 3 outputs still with zero cross detection on. LO0 or LO1 Control Data2 Bit 7 (LO0 control) and Bit 6 (LO1 control) Used to control the switching of the open collector outputs. The output transistor emitters are connected to digital ground. Each output is capable of sinking 1 mA. LO0 or LO1 bit 0 1 Collector output Low impedance High impedance

Zero Cross Detection Switch Data3 Bit 7 Switches the ZCD function on or off. When the ZCD is on, a volume control change or mute instruction sent via the I2C bus will only be implemented when a minimal, ie., zero cross, signal amplitude is detected. ZCD bit 0 1 Meaning ZCD off ZCD on

SYNC ID Switches Data6 Bit 5 (SYNC1 Switch) and Bit 4 (SYNC2 Switch) Switches the respective SYNC ID circuit to an input our output. SYNC1 switches between the TV input and YOUT1 output. SYNC2 switches between the CVIN1 input and YOUT2 output. SYNC1 or SYNC2 bit 0 1 Input to SYNC ID YOUT1 and YOUT2 YV and CVIN1

External Logic Inputs and Output Hardware Mute The hardware mute (Pin 17) provided will mute all audio outputs when the pin voltage exceeds 2.5 V. In this case the muting will be instantaneous. SCART Modes Three Mode inputs (Pins 18, 19 and 20) are used to allow the format identification of up to three SCART ports. See the description for mode status. LO0 and LO1 Logic Outputs LO0 and LO1 are open collector output I2C controllable logic switch for any external switching functions an application may require. See the description for LO0 and LO1 control.

21

9V 10 600 600 10 600 10 600 10 10

10

Application Diagram

0.1 1 1 1 1 1 0.1

0.1

0.1

51
C2 NC C3 RV1 RV2 RV3 RV4 RTV 32 1 AGND 31 LV1 30 LV2 29 LV3 28 LV4 27 1 DVCC DGND TRAP2 LOUT2 YOUT2 LOUT1 RV5

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

ROUT2

VGND2

COUT2

52 C1 53 TRAP3 54 Y3 55 VBIAS 56 Y2 57 VGND1 58 Y1 CXA2149Q 59 VVCC1 60 CVIN2 61 TC2 62 CVIN1 63 TC1 64 TV

REXT TVOUT RGD4 RGD3 LO0 RGD2 RGD1 LO1 CVOUT1 TRAP1 MODE1 YOUT1 VVCC2 COUT1

10p

180

0.1

0.1

CVOUT2

ROUT1

0.1

Y2 DRIVE 10

0.1

Y1 DRIVE

0.1 LV5 26 LTV 25 ROUT3 24 LOUT3 23 ABIAS 22 AVCC 21 MODE3 20 SCL SDA ADR MUTE MODE2

22
1
10p 100p 100p 10p 10 10 39k (1%)

0.1

9V

0.1

600 600 10

0.1

10 10

9V

68k

0.1

0.1

9V

0.1 0.1

9V

68k

0.1

9
180

10
10

11

12

13
0.1

14
220

15
220

16

17

18

19

CXA2149Q

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

0.1 560 560

0.1

10p

9V

CXA2149Q

Applications Notes (see circuits diagram on next page). 1. Care should be taken with polarity sensitive capacitors. The respective bias voltages for audio and video inputs and outputs are as follows. C1, C2, C3, COUT1 and COUT2 are biased at approximately 4.5 V. TV, CVIN1, CVIN2, Y1, Y2 and Y3 are SYNC tip clamped at approximately 3.9 V. CVOUT1, CVOUT2, TVOUT have their SYNC tip output at approximately 3.5 V. YOUT1, YOUT2 have their SYNC tip output at approximately 3.3 V. ABIAS and VBIAS are equal to approximately 4.5 V. 2. Connect ADR to VCC when wishing to set the slave address to 92H. 3. Setting the MUTE pin to 2.5 V or more can mute the audio outputs. 4. TRAP1, TRAP2 and TRAP3 are set for a 3.58 MHz subcarrier. For a 4.43 MHz subcarrier typical values for the two traps would be 47 and 27 p, respectively. Values may require adjustment dependent upon the application. Each trap gives 6 dBs of attenuation at the desired frequency. 5. LO0 and LO1 connected to ground when not required. 6. Connect all NC to ground in application.

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CXA2149Q

Example of Representative Characteristics

Typical audio system frequency response LTV-LOUT1 4 Audio system input/output gain [dB] 2 0 2 4 6 8 10 1000

10000 100000 Frequency [Hz]

1000000

Video system typical frequency response 8 Video system input/output gain [dB] 6 4 2 0 2 4 6 8 10 1 10 Frequency [MHz] 100

TV-CVOUT1 Typical audio system distortion vs. Input amplitude 0 10 Total harmonic distortion [dB] 20 30 40 50 60 70 80 90 100 110 0.5 1 1.5 2 Input amplitude [Vrms] 2.5 3 f=1kHz 400Hz HPE, 80kHz LPF Y1-CVOUT2 (Mx)

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CXA2149Q

Package Outline

Unit : mm

64PIN QFP(PLASTIC)

23.9 0.4 + 0.4 20.0 0.1

51 33

+ 0.1 0.15 0.05 0.15

52

32

17.9 0.4

+ 0.4 14.0 0.1

64

20

+ 0.2 0.1 0.05

1 1.0 + 0.15 0.4 0.1

+ 0.35 2.75 0.15 0.2 M 0 to10

PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g

25

0.8 0.2

19

16.3