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8051 Interfacings
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ADC-DAC Interfacing
Analog signals are very common inputs to embedded systems .Most transducers and sensors such as temperature ,pressure ,velocity ,humidity are analog. Therefore we need to convert these analog signals in to digital so that 8051 can read it.
ABOUT IC PinOut
CS Chip Select , active low RD Read Digital data from ADC, H-L edge triggered WR -- Start conversion, L-H pulse edge triggered INTR -- end of conversion, Goes low to indicate conversion done Data bits -- D0-D7 CLK IN & CLK R CLK IN is an input pin connected to an external clock source when an external clock is used for timing. However, ADC804 has an internal clock generator. To use the internal clock generator of the ADC804, the CLK IN and CLK R pins are connected to a capacitor and a resistor. In that case, the clock frequency is determined by the equation. f = 1/1.1RC R=10K and C=150pF f=606Hz the conversion time is 110us.
Step Size a Smallest change (2 x Vref/2)/ 256 for ADC804 for eg for step size 10mv ,digital output on D0-D7 changes by one count for every 10mv change of the input analog voltage.
Data Out
for input vtg. of 2.56 volts (Vref=1.28 volts) and stepsize of 10mv Dout =2560/10 =256 or FF that is full scale output.
Conversion Time
Greater than 110us for ADC804
Resolution
8 bits for ADC804
Algorithm
Make CS=0 and send a low-to-high to pin WR to start the conversion.
Keep monitoring INTR If INTR =0, the conversion is finished and we can go to the next step. If INTR=1, keep polling until it goes low. After INTR=0, we make CS=0 and send a high-to-low pulse to RD to get the data out of the ADC804 chip.
ASSEMBLY LANGUEGE
(A51)
ADC_IO: mov P1, #0xff ; To configure as input AGAIN clr p3.7 ;Chip select setb P3.6 ;RD=1 clr P3.5 ;WR=0 setb P3.5 ;WR=1- low to high transition WAIT: jb P3.4, WAIT ;wait for INTR clr p3.7 ;generate cs to ADC clr P3.6 ;RD=0 -High to low transition mov A, P1 ;read digital o/p sjmp AGAIN
Algorithm
Notice that the ADC808/809 that there is no self-clocking and the clock must be provided from an external source to the CLK pin. (you can use programmable clock oscillator to enable or disable clock by programmable bit. ) Select an analog channel by provide bits to A, B, C. Enable clock Activate ALE with a low-to-high pulse. Activate SC with a high-to-low pulse (start conversion) The conversion is begun on the falling edge of the start conversion pulse. you can use circuit like Monitor EOC Pin .After conversion this pin goes high. Activate OE with a high-to-low pulse to read data out of the ADC chip.