ECE 546 - VLSI Systems Design Lecture 14: Dynamic Latches Latches, FlipFlip-Flops, & Pipelining

Fall 2011 W. Rhett Davis NC State University

with significant material from Rabaey, Chandrakasan, and Nikoli Rabaey, Chandrakasan,
W. Rhett Davis NC State University Slide 1 ECE 546 Fall 2011

Announcements

HW#6 Due Tuesday Start forming project groups

3-person g p p groups e-mail me your names and Unity IDs I will assign you a group number and post it to the class webpage

W. Rhett Davis

NC State University

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ECE 546

Fall 2011

Summary of Last Lecture

Is this a positive or a negative latch? Does is work b l k by loop-breaking b ki or loop-forcing? How should you size the transistors?

CLK D CLK Q

How do you calculate the minimum clock-period for a design? What are the types of timing constraints? Which one is the most critical to satisfy? Using the skew definition from the last lecture, if the clock edge at the source register arrives BEFORE the clock edge at the destination register, is the skew positive or negative?
NC State University Slide 3 ECE 546 Fall 2011

W. Rhett Davis

Todays Lecture

Dynamic Latches & Registers (7 3) (7.3) Pipelining (7 5) Pi li i (7.5)

W. Rhett Davis

NC State University

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ECE 546

Fall 2011

Static vs. Dynamic Latches

Static Dynamic (charge-based)
CLK
CLK

Q CLK D

CLK

CLK

W. Rhett Davis

NC State University

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ECE 546

Fall 2011

Dynamic Flip-Flop

What are the dynamic nodes? Rising-Edge or Falling Edge Triggered? Estimate tsu, thold, and tc-q based on the delays of the transmission gates and inverters.
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Clock-Overlap

Problem: Both latches are transparent Assume tsu and thold are relative to CLK What timing constraints are needed to ensure proper operation?
Falling-edge (ensure input doesnt propagate to slave) Rising-edge (ensure input doesnt propagate to master)

W. Rhett Davis

NC State University

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ECE 546

Fall 2011

Clock-Overlap

Consider CLK later than CLK: Both latches are still transparent Assume tsu and thold are relative to CLK What timing constraints are needed to ensure proper operation?
Falling-edge (ensure input doesnt propagate to slave) Rising-edge (ensure input doesnt propagate to master)

W. Rhett Davis

NC State University

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ECE 546

Fall 2011

C2MOS (Clocked CMOS) Register

Insensitive to CLK and CLK overlap

P Prevents a change on D f t h from affecting Q during overlap ff ti d i l
VDD M2 VDD M6

CLK D CLK

M4 X M3 CL1

CLK

M8 Q CL2

CLK

M7

M1

M5

Master Stage
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Slave Stage
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Insensitive to Clock-Overlap
VDD M2 0 D M4 X 0 VDD M6 M8 Q D 1 M1 (a) (0-0) overlap

VDD M2

VDD M6

X M3 M1 (b) (1-1) overlap

Q 1 M7 M5

M5

D 01: doesnt change X g D 10: changes X, but not Q

NC State University

D 01: changes X, but not Q g , D 10: doesnt change X

ECE 546 Fall 2011

W. Rhett Davis

Slide 10

Disadvantage to
VDD M2

2MOS C
VDD M6

CLK D CLK

M4 X M3 CL1

CLK

M8 Q CL2

CLK

M7

M1

M5

Master Stage

Slave Stage

Short-Circuit currents destroy charge stored at X and Q For correct operation, ensure that triseCLK < 5 tc q c-q
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Other Latches: TSPC

VDD VDD VDD VDD

Out In CLK CLK In CLK CLK Out

Positive latch Negative latch (transparent (t a spa e t when C e CLK= 1) (transparent when C ) (t a spa e t e CLK= 0)
W. Rhett Davis NC State University Slide 12 ECE 546 Fall 2011

TSPC Register
Y X

_ Q

Positive-Edge Triggered P iti Ed T i d

Negative-Edge T i N ti Ed Triggered d

Not susceptible to clock-overlap, but still susceptible t clock skew tibl to l k k

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TSPC Negative-Edge FF
V

time

Positive Input Edge followed by a Negative Clock Edge

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TSPC Negative-Edge FF
V

time

Negative Input Edge followed by a Negative Clock Edge

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Todays Lecture

Dynamic Latches & Registers (7 3) (7.3) Pipelining (7 5) Pi li i (7.5)

W. Rhett Davis

NC State University

Slide 16

ECE 546

Fall 2011

Pipelining
RE EG

RE EG

REG

REG

REG

REG
CLK

CLK
RE EG

log

Out
b

CLK

log

Out

RE EG

CLK

CLK

CLK

CLK

CLK

Reference R f

Pipelined

W. Rhett Davis

NC State University

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ECE 546

Fall 2011

Advantages of Pipelining
Latency increases, but so does Throughput (avg operations per second) (avg. Example: tc-q, tsu =1 / tadd, tabs= 2 / tlog = 3

B f Before Pipelining Pi li i
Tmin = tc-q + tadd + tabs + tlog + tsu = 9 Delay for 1 operation = Tmin = 9 i Delay for 5 operations = 5*Tmin = 45

After Pipelining
Tmin = tc-q + max(tadd, tabs, tlog) + tsu = 5 Delay for 1 operation = 3*Tmin = 15 D l f 5 operations = 7*Tmin = 35 Delay for ti
W. Rhett Davis NC State University Slide 18 ECE 546 Fall 2011

Advantages of Pipelining

Can be Lower-Energy due to Operand Isolation Can d C reduce glitching i complex l i networks lit hi in l logic t k

Before:

After:

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NC State University

Slide 19

REG

ECE 546

Fall 2011

Latch-Based Pipeline
CLK CLK CLK In C1 F C2 G C3 Out

CLK CLK

Compute F

compute G

The lower tc-q and energy of latches makes th Th l d fl t h k them a good d choice for high-performance pipelines Recall that pipeline should alternate p pp pos. and neg. latches g Problem: Sensitive to clock overlap (race btw. In1 and In2)
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Solution: NORA-CMOS

Use C2MOS latches A C2MOS based pipeline is race free as long as all of the MOS-based logic functions between the latches are non-inverting Example: 0-0 Overlap p p

Inverting Logic: Falling-edge Falling edge at 1st latch can cause transition at 2nd latch
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Non-Inverting Logic: Falling-edge Falling edge at 1st latch cannot affect at 2nd latch
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Non-Inverting Logic

Non-Inverting Logic is logic for which a positive edge on any input can produce only a positive edge at the output If an expression contains only AND and OR with no inversions, it is non-inverting Examples
Non-Inverting:
A BC D

Inverting:

A B C D A B AB AB
W. Rhett Davis NC State University Slide 22 ECE 546 Fall 2011

Example
Implement the function F=AB+BC+D as a two-stage two stage C2MOS Pipeline Use the following architecture:

f A, B, C , D A, B, C , D

g f A, B, C , D

f
A, B, C , D f A, B, C , D

g f A, B, C , D

positive non- negative nonpositive latches inverting latches inverting latches logic logic
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Example

Decompose F into non-inverting functions f and g:

F AB BC D

What logic implements f()? What logic implements g()?

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Example

Circuit Diagram:
F A B B C D

NOTE: NORA CMOS: Use Dynamic Domino-Gates NORA-CMOS: Domino Gates with this structure for very-high performance
W. Rhett Davis NC State University Slide 25 ECE 546 Fall 2011

Summary

Learned how to estimate setup- and hold-times using delays of inverters and transmission gates. Learned how to express timing constraints of a flip-flop to ensure proper operation during clock-overlap. p p p g p Learned how to make a flip-flop that is insensitive to p (C ) clock-overlap ( 2MOS) Learned how to make an edge-triggered flip-flop that does not require two clock-phases (TSPC) clock phases Learned how to build a very-high speed pipeline using C2MOS latches and non-inverting logic
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W. Rhett Davis