Play around with the circuit to see that it works

Four-Bit Modulo-16 D-Flipflop Counter

As we might say that the heart of a living person beats as time passes, even so a counter is a logic circuit that counts as time passes. The interactive circuit above is a four-bit counter that is designed to count from zero (0000) to fifteen (1111) as time passes. When it reaches fifteen, it loops back and starts again at zero; and so on forever (i.e. as long as time exists). Since our counter counts from the low value zero to the high value fifteen, we say it is an up-counter. Furthermore, we say it is a modulo-sixteen counter because there are sixteen numbers between zero and fifteen inclusive. Designing counters using Data Latches can be a simple and straightforward process. For example, if you have n data latches, then you can design a counter that can count from 0 to 2n 1: This means if you want to count from zero to fifteen, then you need to solve for n in the equation 2n -1 = 15; which solves as n (= log 16 / log 2) = 4; which means you need 4 data latches. In the next section we will go through the process of designing our modulo-16 counter. But, before we do, here is a picture (Figure 1) of the finished product with the labels that we will be referring to in the rest of the article. The uppercase labels W, X, Y, and Z, which are the outputs of the combinational circuits, are referred to as the next state signals, the flipflop input signals, or the flipflop input equations. The lowercase labels w, x, y and z are referred to as the output signals or the present state equations.

Figure 1: Labeled Modulo-16 D-Flipflop Counter DESIGN AND SYNTHESIS Generally, the problem statement will read: Design a circuit to count from zero to fifteen. Include a switch to enable pausing the circuit. As it is always a good idea to try to visualize what the question is asking, we will start our design by drawing a diagram using what we know. We know the following: if the current count is zero (0), then the next count must be one (1); the next count after one must be two (10); then three (11); then four (100); then so on until the count reaches fifteen (1111). Another detail we know is that we need to include a switch to enable freezing/pausing the circuit between counts. We can draw this sequence of numbers as shown in Figure 2 below.

Figure 2 is formally known as a state diagram because each ellipse represents one of the states that the circuit can ever possibly be in, and each arrow shows how the circuit moves from state to state depending on whether the enable switch (E) is 1 or 0. The colored arrow shows that after the circuit has reached the number fifteen (1111), it will restart at zero (0000) and continue on from there.

Figure 2: Four-Bit Counter State Diagram Although a state diagram is very easy to understand, in order to use the state diagram to build a circuit, we need to transform the diagram into a table because it is easier to write the Boolean expressions from a table description of the problem (kind of like truth tables). We show the state transition table in Table 1 below. Notice that when E = 0, the circuit will not change state; only when E = 1 does the counting continue. NEXT STATE E=0 0000 0001 0010 0011 0100 0101 0110 0111 0001 0010 0011 0100 0101 0110 0111 1000 E=1

Present State 0000 0001 0010 0011 0100 0101 0110 0111

1000 1001 1010 1011 1100 1101 1110 1111 Table 1

1000 1001 1010 1011 1100 1101 1110 1111

1001 1010 1011 1100 1101 1110 1111 0000

Just as we would in a truth table, we must label the bits of the state transition table so as to be able to derive Boolean expressions from the table. So we recreate the table as Table 2, with the bits labeled. We use lower cases for the present states and upper cases for the next states. NEXT STATE E=0 WXYZ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 E=1 WXYZ

Present State wxyz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 2