Embedded Systems 7.

System Components

Lothar Thiele

Swiss Federal Institute of Technology

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Computer Engineering and Networks Laboratory

Contents of Course
1. Embedded Systems Introduction 2. Software Introduction 3. Real-Time Models 4. 4 Periodic/Aperiodic Tasks 5. Resource Sharing 6. Real-Time OS 12. Model Based Design 7. System Components 8. Communication 9. Low Power Design 10. Models

3.4

11. Architecture 11 Architect re Synthesis

Software and Programming

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Processing and Communication

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Hardware
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Embedded System Hardware

Embedded system hardware is frequently used in a loop (hardware in a loop):
this course

actuators embedded system

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Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW

Programmable Hardware ASICs System-on-Chip

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Implementation Alternatives
General-purpose processors

3.4.1

Performance Power Efficiency

Application-specific instruction set processors (ASIPs) Microcontroller DSPs (digital signal processors)

Flexibility

Programmable hardware FPGA (field-programmable gate arrays)

Application-specific integrated circuits (ASICs)

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General-purpose Processors General purpose

High performance
Hi hl optimized circuits and t h l Highly ti i d i it d technology Use of parallelism
superscalar: dynamic scheduling of instructions super-pipelining: instruction pipelining, branch prediction, speculation

3.4.3

complex memory hierarchy

Not suited for real-time applications

Execution times are highly unpredictable because of intensive resource sharing and dynamic decisions

Properties P ti
Good average performance for large application mix Hi h power consumption High ti
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Pentium P4

Dual Core

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System Specialization
The main difference between general purpose highest volume microprocessors and embedded systems i l i d b dd d is specialization. Specialization should Speciali ation sho ld respect flexibility fle ibilit
application domain specific systems shall cover a class of applications some flexibility is required to account for late changes, debugging

System analysis required

identification of application properties which can be used for specialization quantification of individual specialization effects
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Architecture Specialization Techniques

system design DSP subsystems micro controllers conf. HW f functions (FPGA) memory blocks memory cells

processors system component t design logic design

coprocessors

buses

data paths

interfaces

logic cells

switch elements

A simple system design classification

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Example: Code-size Efficiency Code size

CISC machines: RISC machines designed for run-time-, not for code-size-efficiency. Compression techniques: key idea

(de)compressor

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Example: Multimedia Instructions Multimedia-Instructions

Multimedia instructions exploit that many registers, adders etc are quite wide (32/64 bit) whereas most multimedia data types are bit), narrow ( g (e.g. 8 bit p color, 16 bit p audio sample p channel) per , per p per ) 2-8 values can be stored per register and added. E.g.:

+ 4 additions per instruction; carry disabled at word boundaries. boundaries

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Example: Heterogeneous registers

Example (ADSP 210x):
P D

AX

AY AF

MX

MY MF

Addressregisters A0, A1, A2 .. +,-,.. Address g generation unit (AGU)

AR

* +,MR

Different functionality of registers A AX AY AF MX MY MF MR Diff tf ti lit f i t An, AX, AY, AF,MX, MY, MF,
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Example: Multiple memory banks or memories

P D

AX

AY AF

MX

MY MF

Addressregisters A0, A1, A2 .. +,-,.. Address generation unit (AGU)

AR

* +,+
MR

Simplifies p p parallel fetches

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Example: Address generation units

Example (ADSP 210x):
Data memory can only be fetched with address contained in A, but this can be done in parallel with operation in main data p p path (takes ( effectively 0 time). A := A 1 also takes 0 time, : same for A := A M;

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Example: Modulo addressing

Modulo addressing: Am++ Am:=(Am+1) mod n (implements ring or circular buffer in memory) sliding window x

t1

x[t]: value accessed at time t

.. x[t1-1] [t1 1] x[t1] x[t1-n+1] x[t1-n+2] .. Memory, t=t1

.. x[t1-1] x[t1] [ ] x[t1+1] x[t1-n+2] .. Memory, t2=t1+1

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Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW

Programmable Hardware ASICs System-on-Chip

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Control Dominated Systems

Reactive systems with event driven behavior Underlying semantics of system description (input model of computation) typically (coupled) Finite State Machines or Petri Nets
I/O signals g

output signals output signals

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Microcontroller
control-dominant applications
supports process scheduling and synchronization preemption (interrupt) (interrupt), context switch short latency times

low power consumption peripheral units often integrated suited for real-time applications

8051 core
SIECO51 (Siemens)

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Microcontroller as a System on Chip System-on-Chip

processor 80C51 15 - vector interrupt timer 0 (16 bit) timer 1 (16 bit) timer 2 (16 bit) 8K8 ROM (87C552 8K8 EPROM)256 x 8 RAM

complete system timers I2C-bus and par./ser. interfaces for communi communication A/D converter watchdog (SW activity timeout): safety on-chip memory interrupt controller p

A/DC 10 - bit PWM UART watchdog (T3) I2C parallel ports 1 through 5 p p g

Philips 83 C552: 8 bit-8051 based microcontroller

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Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW

Programmable Hardware ASICs System-on-Chip

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Data Dominated Systems

Streaming oriented systems with mostly periodic behavior b h i Underlying semantics of input description e.g. flow graphs (input model of computation) ( input computation )
B f1 B f2 B f3 B

f2

B: buffer

Application examples: signal processing control processing, engineering

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Digital Signal Processor

optimized for data-flow applications suited for simple control flow parallel hardware units (VLIW) specialized instruction set high data throughput zero-overhead loops specialized memory suited for real-time applications

3.4.3.1

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MAC (multiply & accumulate)

sum = 0.0; for (i=0; i<N; i++) sum = sum + a[i]*b[i];

zero overhead zero-overhead loop (repeat next instruction N times)

MAC - Instruktion

LDF LDF RPTS MPYF3 || ADDF3

0, R0 0, R1 N *(AR0)++, *(AR1)++, R0 R0, R1, R1

TMS320C3x Assembler (Texas Instruments)

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Very Long Instruction Word (VLIW)

Key idea: detection o poss b e pa a e s to be do e by ey dea detect o of possible parallelism done compiler, not by hardware at run-time (inefficient).

3.4.3.3

VLIW: parallel operations (instructions) encoded in one long word (instruction packet), each instruction controlling one functional unit. E.g.:

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Explicit Parallelism Instruction Computers

The TMS320C62xx VLIW Processor as an example of EPIC: 31 Instr. A 0 31 0 Instr. B 0 31 1 Instr. C 0 31 1 Instr. D 0 31 0 Instr. E 0 31 1 Instr. F 0 31 1 Instr. G 0 0

Cycle C l 1 2 3
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Instruction I t ti A B E C F D G
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Example: Philips TriMedia TM1000

SDRAM Main Memory Interface
32 bits data 400 MB/sec

CCIR601/656 YUV 4:2:2 38 MHz (19 Mpix/sec) Stereo digital audio I2S DC-100 kHz 2/4/6/8 ch. digital audio I2S DC-100 kHz I2C bus to b t camera, etc.

Video In

VLD p Coprocessor Video Out

Huffman decoder Slice-at-a-time MPEG-1 & 2 CCIR60/656 YUV 4:2:2 80 MHz (40 Mpix/sec)

Audio In

Audio Out

Timers Synchronous Serial S i l Interface Image Coprocessor

I2C Interface
32K

V.34 V 34 or ISDN Front End Down & up scaling YUV RGB 50 Mpix/sec PCI (32 bits, 33 MHz)

VLIW I$ CPU 16K

D$
Rolf Ernst

TM - 1000

PCI Interface

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Example: M3 VLIW DSP Processor

Designed at TU Dresden (G. Fettweis et al.)

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Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW

Programmable Hardware ASICs System-on-Chip

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FPGA Basic Strucutre

Logic Units I/O Units Connections

3.4.4

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FPGA - Classification
Granularity of logic units:
Gate, tables, memory, functional blocks (ALU, control, data path, processor)

Communication network:
Crossbar hierarchical mesh tree Crossbar, mesh,

Reconfiguration:
fixed at production time, once at design time, dynamic during run-time

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Floor plan Floor-plan of VIRTEX II FPGAs

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Virtex Logic Cell

[ and source: Xilinx Inc.: Virtex-II Pro Platform FPGAs: Functional Description, Sept. 2002, //www.xilinx.com]
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Virtex II Pro Devices include up to 4 PowerPC processor cores

[ [ and source: Xilinx Inc.: Virtex-II Pro Platform FPGAs: Functional Description, Sept. 2002, //www.xilinx.com]
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Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW

Programmable Hardware ASICs System-on-Chip

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Application Specific Circuits (ASICS)

Custom-designed circuits necessary C t d i d i it
if ultimate speed or energy efficiency is the goal and large numbers can be sold.

Approach suffers from

long design times, lack of flexibility (changing standards) and high costs (e.g. Mill. $ mask costs).
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Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW

Programmable Hardware ASICs System-on-Chip

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Configurable System On Chip System-On-Chip

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System on a Chip System-on-a-Chip

[NTNU] Tensilica synthesized and g p Confgurable microprocessor (Soft IP)

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Trend: multiprocessor systems-on-a-chip (MPSoCs) p y p( )

http://ww ww.mpsoc c-forum.org g/2007/slid des/Hattori.pdf
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Multiprocessor systems-on-a-chip (MPSoCs) systems on a chip

h http://www w.mpsoc-fo orum.org/2 2007/slide es/Hattori.pdf
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Multiprocessor systems-on-a-chip (MPSoCs) y ( )

h http://www w.mpsoc-fo orum.org/2 2007/slide es/Hattori.pdf
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Multiprocessor systems-on-a-chip (MPSoCs) u t p ocesso syste s o a c p ( SoCs)

h http://www w.mpsoc-fo orum.org/2 2007/slide es/Hattori.pdf
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