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CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-1

CHAPTER 5 – HOMEWORK SOLUTIONS

Problem 5.1-01

Assume that M2 in Fig. 5.1-2 is replaced by a 10kresistor. Use the graphical technique illustrated in this figure to obtain a voltage transfer function of M1 with a 10kload resistor. What is the maximum and minimum output voltages if the input is taken from 0V to 5V?

Solution

A computer generated plot of this problem is shown below. 5
+5V
4
10kΩ
V
out
Μ1
V
in
3
2µm
1µm
2
1
0
V out (V)

012345

V in (V)

Fig. S5.1-01

The maximum output is obviously equal to 5V. The minimum output requires the following calculation assuming that M1 is in the active region.

110x10 -6 ·2[(5-0.7)v out – 0.5v out 2 ] = 5- 10kv out

4.3 v out - v out 2 = 5-v out

2.22

v out 2 – 9.5 v out + 4.504 = 0

This gives, v out (min) = 4.25±4.2945 = 0.5V

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-2

Problem 5.1-02

Using the large-signal model parameters of Table 3.1-2, use Eqs. (1) and (5) to calculate the values of v OUT (max) and v OUT (min). Compare with the results shown on Fig. 5.1-2 on the voltage transfer function curve.

Solution From Eq. (5.1-1),

V out

(max)

can be calculated as

V

out

(max) = Tp

VV

DD

= 4.3 V

5V W 2
= 1µm
1µm
L 2
I D
M2
+
M1
v
OUT
+
W 1
= 2µm
v
IN
1µm
L 1
-
-
Fig. S5.1-02

From Eq. (5.1-5),

V

out

(min) =

V

DD

V out

V

T (min)
can be calculated as
(
V
− V
)
DD
T
β
2
1 +
β
1

V out (min)

=−

5

.

07 (
5
− 07
.
)
( 50
)( )
1
1 +
( 110
)( )
5

= 0.183 V

Problem 5.1-03

What value of β 1 /β 2 will give a voltage swing of 70% of V DD if V T is 20% of V DD ? What is the small-signal voltage gain

corresponding to this value of β 1 /β 2 ?

Solution

Given

V

T

= 0.2V

and

(

V

out

DD

(max) V

(min) = 0.7V

)

out

DD

From Eq. (5.1-1) and (5.1-5)

or,

V

out

(max)

V

out

(min)

= (
V
− V
)
DD
T
β
2
1 +
β
1

0.7 V

DD

=

(

V

DD

0.2

V

DD

)

1 +

β

2

β 1

  1 + 2
β
8 
2
β
 = 
7
1

5V W
2
= β 2
L
2
I
D
M2
+
M1
v
OUT
+
W
1
=
β
v
1
IN
L
1
-
-
Fig. S5.1-03 β
2
β
1

= 0.306

The small-signal voltage gain can be given by

A

v

≅− g
β
m 1
1
=−
g
β
m 2
2

= -1.8 V/V

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-3

Problem 5.1-04

What value of V in will give a current in the active load inverter of 100µA if W 1 /L 1 = 5µm/1µm and W 2 /L 2 = 2µm/1µm? For this value of V in , what is the small-signal voltage gain and output resistance?

Solution

Assuming

5V W 2
= 2µm
1µm
L 2
I D
M2
+
M1
v
OUT
+
W 1
= 5µm
v
IN
1µm
L 1
- -
Fig. S5.1-04

M 1 is operated in saturation

I

D

1

100

  ( ) 2     W  V in − V T  L  1   2  ( V in − 0 7 . ) 2 110 µ)( 5 )   2

=

'

N

K

µ = (

or, → V in = 1.303V
(
'
)
g
K
 W   L
N
m
1
A
v ≅−
=−
= -2.345 V/V
'
g
(
K
)
L
 
W
m
2
P
1
2
1
R
= 7.07 kΩ
out

The small-signal gain can be given by

The output resistance can be given by

g m 2

Problem 5.1-05

Repeat Ex. 5.1-1 if the drain current in M1 and M2 is 50µA.

Solution

From Eqs. (5.1-1) and (5.1-5) we get v OUT (max) = 4.3V

v OUT (min) = 5 – 0.7 -

From Eq. (5.1-7) we get,

5-0.7

1 + (50·1/110·2) = 0.418 V  v

out

v in

g

m1

= -

g ds1 +g ds2 +g m2 =

148.3

2.0 + 2.5+ 70.71 = -1.972 V/V

From Eq. (5.1-8) we get,

R out =

1

g ds1 +g ds2 +g m2 =

10

6

2.0 + 2.5 + 70.71 = 13.296 k

The zero is at,

z 1 =

C gd1 = 148.3µS

g

m1

0.5ff

= 2.966x10 11 rads/sec 47.2 GHz

The pole is at,

1

p 1 = -ω -3dB = R out (Cbd1+C bd2 +C gs2 +C L ) =

1

(13.296k)(1.0225pF)

= 73.555x10 6 rads/sec. 11.71 MHz

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-4

Problem 5.1-06

Assume that W/L ratios of Fig. P5.1-6 are W 1 /L 1 = 2µm/1µm and W 2 /L 2 = W 3 /L 3 = W 4 /L 4 = 1µm/1µm. Find the dc value of V in that will give a dc current in M1 of 110µA. Calculate the small signal voltage gain and output resistance of Fig. P5.1-6 using the parameters of Table 3.1-2.

Solution

Assuming all transistors are in saturation and ideal current mirroring

V DD M2
M3
M4
+
M1
+
v OUT
v
IN
-
-

Figure P5.1-6

100µA 2
( V
)
I
= K
D
1
N
'  W 
− V
in
T
L
2 
1
2 
− 0 7
.
)
( V in
or,
110
µ = (
110
µ)(
2
)
→ V in = 1.7V
2 
The small-signal voltage gain can be given by
'
g
K
 W   L
  I
m
1
N
D
1
A
V ≅−
=−
'
g
K
L
 
W
 I
 
= -6.95 V/V
m
2
P
1
2
D
2
where, I
= I
= 100 µA, and I D2 = 10 µA.
D3
D4

The output resistance can be given by

R

out

1

g m 2

= 31.6 k

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-5

Problem 5.1-07

Find the small-signal voltage gain and the -3dB frequency in Hertz for the active-load inverter, the current source inverter and the push-pull inverter if W 1 = 2µm, L 1 = 1µm, W 2 = 1µm, L 2 = 1µm and the dc current is 50µA. Assume that C gd1 = 4fF, C bd1 = 10fF, C gd2 = 4fF, C bd2 = 10fF and C L = 1pF. M2
M2
M2
V
I
GG2
I
I
D
D
v
v
v
D
OUT
OUT
IN
v
OUT
v
v
IN
IN
M1
M1
M1
Active
Current
Push-
pull
Inverter
Inverter
Inverter

V DD

Figure 5.1-1 Various types of inverting CMOS amplifiers.

Solution

The output resistance can be given by

R out

1

g m 2

=

1

2 50

(

µ)( 1 )(

50

µ) = 14.14 k

The total output capacitance can be given by

C

C

out

CC

=+

L

gs

2

+

bd

211 = 1.029 pF

+

C

gd

+

C

bd

The –3 dB frequency can be given by

f

3 dB

=

1

2π

R

out

C

out

= 10.9 MHz

2. Current-source inverter

The output resistance can be given by

R

out

1

1

+

gg

ds

1

ds

2

I

D

(λ

N

+

λ

P

=

) = 222.22 k

The total output capacitance can be given by

C

out

=

C

L

+

C

gd

2 +

C

bd

CC

211

++

gd

bd

= 1.028 pF

The –3 dB frequency can be given by

f

3 dB

=

1

2π

R

out

C

out

= 0.697 MHz

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-6

Problem 5.1-07 - Continued

3. Push-pull inverter

The output resistance can be given by

R

out

1

1

+

gg

ds

1

ds

2

I

D

(λ

N

+

λ

P

=

) = 222.22 k

The total output capacitance can be given by

C

out

=

C

L

+

C

gd

2

+

C

bd

211 = 1.028 pF

CC

++

gd

bd

The –3 dB frequency can be given by

f

3 dB

=

1

2π

R

out

C

out

= 0.697 MHz

Problem 5.1-08

What is the small-signal voltage gain of a current-sink inverter with W 1 = 2µm, L 1 = 1µm, W 2 = L 2 = 1 µm at I D = 0.1, 5 and 100 µA? Assume that the parameters of the devices are given by Table 3.1-2. 1.
I
= 0.1
µA
D
I
(
0 1
.
µ )
D
1
g
= =
= 1.538 µS
m 1
nV
(
2 5
.
)(
26
m
)
p
t
g
g
m 1
m 1
A
= − (
) = −
= - 170.9 V/V
v
g
I
(
λ
+ λ
)
g ds
1 + ds
2
DN
P
2.
I
= 5
D
µA
W 
'
=
2
K
I
=
31 62 = 31.62 µS
.
g m1
PD 1
L
1
g
g
m 1
m 1
A
=
) = −
= - 70.27 V/V
v
− (
g
I
(
λ
+ λ
)
g ds
1 + ds
2
DN
P
3. I
= 100
D
µA
W 
'
=
2
K
I
= 141 42
.
µS
g m1
PD 1
L
1
g
g
m 1
m 1
A
=
) = −
= -15.71 V/V
v
− (
+ g
I
(
λ
+ λ
)
g ds
1
ds
2
DN
P

2.5V 5V
W
= 2µm
2
L
1µm
2
I
D
M2
+
M1
v
OUT
+
W
= 2µm
1
v
IN
L
1µm
1
-
-

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-7

Problem 5.1-09

A CMOS amplifier is shown. Assume M1 and M2 operate in the saturation region. a.) What value of V GG gives 100µA through M1 and M2? b.) What is the DC value of v IN ? c.) What is the small signal voltage gain, v out /v in , for this amplifier? d.) What is the -3dB frequency in Hz of this amplifier if C gd = C gd = 5fF, C bs = C bd = 30fF, and C L =

500fF? Solution
a)
= V
+V
V GG
T 2
dsat 2
2 I
D 2
V
=
V
+
GG
T 2
'
K
(
WL
)
N
2

= 2.05 V 2 I
D
1
b) VV
=
−−
V
= 3.406 V
in
DD
T 1
K
' (
WL
)
P
1
g
v out
m 1
c)
A
=
=− (
= -24.85 V/V
v
v
g
+ g
)
in
ds
1
ds
2
( g
+ g
)
ds
1
ds
2
d)
f
=
− 3 dB
(
)
CCCCC ++++
gd
1212
gd
bd
bd
L

= 2.51 MHz.

v in

V GG V DD
M1
5µm/1µm
v out
M2
1µm/1µm

Figure P5.1-9

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-8

Problem 5.1-10

A current-source load amplifier is shown.

=C BDP = 100fF, C GDN =C GDP = 50fF, C GSN = C GSP =

100fF, and C L = 1pF, find the -3dB frequency in Hertz.

(b.) If Boltzmann’s constant is 1.38x10 -23 Joules/°K, find the equivalent input thermal noise voltage of this amplifier

at room temperature (ignore bulk effects, η = 0).

Solutions

(a.) The -3dB frequency is equivalent to the magnitude of the output pole which is given as

If C BDN

(a.) V DD
M3
M2
v
out
C
L
100µA
M1
All W/L's
v in
equal 10

Fig. P5.1-10

ω -3dB =

1

R out C out

where R out =

1

g ds1 +g ds2 =

1

100µA(0.04+0.05) =

1

9x10 -6 = 111k

C out = C gd1 +C bd1 +C gd2 +C bd2 +C L = 0.05 + 0.05 + 0.1 + 0.1 +1 pF = 1.3pF 1
0.111MΩ·1.3pF = 6.923x10 6 rads/sec. →
∴ ω -3dB =
(b.) The noise voltage at the output can be written as
g
g
m1
m2
2
2 +
e no 2 =
e n1 2 
g
e n2 2 
g
ds1 +g ds2
ds1 +g ds2

f -3dB = 1.102 MHz

Reflecting this noise voltage back to the input gives the equivalent input noise as, g
 
e
 
m2
n2
1 + 
 2
 2
=
1 +
e ni 2 =
e n1 2 
g
e
e n1 2
m1
 
 
n1
where
2I D K N W 1
= 469µS, g m2 =
g m1 =
L 1

m2

2

g

m1

g

8kT

3g m2

8kT

3g m1

=

e n1 2 2I D K P W 2
L 2

= 316µS,

and

e n1 2 =

8kT

3g m1

= 8·1.38x10 -23 ·300 3·469x10 -6

= 2.354x10 -17 V 2 /Hz

1 +

m2

g

m1

g

e ni 2 = 2.354x10 -17 ·1.6738 = 3.94x10 -17 V 2 /Hz e ni = 6.277nV/ Hz

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-9

Problem 5.1-11 Six inverters are shown. Assume that K N ' = 2K P ' and that λ N = λ P , and that the dc bias current through each inverter is equal. Qualitatively select, without using extensive calculations, which inverter(s) has/have (a.) the largest ac small signal voltage gain, (b.) the lowest ac small signal voltage gain, (c.) the highest ac output resistance, and (d.) the lowest ac output resistance. Assume all devices are in saturation. V DD
M2
v IN
v IN
v IN
M2
M2
M2
M2
v
v OUT
v OUT
v OUT
v OUT
M2
v OUT
OUT
V BP
v
M1
v IN
IN
M1
M1
M1
M1
v IN
V BN
M1
Circuit 1
Circuit 2
Circuit 3
Circuit 4
Circuit 5
Circuit 6

Figure P5.1-11 Solution
Circuit 1
Circuit 2
Circuit 3
Circuit 4
Circuit 5
Circuit 6
g m
g mN = 2 g mP
g mP
g mN = 2 g mP
g mP
g mN = 2 g mP
g mP
1
1 1
1
1
1
g
g
R out
mN +g mbN
mP +g mbP
g mP
g mN
g dsN +g dsP
g dsN +g dsP
0.707
≈ 0.707
=
=
=
g
1
1
mP +g mbP
g mP
g dsP (1+ 2)
g dsP (1+ 2)
1 2 g mP
|Gain|
g mP
g mP
g mP
2
g mP +g mbP
g mP +g mbP
2 g dsP (1+ 2)
g dsP (1+ 2)

(a.) Circuit 5 has the highest gain. (b.) Circuit 4 has the lowest gain (assuming normal values of g m /g mb ). (c.) Circuits 5 and 6 have the highest output resistance. (d.) Circuit 1 has the lowest output resistance.

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-10

Problem 5.1-12

Derive the expression given in Eq. (5.1-29) for the CMOS push-pull inverter of Fig. 5.1-8. If C gd1 = C gd2 = 5fF, C bd1

= C bd2 = 50fF, C L = 10 pF, and I D = 200 µA, find the

small-signal voltage gain and the 3 dB frequency if W 1 /L 1

= W 2 /L 2 = 5 of the CMOS push-pull inverter of Fig. 5.1-8.

Solution

The effective transconductance can be given by

g

m,eff

=+

gg

m

1

m

2

=  W 
'
2
IK
D
N
L
1

+  W 
'
K
P
L
2

The output conductance can be given by g
= (
g
+
g
)(
=
I
λ
+ λ
)
out
ds
1
ds
2
D
1
2
Thus, the small-signal gain becomes
g
m eff
,
A
=
v
g
out
 W 
 W 
'
'
K
K
N
+ 
P
2
L
L
1
2
A
= −
v
I
(
λ
+ λ
)
D
1
2
For
I
D = 200
µA
A
=
−43.63
= -43.63 V/V
v

The total capacitance at the output node is

C

total

= (

CC

gd

++++

1212

gd

bd

bd

C

C

C

L

)

Thus, the –3 dB frequency is

f

3 dB

=

g out

2π

C total

= 283.36 kHz.

= 10.11 pF. 5V
W
= 2µm
2
L
1µm
2
I
D
M2
+
+
M1
v
OUT
v
IN
1µm
W
1
=
L
1µm
1
-
-

Fig.P 5.1-12 Eq. (5.1-29)

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-11

Problem 5.1-13

For the active-resistor load inverter, the current-source load inverter, and the push-pull inverter compare the active channel area assuming the length is 1µm if the gain is to be 1000 at a current of I D = 0.1 µA and the PMOS transistor has a W/L of 1. M2
M2
M2
V
I
GG2
I
I
D
D
v
D
v
v
OUT
OUT
IN
v
OUT
v
v
IN
IN
M1
M1
M1
Active
Current
Push-
pull
Inverter
Inverter
Inverter

V DD

Figure 5.1-1 Various types of inverting CMOS amplifiers.

Soluton

Given,

I

D

=

10

µA , and

A

v

= −100

V/V

A

v

≅ −

g

m 1

g

m

2

100

= (
W L
K N
) 1
K
P (1)

W 1

L

1

Active area = 4546·1 + 5·1 = 4551 µm 2

A

v

=

g m 1

(

g

ds

1

+

g

ds

2

)

100

= 2 K
W L
N ’ (
) 1
I
D (
+ λ
) 2
λ 1
2

Active area = 3.64·1 + 5·1 = 8.64 µm 2

= 4546

c) Push-pull inverter

A

v

=

(

g

m

1

+

g

m

2

)

(

g

ds

1

+

g

ds

2

)

100

=

 2 K ’ N ( W L ) 1 + 2 K ’ P () 1/1 I D ( λ 1 + λ 2 ) 2

Active area = 1.55·1 + 5·1 = 4.55 µm 2

W 1

L

1

= 3.64

W L 1 1

= 1.55

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-12

Problem 5.1-14 For the CMOS push-pull inverter shown, find the small signal voltage gain, A v , the output resistance, R out , and the -3dB frequency, f -3dB if I D = 200µA, W 1 /L 1 = W 2 /L 2 = 5, C gd1 = C gd2 = 5fF, C bd1 = C bd2 = 30fF, and C L = 10pF. Solution

The small-signal model for this problem is shown below.

v IN C M
i out
+
+
g
r
v
v in
m1 v in
r ds1
g m2 v in
ds2
out
C
out
-
-

Fig. S5.1-14 V DD
M2
v OUT
M1
V SS
Fig. P5.1-14

Summing the currents at the output (ignoring the capacitors) gives,

g m1 v in + g ds1 v out + g m2 v in + g ds2 v out = 0

Solving for the voltage gain gives, 2
W 1 I D K N +
2 W 2
L
L 2 I D K P
v out
1
= -
v in
g m1 + g m2
g ds1 + g ds2 = -
I D (λ N +λ P )
v out
2
5·110x10 -6 +
5·50x10 -6
= A v = -
0.05 + 0.04
v in
200x10 -6

A v = - 43.63V/V

= - W 1
W 2
K N +
2
L 1
L 2 K P
I D
λ N +λ P

= - (100)(0.436) = - 43.63V/V

The output resistance is found by setting v in = 0 and solving for v out /i out .

R out is simply expressed as,

R out =

1

g ds1 + g ds2 =

R out = 55.55k

1

1

I D (λ N + λ P ) = 200x10 -6 (0.05+0.04) = 55.55k

From Eq. (5.1-26) we can solve for the –3dB frequency as

ω -3dB = ω 1 =

g ds1 + g ds2

C gd1 + C gd2 + C bd1 + C bd2 + C L

1

= R out (C gd1 + C gd2 + C bd1 + C bd2 + C L )

1

1

·10x10 -12 = 1.8x10 6 rad/s

= 55.55x10 -3 ( 5fF + 5fF + 30fF + 30fF + 10pF ) 55.55x10 3

ω -3dB = 1.8x10 6 rad/s

f -3dB = 286.5 kHz

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-13

Problem 5.2-01

Use the parameters of Table 3.1-2 to calculate the small-signal, differential-in, differential-out transconductance g md and voltage gain A v for the n-channel input,

differential amplifier when I SS = 100 µA and W 1 /L 1 = W 2 /L 2 = W 3 /L 3 = W 4 /L 4 = 1

assuming that all channel lengths are equal and have a value of 1µm. Repeat if W 1 /L 1 =

W 2 /L 2 = 10W 3 /L 3 = 10W 4 /L 4 = 10.

Solution

Referring to Fig. 5.2-5 and given that

a)

W

L

W

W

=

W

1

L

L

L

=

=

234

= 1

Differential-in differential-out transconductance is given by

g

md

===

1

m

2

gg

m  W 
'
K
I
N
SS
L
1

= 104.8 µS

Small-signal voltage gain is given by

b)

A

v

=

g

m

2

2 g

m 2

) =

(

g

ds

2

+

g

ds

4

I

SS

(

λ

2

+

λ

4

)

= 23.31 V/V

W

L

=

W

W

L

W

L

1

L

= 10

=

10

234

g

md

=

gg

m

1

=

m

2 = 331.4 µS

A

v

=

g

m 2

(

g

ds

2

+

g

ds

4

)

= 36.82 V/V

=

10

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-14

Problem 5.2-02

Repeat the previous problem for the p-channel input, differential amplifier.

Solution

Referring to Fig. 5.2-7 and given that

(a.)

W

L

=

W

=

W

=

W

1

L

L

L

234

= 1

Differential-in differential-out transconductance is given by

g

md

===

1

m

2

gg

m  W 
'
K
I
P
SS
L
1

= 70.71 µS

Small-signal voltage gain is given by

(b.)

A

v

=

g

m

2

2 g

m 2

) =

(

g

ds

2

+

g

ds

4

I

SS

(

λ

2

+

λ

4

)

= 15.7 V/V

W

g

=

=

W

W

L

W

L

L

1

md

L

= 10

=

10

234

m

2 = 223.6 µS

gg

m

1

=

=

10

A

v

=

g

m 2

(

g

ds

2

+

g

ds

4

)

=

24.84 V/V

Problem 5.2-03

Develop the expressions for V IC (max) and V IC (min) for the p-channel input differential amplifier of Fig. 5.2-7.

Solution

The maximum input common-mode input is given by

or,

V IC

(max) =

V

DD (
V
T 1

+

V

dsat

1

+

V

dsat

5

)

V

IC (max) =−
VV
DD
T 1

+ I DD
'
K
(
WL
)
P
1

+ 2 I
DD
'
K
(
WL
)
P
5

The minimum input common-mode input is given by

or,

V

IC

(min) =

V

SS + V

T

V

IC T 1

(min) =−++

VVV

SS

T 3 +
V
3
dsat
3
I DD
'
K
(
WL
)
N
3

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-15

Problem 5.2-04

Find the maximum input common mode voltage, v IC (max) and the minimum input common mode voltage, v IC (min) of the n-channel input, differential amplifier of Fig. 5.2- 5. Assume all transistors have a W/L of 10µm/1µm, are in saturation and I SS = 10µA. What is the input common mode voltage range for this amplifier?

Solution

The maximum input common-mode input is given by

or,

V IC

(max)

= V

DD

+V

T

1

V

T

V

IC

(max) =

V

DD

VV

+−

T

1

T

3 −V
3
dsat
3
I SS
K
' (
WL
)
P
3

= 4.86 V

The minimum input common-mode input is given by

or,

V IC

(min)

= V

SS

+V

T

1

V

IC

(min) =++

VV

SS

T 1 +V
+V
dsat
1
dsat
5
2 I
I SS
SS
+
'
(
)
'
K WL
K
(
WL
)
N
N
1
5

= 0.93 V

So, the input common-mode range becomes

ICMR

=

V

IC

(max)

V

IC

(min)= 3.93 V

Problem 5.2-05

Find the small signal voltage gain, v o /v i , of the circuit in the previous problem if v in = v 1 - v 2 . If a 10pF capacitor is connected to the output to ground, what is the -3dB frequency

for V io (jω)/V IN (jω) in Hertz? (Neglect any device capacitance.)

Solution

Small-signal voltage gain is given by

A

v

g

m 2

2 g

m 2

= (

g

ds

2

+

g

ds

4

I

SS

(

λ

2

+

λ

4

)

) =

= 233.1 V/V

The –3 dB frequency is given by

f 3 dB

(

g

ds

2

+

g

ds

4

)

I

SS

(

λ

λ

+

24

)

=

2π

C

L

4

C

π

L

= 7.16 kHz.

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-16

Problem 5.2-06

For the CMOS differential amplifier of Fig. 5.2-5, find the small signal voltage gain, v out /v in , and the output resistance, R out , if I SS = 10µA, V DD = 2.5V and v in = v gs1 -v gs2 . If the gates of M1 and M2 are connected together, find the minimum and maximum common mode input voltage if all transistors must remain in saturation (ignore bulk effects). Solution

Small-signal model for calculations: i
out
+ v in
-
+
+
+
i
3
v gs1
v gs2
gm1 v gs1
v
1
out
i
3
rds2
rds4
-
-
rds1
rds3
gm3
gm2 v gs2
-
Fig. S5.2-06
1
1
R out =
(0.04 + 0.05)5µA = 2.22 MΩ
g ds2 + g ds4 =
g
m1 g m3 r p1
v out = 
v gs1 − g m2 v gs2 R out ≈ (g m1 v gs1 – g m2 v gs2 )R out = g m1 R out v in
1 + g m3 r p1
v out
v in
2·110·5·2) µS = 46.9 µS
= g m1 R out = g m2 R out ,
g m1 = g m2 =

v out

v in

= 46.9µS·2.22M= 104.1 V/V

Common mode input range: 2·5
V icm (max) = V DD – V SG3 + V TN = 2.5 - 
+ 0.7 = 2.5 - 0.3162 = 2.184 V
50·2 +0.7
2·10
2·5
V icm (min) = 0+V DS5 (sat)+V GS1 =
= 0.3015+0.9132
110·2 
110·2 +0.7

= 1.2147 V

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-17

Problem 5.2-07

Find the value of the unloaded differential-transconductance gain, g md , and the unloaded differential-voltage gain, A v , for the p-channel input differential amplifier of Fig. 5.2-7

when I SS = 10 microamperes and I SS = 1 microampere. Use the transistor parameters of Table 3.1-2.

Solution Assuming all transistors have W/L = 1

a)

b)

Given,

I

SS

=

10

µA

g

md

= = 22.36 µS

Given,

I

SS

=

1

µA

g

md

= = 7.07 µS

A

A

v

v

g

md

2 g

md

 = g ds 2 + g ds 4 ) I SS ( λ λ + 24 ) g md 2 g md g ds 2 + g ds 4 ) = I SS ( λ λ + 24 )

= (

= (

= 49.69 V/V

= 157.11 V/V

Problem 5.2-08

What is the slew rate of the differential amplifier in the previous problem if a 100 pF capacitor is attached to the output?

Solution

Slew rate can be given as

For

For

SR =

I

SS

=

10

SR =

I

SS

=

1

SR =

I SS

C

L

µA and

C

L

= 100

pF

I

SS

C

L

=

0.1 V/µs

µA and

C

L

= 100

pF

I

SS

C

L

=

0.01 V/µs

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-18

Problem 5.2-09

Assume that the current mirror of Fig. 5.2-5 has an output current that is 5% larger than the input current. Find the small signal common-mode voltage gain assuming that I SS is 100µA and the W/L ratios are 2µm/1µm for M1, M2 and M5 and 1µm/1µm for M3 and

M4.

Solution

Given that

I

D 4

=

(1.05)

I

D

3

or,

I

D

2

=

(1.05)

I

D

1

This mismatch in currents in the differential input pair will result in an input offset voltage.

Now,

So,

I

D

1

+ I

D

2

= I

SS

I

D

1

(0.49)I

SS

and

I

D

2

(0.51)I

SS

To calculate the common-mode voltage gain, let us assume a small signal voltage

v

s applied to both the gates of the differential input pair.

The small-signal output current

i out

is given by i
=
(
i
− i
)
out
D4
D2
where,
0
.
5 g
ds 5
i
≅  
g
 v
D 4
m
s
g
4 
m 3
i
(
0.5
g
)
v
D
2
ds
5
s
So,
 g
i
= (
ii
)
= (
05. g
)
m
4
1  v
out
D
42
D
ds
5
s
 g
m
3
The output conductance can be given as
≅ g
as
M
and
M
5 form a cascode structure.
g out
ds4
2
Thus,
g
 g
i out
ds 5
4
=≅
m
− 1  v
v out
s
2 g
 g
g out
ds 4
m
3
v
 g
out
g ds 5
4
=
m
or,
− 1 
v
2 g
 g
s
ds 4
m
3
v
I
(
λ
)
I
out
SS
5
D
4
or,
=
− 1 
v
I
(
λ
)
I
s
SS
4
D
3
v
out
or,
= 0.02 V/V
v
s

Thus, the small-signal common-mode gain is approximately 0.02 V/V

CMOS Analog Circuit Design (2 nd Ed.) – Homework Solutions

Page 5-19

Problem 5.2-10

Use the parameters of Table 3.1-2 to calculate the differential-in-to-single-ended-output voltage gain of Fig. 5.2-9. Assume that I SS is 50 microamperes.

Solution Let, the aspect ratio of all the transistors be 1.

The small-signal differential-in single-ended out voltage gain is given by (
W
'
L )
g