Computer Science 141 Computing Hardware C i d

Fall 2008 Harvard University Instructor: Prof. David Brooks dbrooks@eecs.harvard.edu

Computer Science 141 David Brooks

Next couple of weeks

Next three lectures on FSM Design Next two labs on sequential design/FSMs Take-home midterm will be handed out Wednesday 11/5 (after class) due Friday 11/7 at 5pm
NO Lab the week of 11/3

Review Session
Monday 11/3?

Computer Science 141 David Brooks

Finite State Machine (FSM)

Consists of:
State register that g
Store the current state and Load the next state at the clock edge
S Next State S Current State CLK

Combinational logic that

C Computes the next state h Computes the outputs

Next State Logic

C L
Output Logic

Next State

C L
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Outputs

Moore vs. Mealy machines

block diagrams
C L
state inputs i t

C L

outputs

clock Moore machine

inputs st tate

outputs

C L

clock Mealy machine

Computer Science 141 David Brooks

Moore Machine
Inputs Excitation Current State Outputs p

Clock input p

Clock

clock inputs state outputs Moore machine timing

Computer Science 141 David Brooks

Mealy Machine
Inputs Excitation Current State Outputs

Clock input

Clock

clock inputs state outputs

Mealy machine timing
Computer Science 141 David Brooks

Moore vs. Mealy machines

timing of input, state, and output changes

clock inputs state outputs t t Moore machine timing Mealy machine timing

Computer Science 141 David Brooks

Mealy vs. Moore: Design Example

function: assert output if 2 or more 1s in a row state diagram:
reset 0 [0] 1 0 1 2 [1] 1 Moore machine Mealy machine 1 [0] 0 1/0 1 1/1 0 reset 0 0/0 0/0

advantages/disadvantages
Mealy often has fewer states than Moore machine since it associates outputs with transitions Mealy machine can fall victim to glitches since outputs are asynchronous
Computer Science 141 David Brooks

Moore vs. Mealy FSM

Alyssa P. Hacker has a snail that crawls down a paper tape with 1s and 0s on it. The snail smiles whenever the last four digits it has crawled over are 1101. Design Moore and Mealy FSMs of the snails brain.

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State Transition Diagrams

Moore FSM
reset S0 0 0 0 1 S1 0 1 1 S2 0 0 0 S3 0 0 1 1 S4 1

Mealy FSM: arcs indicate input/output

Mealy FSM
reset 1/1 1/0 S1 0/0 0/0 1/0 1/0 S2 0/0 0/0 S3

S0

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Moore FSM State Transition Table

Current State Inputs Next State
S2
0 0 0 0 0 0 0 0 1 1

S1
0 0 0 0 1 1 1 1 0 0

S0
0 0 1 1 0 0 1 1 0 0

A
0 1 0 1 0 1 0 1 0 1

S S'2

S S'1

S S'0

State S0 S1 S2 S3 S4

Encoding 000 001 010 011 100

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Moore FSM State Transition Table

Current State Inputs Next State
S2
0 0 0 0 0 0 0 0 1 1

S1
0 0 0 0 1 1 1 1 0 0

S0
0 0 1 1 0 0 1 1 0 0

A
0 1 0 1 0 1 0 1 0 1

S S'2
0 0 0 0 0 0 0 1 0 0

S S'1
0 0 0 1 1 1 0 0 0 1

S S'0
0 1 0 0 1 0 0 0 0 0

State S0 S1 S2 S3 S4

Encoding 000 001 010 011 100

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Moore FSM Output Table

Current State S2 0 0 0 0 1 S1 0 0 1 1 0 S0 0 1 0 1 0

Output Y

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Moore FSM Output Table

Current State S2 0 0 0 0 1 S1 0 0 1 1 0 S0 0 1 0 1 0

Output Y 0 0 0 0 1

Y = S2

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Mealy FSM State Transition and Output Table

Current State S1
0 0 0 0 1 1 1 1

Input p A
0 1 0 1 0 1 0 1

Next State S'1 S'0

Output p Y

S0
0 0 1 1 0 0 1 1

State S0 S1 S2 S3

Encoding 00 01 10 11

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Mealy FSM State Transition and Output Table

Current State S1
0 0 0 0 1 1 1 1

Input p A
0 1 0 1 0 1 0 1

Next State S'1

0 0 0 1 1 1 0 0

Output p Y
0 0 0 0 0 0 0 1

S0
0 0 1 1 0 0 1 1

S'0
0 1 0 0 1 0 0 1

State S0 S1 S2 S3

Encoding 00 01 10 11

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Moore FSM Schematic

A S'2 CLK S2 Y

S S'1

S1

S'0

S0 Reset

S2
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S1

S0

Mealy FSM Schematic

A CLK S'1 S1 Y

S'0

S0 Reset

S1

S0

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Moore and Mealy Timing Diagram

Cycle 1 y CLK Reset A S Y ?? S0 1 S1 1 S2 1 S2 0 S3 1 S4 1 S2 0 S3 1 S4 0 S0 Cycle 2 y Cycle 3 y Cycle 4 y Cycle 5 y Cycle 6 y Cycle 7 y Cycle 8 y Cycle 9 Cycle 10 y y

Moore Machine

Mealy Machine
S Y ?? S0 S1 S2 S2 S3 S1 S2 S3 S1 S0

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Timing
Flip-flop samples D at clock edge D must be stable when it is sampled Similar to a photograph, D must be stable around the clock edge If D is changing when it is sampled, metastability can occur

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Input Timing Constraints

Setup time: tsetup = time before the clock edge that data must be stable (i.e. not changing) ( g g) Hold time: thold = time after the clock edge that data must be stable Aperture time: ta = time around clock edge that data must be stable (ta = tsetup + thold)
CLK

D tsetup thold ta
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Output Timing Constraints

Propagation delay: tpcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing) g ( , p g g) Contamination delay: tccq = time after clock edge that Q might be unstable (i.e., start changing)
CLK Q tccq tpcq

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Dynamic Discipline
The input to a synchronous sequential circuit must be stable during the aperture ( g p (setup and hold) time around the clock p ) edge. Specifically, the input must be stable
at l least tsetup b f before the clock edge h l k d at least until thold after the clock edge

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Dynamic Discipline
The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit y, p y elements
CLK Q1 ( ) (a) CLK Q1 D2 (b)
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CLK C L D2 R2 Tc

R1

Setup Time Constraint

The setup time constraint depends on the maximum delay from register R1 through the combinational logic. The input to register R2 must be stable at least tsetup before the clock edge.
CLK Q1 R1 Tc CLK Q1 D2 tpcq p q
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CLK C L D2 R2

Tc

tpd p

tsetup p

Setup Time Constraint

The setup time constraint depends on the maximum delay from register R1 through the combinational logic. The input to register R2 must be stable at least tsetup before the clock edge.
CLK Q1 R1 Tc CLK Q1 D2 tpcq p q
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CLK C L D2 R2

Tc tpcq + tpd + tsetup tpd

tpd p

tsetup p

Setup Time Constraint

The setup time constraint depends on the maximum delay from register R1 through the combinational logic. The input to register R2 must be stable at least tsetup before the clock edge.
CLK Q1 R1 Tc CLK Q1 D2 tpcq p q
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CLK C L D2 R2

Tc tpcq + tpd + tsetup tpd Tc (tpcq + tsetup)

tpd p

tsetup p

Hold Time Constraint

The hold time constraint depends on the minimum delay from register R1 through the combinational logic. The input to register R2 must be stable for at least thold after the clock edge.
CLK Q1 R1 CLK Q1 D2 tccq tcd thold
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CLK C L D2 R2

thold <

Hold Time Constraint

The hold time constraint depends on the minimum delay from register R1 through the combinational logic. The input to register R2 must be stable for at least thold after the clock edge.
CLK Q1 R1 CLK Q1 D2 tccq tcd thold
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CLK C L D2 R2

thold < tccq +tcd tcd >

Hold Time Constraint

The hold time constraint depends on the minimum delay from register R1 through the combinational logic. The input to register R2 must be stable for at least thold after the clock edge.
CLK Q1 R1 CLK Q1 D2 tccq tcd thold
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CLK C L D2 R2

thold < tccq + tcd tcd > thold - tccq

Timing Analysis
CLK A B X X' Y' X Y CLK

Timing Characteristics
tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps
per gate

C D

tpd = 35 ps p tcd = 25 ps

tpd = tcd = Setup time constraint: Tc fc = 1/Tc =

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Hold time constraint: tccq + tpd > thold ?

Timing Analysis
CLK A B X X' Y' X Y CLK

Timing Characteristics
tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps
per gate

C D

tpd = 35 ps p tcd = 25 ps

tpd = 3 x 35 ps = 105 ps tcd = 25 ps p Setup time constraint: Tc (50 + 105 + 60) ps = 215 ps fc = 1/Tc = 4 65 GHz 4.65 GH
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Hold time constraint: tccq + tpd > thold ? (30 + 25) ps > 70 ps ? N ! No!

Fixing Hold Time Violation

Add buffers to the short paths:
CLK A B C D X' Y' X Y CLK

Timing Characteristics
tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps
per gate

tpd = 35 ps p tcd = 25 ps

tpd = tcd = Setup time constraint: Tc fc =

Copyright 2007 Elsevier

Hold time constraint: tccq + tpd > thold ?

Fixing Hold Time Violation

Add buffers to the short paths:
CLK A B C D X' Y' X Y CLK

Timing Characteristics
tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps
per gate

tpd = 35 ps p tcd = 25 ps

tpd = 3 x 35 ps = 105 ps tcd = 2 x 25 ps = 50 p p ps Setup time constraint: Tc (50 + 105 + 60) ps = 215 ps fc = 1/Tc = 4 65 GHz 4.65 GH
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Hold time constraint: tccq + tpd > thold ? (30 + 50) ps > 70 ps ? Y ! Yes!