Built-In Self-Test (BIST) and Built-In Self-Repair (BISR) techniques in syncronous memory devices

Alberto Rui Frutuoso Barroso

Integrated Master in Electrical and Computers Engineering Faculdade de Engenharia da Universidade do Porto Porto, Portugal Email: http://www.fe.up.pt/ee07094

AbstractThe use of a symmetrical BIST system in prefetched memory architectures, associated with BISR adaptative eld programmable redundancy mechanisms, can increase the production yield at wafer level, transfer auto-test operations to the exterior of the microprocessor, and will allow to auto-repair or replace memory cells during the normal operation on the end product.

I. I NTRODUCTION The current CMOS manufacturing processes using sub 100nm resolutions allows the development of Multi-Gigabit discrete memory devices, and to integrate several megabits of memory in microprocessors and in application specic integrated circuits (ASIC). Due to the fact that the number of dies without defects present in the wafer diminish with the increase of the number of storage cells [1], BISR and BIST mechanisms must be implemented in RAM products to rescue dies from wafers that have a yield of zero (all dies are defective before wafer level repair operations). Integrated in standard JEDEC RAM devices [2], the BIST and BISR mechanisms proposed in this paper will introduce a new production ow for devices that are partially tested during the front-end and back-end manufacturing operations. This new production ow will be added to the current low power, industrial/military temperature and high speed test ows, recovering RAM devices that my be used as main memory in embedded systems with parallel processing architectures in price competitive consumer, communications and computers (CCC) products. This new type of RAM (with mirror BIST) can be used in mechatronic equipment used in harsh and remote environments, allowing to soft repair failing memory locations in the power on self-test (POST), and as a background task during normal operation. ARFB July, 2008 II. M IRROR BIST A. Description The mirror BIST mechanism developed in this work was projected to be integrated in multiple banks prefetched memory devices, with the addition of soft repair capabilities to the conventional hard repair (laser fusing or electrical anti-fuses) redundant memory elements. Using a remapping scheme to store a n bit wide failing address in a typical m bits wide data bus (m<n), the fail addresses caught during the BIST

operation will be stored in a pre-tested area of the closest block in the device. This mirror BIST feature will be placed in the spine zone of the memory device, integrated with the I/O gating of the near block maintaining the signal integrity in bus lines with transfer velocities greater than 100 Mbps. The use of this symmetrical BIST mechanism (mirror of fails) in devices with four or more banks, allows the self test of a bank using the pretested area in the opposite bank to store the addresses of the failing memory positions, with the tested banks in the device available to be used by the microprocessor in normal work operations. When used in discrete DRAM or SRAM devices, this BIST will be initialized and started using internal test mode registers. Accessing this internal registers, we can dene a maximum fail count limit, read the number of fails caught in the tested bank, choose de bank under test (BUT) and interrupt the BIST operation. The maximum fail count limit is dened by the size of the pretested (and repaired) memory area, and will be used to stop one iteration in a recursive mirror BIST operation. The mirror BIST with recursive operations is designed to speed up the boot time in embedded systems, and to reduce the initial pre-tested area in the new CMOS technologies with a high number of single cell fails (SCF). To speed up the boot time we may reduce the pretested area in size, reducing the POST time of the microprocessor, in devices with high bit fail ratios this area will be dened to avoid pre-testing large areas using an external microprocessor. After the boot, the mirror BIST operation will interleave the test sequence (A tests B then B tests A) with the respective replacement or repair of the failing addresses. The BISR after a BIST step can be executed by the external microprocessor, or integrating a microcoded BISR unit with the mirror BIST. In embedded systems used in fault tolerant equipments, the microprocessor unit will boot from a redundant ROM/RAM conguration, and must execute a normal test (using a BISR scheme to repair or replace fail addresses) in the areas needed by the operating system to start the standard operation services, and test the areas to the be used in the initial BIST operations. The use of this BIST (combined with a eld programmable BISR) can skip some steps in the conventional hard repair techniques, reducing the test time in the front-end operations (wafer testing) and in the back-end test operations (in burn-in and nal test).

B. Implementation To evaluate the area used in the die to implement the mirror BIST mechanism, a Xilinx Spartan-3 (X3S400) FPGA was used to sinthetize a reference datapath and the datapath with mirror BIST. The reference datapath is similar to the datapath used in DDR devices: minimal control pins, multiplexing of the address lines, and burst operations counter. In a DDR device this datapath is normally located between the output of the sense ampliers, and the DDR FIFO and output registers. The datapath with Mirror-BIST have the same structure as the reference datapath, with the additional inclusion of bus multiplexers and BIST control logic. Both datapath implementations where done in Verilog, and sinthetized and tested in the developed FPGA system.
Software Xilinx XST ISE Synopsys Design Compiler Synopsys Design Compiler Cadence SOC Encounter

TABLE I M IRROR BIST DIE OVERHEAD

Units equivalent gate count total cell area total area area No BIST 570 22422 25644 0,0233 Mirror BIST 1622 37291 44086 0,0385 Overhead(%) 184 66 72 65

dielectric). There are physical restrictions that limit the maximum number of fuses and anti-fuses, and both suffer some reliability issues after been used. The proposed soft-BISR (integrated with the mirror BIST) gives maximum exibility to the self repair mechanism present in all DRAM/SRAM discrete devices[3]. The granularity of this soft-BISR will be dened after some statistical evaluation of the number of SCF present in the cell matrix, for a particular process-technology. The repair registers will be accessed via test modes, with a maximum number limited by die overhead issues and address location access delay. B. Adaptative refresh BISR This BISR solution uses programmable refresh controllers (PRC) distributed in the memory array, this solution was designed to be used in pseudo static RAM (PSRAM), and in the self refresh circuit of DRAM devices. In a PSRAM device, the PRC can be integrated in the partial array refresh (PAR) circuit and replace the temperature self refresh controller (TCSR) used in the standby mode. The core component of the PRC is a time measurement unit (TMU), designed to measure the retention time of the cells failing to operate at nominal temperature and refresh times. This TMU was implemented in the FPGA system, using a 16 positions state machine. IV. C ONCLUSION The feasibility of integrating a basic mirror BIST mechanism in memory devices, with a die overhead in the spine zone less than 72%, became proved using the synthesis results of a typical DDR data path as a reference, and implementing a state machine mirror BIST solution in this data path. Using this BIST and BISR mechanisms we can rescue devices with single cell fails that are tormenting the yield of the DRAM industry, and extend the operational life of degraded memory devices in end products. ACKNOWLEDGMENT I am extremely grateful to Professor Jo o Canas Ferreira a for his constant support, and to Herr Christian Seibert for the huge interest in this work. R EFERENCES
[1] A. Miczo, Digital Logic Testing and Simulation, 2nd ed. Wiley, 2003. [2] JEDEC, Joint electron device engineering council, July 2008, http:// www.jedec.org/. [3] R. Adams, High Performance Memory Testing, 1st ed. Kluwer Academic Publishers, 2002.

Fig. 1.

Mirror BIST: state machine

A bare bones version of the mirror BIST was implemented using a symmetrical state machine (gure1), with the objective to obtain a solution with a minimal die overhead. This value will be used as a base reference for comparison with more complete (with checkerboard and stripes test topology generation) microcode implementations of the mirror BIST. The area occupied by the storage cells was not included in the calculation of the die overhead, because this is a mixed signal area using distinct cell topologies (8F2, 6F2, 4F2) with different types of sense ampliers (folded, open, hybrid). The die overhead was calculated using the area taken in the placement of logic cells in the exterior of the matrix of storage cells (the spine of the die), comparing the area needed to implement a normal data path and a data path with the mirror BIST. The Verilog HDL used to design this two data paths, was synthesized in the FPGA using the Xilinx XST, and physically (AMS 0.35 m) using the Synopsis Design Compiler, and the Cadence SOC encounter. The BIST data path synthesis reached operating frequencies equivalent to the reference data path; a summary of the synthesis results is presented in the table I. III. S OFT AND ADAPTATIVE REFRESH BISR A. Soft BISR The main reason for the lack of adequate granularity to repair single cell fails in RAM devices is the use of a short number of fuses (laser cut) or anti-fuses (electrically disrupted