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Fifth Workshop on Intelligent Solutions in Embedded Systems “WISES 07”, June 21-22, Madrid

in Embedded Systems “WISES 07”, June 21-22, Madrid A A Low Low - - Cost Cost

AA LowLow--CostCost FPGAFPGA--basedbased EmbeddedEmbedded FingerprintFingerprint VerificationVerification andand MatchingMatching SystemSystem

Verification and and Matching Matching System System Maitane Barrenechea Jon Altuna Miguel San Miguel Signal

Maitane Barrenechea

Jon Altuna

Miguel San Miguel

Signal Theory and Communications Group Department of Electronics University of Mondragon

Index

Introduction Software Architecture Hardware Architecture Conclusions

Architecture Hardware Architecture Conclusions A Low-Cost FPGA-based Embedded Finger print Verification and

Index

Introduction Software Architecture Hardware Architecture Conclusions

Architecture Hardware Architecture Conclusions A Low-Cost FPGA-based Embedded Finger print Verification and

Introduction

Biometrics

Introduction Biometrics Uses some unique behavioural or physiological characteristics to identify a person.

Uses some unique behavioural or physiological characteristics to identify a person. Behavioural characteristics:

to identify a person. Behavioural characteristics: Signature Gait Typing pattern Physiological
to identify a person. Behavioural characteristics: Signature Gait Typing pattern Physiological

Signature Gait Typing pattern Physiological characteristics:

Fingerprints Facial Patterns Hand Measurements Eye Retinas

Introduction

System Overview

Introduction System Overview Software Based on the packages from the National Institute of Standard and Technology’s

Software

Based on the packages from the National Institute of Standard and Technology’s (NIST) Fingerprint Image Software (NFIS2) .

Template minutiae set

Fingerprint Image Software (NFIS2) . Template minutiae set MINDTCT Fingerprint’s minutiae set BOZORTH3 Match Score

MINDTCT

Image Software (NFIS2) . Template minutiae set MINDTCT Fingerprint’s minutiae set BOZORTH3 Match Score Hardware

Fingerprint’s minutiae set

BOZORTH3
BOZORTH3
minutiae set MINDTCT Fingerprint’s minutiae set BOZORTH3 Match Score Hardware - Spartan3 family FPGA - Leon2

Match Score

Hardware

- Spartan3 family FPGA

- Leon2 32-bit Sparc Processor

- Floating Point Unit (FPU)

- Hardware co-processor

- Fujitsu MBF200 fingerprint sensor

Index

Introduction Software Architecture Hardware Architecture Conclusions

Architecture Hardware Architecture Conclusions A Low-Cost FPGA-based Embedded Finger print Verification and

SW Architecture

Software Implementation on a Leon2 Platform

SW Architecture Software Implementation on a Leon2 Platform Custom version of the MINDTCT and BOZORTH3 packages

Custom version of the MINDTCT and BOZORTH3 packages (NIST2). Only those modules required for XYT formatted minutiae output set generation have been used. Input fingerprint image format modified RAW Used fingerprint images fulfil the conditions set for an optimum performance 500 dpi 256 greyscale Bare-C Cross-Compiler GRMON debug monitor

SW Architecture

Minutiae Extraction Algorithm

SW Architecture Minutiae Extraction Algorithm Input Fingerprint RAW Image Image Maps Binarization Minutiae Detection
Input Fingerprint RAW Image
Input Fingerprint RAW Image
Image Maps
Image Maps
Binarization
Binarization
Minutiae Detection
Minutiae Detection
Remove False Minutiae
Remove False Minutiae
Assess Minutiae Quality
Assess Minutiae Quality
Output Minutiae in XYT Format
Output Minutiae in XYT Format
Low Contrast Map
Low Contrast Map
Direction Map
Direction Map
Low Flow Map
Low Flow Map
High Curve Map
High Curve Map
Quality Map
Quality Map

SW Architecture

Image Maps

SW Architecture Image Maps Low Contrast Map : Marks low contrast areas in the image. Direction

Low Contrast Map: Marks low contrast areas in the image.

Direction Map: Represents the main ridge flow direction.

Low Flow Map: Identifies image areas with a weak structure.

High Curve Map: Flags high

curvature areas in the image.

Quality Map: Assigns a quality level to each block in the image.

ridge

Assigns a quality level to each block in the image. ridge Poor quality Fair quality Good

Poor quality Fair quality Good quality Very good quality Excellent quality

SW Architecture

Binarization & Minutiae Extraction

SW Architecture Binarization & Minutiae Extraction Binarization A pixel is assigned a binary value based on

Binarization A pixel is assigned a binary value based on the ridge flow direction associated with the block the pixel is within.

Minutiae Extraction Identify certain pixel patterns Ridge Ending Bifurcation

certain pixel patterns Ridge Ending Bifurcation A Low-Cost FPGA-based Embedded Finger print Verification and
certain pixel patterns Ridge Ending Bifurcation A Low-Cost FPGA-based Embedded Finger print Verification and
certain pixel patterns Ridge Ending Bifurcation A Low-Cost FPGA-based Embedded Finger print Verification and

SW Architecture

False Minutiae Removal & Quality Assessment

Architecture False Minutiae Removal & Quality Assessment Remove False Minutiae Assess Minutia Quality Two factors are

Remove False Minutiae

Assess Minutia Quality

Two

factors

are

quality measure:

Quality Map Pixel Intensity Statistics

Poor quality Fair quality Good quality Very good quality Excellent quality

combined

to

produce

a

Very good quality Excellent quality combined to produce a A Low-Cost FPGA-based Embedded Finger print Verification

SW Architecture

Matching Algorithm

SW Architecture Matching Algorithm Bozorth3 Rotation and translation invariant Matching Score > 40 Finger Match

Bozorth3 Rotation and translation invariant Matching Score > 40

Finger Match

Template Minutiae Set Fingerprint Minutiae Set Construct Intra-Fingerprint Minutia Comparison Tables Construct
Template
Minutiae Set
Fingerprint
Minutiae Set
Construct Intra-Fingerprint
Minutia Comparison Tables
Construct Inter-Fingerprint
Compatibility Table
Traverse the Inter-Fingerprint
Compatibility Table
Matching Score

Index

Index Introduction Software Architecture Hardware Architecture Conclusions A Low-Cost FPGA-based Embedded Finger

Introduction Software Architecture Hardware Architecture Conclusions

APB BUS

HW Architecture

Initial System Architecture

APB BUS HW Architecture Initial System Architecture Initial system architecture LEON-2 soft-processor CACHE AHB I/F

Initial system architecture

LEON-2 soft-processor CACHE AHB I/F INTEGER UNIT DATA INSTR.
LEON-2 soft-processor
CACHE
AHB I/F
INTEGER UNIT
DATA
INSTR.
AHB CONTROLLER
AHB
CONTROLLER

GR-XC3S1500 board with the following embedded

modules:

Leon2 processor 50 MHz Cache system: 8 KB (data and instruction)

AHB BUS

AHB/APB BRIDGE
AHB/APB
BRIDGE
PC
PC

Fingerprint Capture IP Fujitsu MBF200 fingerprint sensor

MEMORY CONTROLLER
MEMORY
CONTROLLER
BOOT PROM I/F
BOOT PROM
I/F
SDRAM I/F
SDRAM I/F

BOOT

ROM

SDRAM

UART FINGERPRINT CAPTURE IP
UART
FINGERPRINT
CAPTURE IP
FINGERPRINT SENSOR
FINGERPRINT
SENSOR

GRXC-3S1500

HW Architecture

Initial System Architecture

HW Architecture Initial System Architecture Why Leon2? High configurability VHDL code availability (under LGPL

Why Leon2? High configurability VHDL code availability (under LGPL license). High performance Best performance per clock cycle High usability Tkconfig graphical configuration tool

HW Architecture

Running the application on the initial system

HW Architecture Running the application on the initial system The execution of the algorithm is successful

The execution of the algorithm is successful in terms of the matching results. Yet the execution time is excessive. MINDTCT occupies 75% of the computation time.

MINDTCT acceleration:

Mainly floating-point operations Leon2 is a fixed-point processor Leon2 compatible FPUs:

LTH Meiko

GRFPU

Leon2 compatible FPUs: LTH Meiko G R F P U IEEE-754 compliant FPU A Low-Cost FPGA-based

IEEE-754 compliant

FPUs: LTH Meiko G R F P U IEEE-754 compliant FPU A Low-Cost FPGA-based Embedded Finger

FPU

HW Architecture

FPU tests

HW Architecture FPU tests FPU insertion Reduce clock frequency Reduce cache sizes Three different system

FPU insertion

Reduce clock frequency Reduce cache sizes Three different system configurations under test 31 MHz and 8KB cache memory. 37 MHz and 8KB cache memory. 40 MHz and 4KB cache memory.

37 MHz and 8KB cache memory. 40 MHz and 4KB cache memory. Great increase in the

Great increase in the amount of logic

HW Architecture

FPU tests

Stanford benchmark

HW Architecture FPU tests Stanford benchmark Measures the execution time in ms for ten small programs.

Measures the execution time in ms for ten small programs.

 

A

 

BCD

 

Perm

34

50

33

34

Towers

50

83

67

50

Queens

33

50

33

33

Intmm

166

133

100

116

Mm

1000

84

50

67

Puzzle

317

450

350

350

Quick

50

50

33

33

Bubble

50

50

50

50

Tree

233

334

266

250

FFT

1067

83

67

50

A: 50 MHz / 8KB cache /No FPU. B: 31 MHz / 8KB cache / FPU. C: 37 MHz / 8KB cache / FPU. D: 40 MHz / 4KB cache / FPU.

91.6% - 95% execution time reductionC: 37 MHz / 8KB cache / FPU. D: 40 MHz / 4KB cache / FPU.

92.22% - 95.3% execution time reductionMHz / 4KB cache / FPU. 91.6% - 95% execution time reduction Paranoia benchmark Test the

Paranoia benchmark

Test the compliance with the IEEE-754 floating-point standard

HW Architecture

Introducing the GRFPU in the design

HW Architecture Introducing the GRFPU in the design LEON-2 soft-processor CACHE AHB I/F INTEGER UNIT DATA
LEON-2 soft-processor CACHE AHB I/F INTEGER UNIT DATA INSTR.
LEON-2 soft-processor
CACHE
AHB I/F
INTEGER UNIT
DATA
INSTR.
AHB CONTROLLER
AHB
CONTROLLER

FPU

AHB BUS AHB/APB BRIDGE MEMORY CONTROLLER UART BOOT PROM I/F BOOT ROM FINGERPRINT CAPTURE IP
AHB BUS
AHB/APB
BRIDGE
MEMORY
CONTROLLER
UART
BOOT PROM
I/F
BOOT
ROM
FINGERPRINT
CAPTURE IP
SDRAM I/F
SDRAM
APB BUS

GRXC-3S1500

PC
PC
FINGERPRINT SENSOR
FINGERPRINT
SENSOR

HW Architecture

Introducing the GRFPU in the design

HW Architecture Introducing the GRFPU in the design 94.14% execution time reduction (40MHz / 4KB cache).

94.14% execution time reduction (40MHz / 4KB cache). Program completion delay is yet excessive.

A: 50 MHz / 8KB cache /No FPU / No HW Co-processor. B: 31 MHz / 8KB cache / FPU / No HW Co-processor. C: 37 MHz / 8KB cache / FPU / No HW Co-processor. D: 40 MHz / 4KB cache / FPU / No HW Co-processor.

D: 40 MHz / 4KB cache / FPU / No HW Co-processor. A Low-Cost FPGA-based Embedded
D: 40 MHz / 4KB cache / FPU / No HW Co-processor. A Low-Cost FPGA-based Embedded

HW Architecture

HW speed enhancement MINDTCT completion time excessive

HW speed enhancement MINDTCT completion time excessive HW accelerator speeds up this process Mainly due to
HW speed enhancement MINDTCT completion time excessive HW accelerator speeds up this process Mainly due to

HW accelerator speeds up this process

time excessive HW accelerator speeds up this process Mainly due to DM. LCM : Low Contrast

Mainly due to DM.

LCM: Low Contrast Map. DM: Direction Map. LFM: Low Flow Map.

HW Architecture

HW speed enhancement

HW Architecture HW speed enhancement LEON-2 soft-processor CACHE AHB I/F INTEGER UNIT DATA INSTR. AHB CONTROLLER
LEON-2 soft-processor CACHE AHB I/F INTEGER UNIT DATA INSTR.
LEON-2 soft-processor
CACHE
AHB I/F
INTEGER UNIT
DATA
INSTR.
AHB CONTROLLER
AHB
CONTROLLER
FPU
FPU

HW co-processor

AHB BUS AHB/APB BRIDGE MEMORY CONTROLLER UART BOOT PROM I/F BOOT ROM FINGERPRINT CAPTURE IP
AHB BUS
AHB/APB
BRIDGE
MEMORY
CONTROLLER
UART
BOOT PROM
I/F
BOOT
ROM
FINGERPRINT
CAPTURE IP
SDRAM I/F
SDRAM
APB BUS

GRXC-3S1500

GRXC-3S1500

PC
PC
FINGERPRINT SENSOR
FINGERPRINT
SENSOR

HW Architecture

HW speed enhancement

HW Architecture HW speed enhancement execution time reduction is estimated (40MHz / 4KB cache). 97.89% A:

execution time

reduction is estimated (40MHz / 4KB cache).

97.89%

A: 50 MHz / 8KB cache /No FPU / No HW Co-processor. B: 31 MHz / 8KB cache / FPU / No HW Co-processor. C: 37 MHz / 8KB cache / FPU / No HW Co-processor. D: 40 MHz / 4KB cache / FPU / No HW Co-processor. E: 40 MHz / 4KB cache / FPU / HW Co-processor.

E: 40 MHz / 4KB cache / FPU / HW Co-processor. A Low-Cost FPGA-based Embedded Finger

Index

Introduction Software Architecture Hardware Architecture Conclusions

Architecture Hardware Architecture Conclusions A Low-Cost FPGA-based Embedded Finger print Verification and

Conclusions

Conclusions I mplementation of a fingerprint minutiae extraction and matching algorithm Spartan3 based low-cost system

Implementation of a fingerprint minutiae extraction and matching algorithm Spartan3 based low-cost system Embedded Leon2 soft-processor. Minutiae extraction process has been accelerated in a

94.14%.

HW co-processor is estimated to speed-up the MINDTCT algorithm up to a 97.89%. Commercial systems use very high frequency clocks. Extrapolating results (400MHz) Minutiae extraction performed in 0’3 s.

Thanks for your assistance A Low-Cost FPGA-based Embedded Finger print Verification and Matching System 26

Thanks for your assistance