ENEL3DE

DIGITAL ELECTRONICS INTRODUCTION TO SEQUENTIAL DEVICES

ENEL3DEH2

SEMESTER 2 2010

CONTENTS Combinational vs Sequential Circuits Stability of Circuits Latches vs Flip Flops

SR Latch
D Latch D Flip Flop SR Flip Flop JK Flip Flop

T Flip Flop

ENEL3DEH2

SEMESTER 2 2010

COMBINATIONAL LOGIC CIRCUIT The output values depend only on the current values of the signals applied to the inputs.
Output is a pure function of the present input only. Mostly implemented by Boolean circuits.

x1 xn

Combinational logic

z1 zn

x1 x2

z1

Examples
TV channel selector with no up and down buttons

ENEL3DEH2

SEMESTER 2 2010

SEQUENTIAL LOGIC CIRCUIT

A combinational circuit and storage elements (storing binary information) are interconnected to form a sequential circuit. The current output depends on the current input and past history of all inputs seen by the circuit. Require use of storage elements - circuits that are capable of storing binary information (Flip flops and latches). Circuit goes through sequence of states as a result of changes in inputs. The binary information stored in these elements (contents of the storage elements) at any given time defines the state of the sequential circuit at that time. The outputs in a sequential circuit are a function not only of the inputs, but also of the present state of the storage elements. The next state of the storage elements is also a function of the inputs and the present state. A sequential circuit is specified by a time sequence of inputs, internals states, and outputs.
ENEL3DEH2

Example: TV channel selectors up and down buttons.SEMESTER 2 2010

CIRCUIT-LEVEL MODEL OF A SEQUENTIAL CIRCUIT.

I/p from

x0 xn-1 yk-1 y0 Current State Memory Unit Combinational Circuit y y0

k-1

Z0 Zm-1

Going to external

external
point

world

State
bits of seq. ckt.

Next
State

The STATE of a sequential circuit is a collection of state variables whose value at any time contain all the information about the past necessary to account for the circuits future behavior.
A circuit with k binary state variables has 2k possible state, which is called FINITE STATE MACHINE. m outputs only depend on k PS bits - Moore Machine m outputs depend on k PS bits AND n inputs - Mealy Machine
ENEL3DEH2 SEMESTER 2 2010

COMBINATIONAL VS SEQUENTIAL CIRCUITS

x1 xn
I/p from external point

x0 xn-1 yk-1

Combinational logic

z1 zn
Z0

Going to
external world

Combinational Circuit yk-1 y0

Zm-1

State
bits of seq. ckt.

y0

Current
State
ENEL3DEH2

Memory Unit

Next State
SEMESTER 2 2010

SUMMARY OF DIFFERENCE BETWEEM SEQ&COMBI

Combinational Circuits No Memory Sequential Circuits Memory

No flip-flops, only combinational gates No feedback Output for a given set of Inputs is independent of order in which these inputs were changed, after the output stabilizes.

Flip-flops may be used. Combinational gates may be used Feedback is allowed The order of input change is quite important and may produce significant differences in the output.

ENEL3DEH2

SEMESTER 2 2010

THE CLOCK
The state changes of most sequential circuits occur at times specified by a clock signal.

A clock signal is active high if state changes occur at the clocks rising edge or when the clock is HIGH. Otherwise, it is active low.
Clock circuits are triggered as level or edge triggered.

ENEL3DEH2

SEMESTER 2 2010

TYPES OF SEQUENTIAL CIRCUITS 1. Feedback sequential circuits Use ordinary gates and feedback loops to obtain memory elements (latches and flip-flops). In the circuit, the next stage is triggered by the completion of the previous stage without reference to a clock pulse.

2. Clocked synchronous state machines Use latches and flip-flops to create circuits that are regulated by a controlling clock signal. In the circuit, changes in output do not occur immediately when there is a change in input, but the next time there is a clock pulse.
ENEL3DEH2 SEMESTER 2 2010

Other Classification Two main types based on the times at which their inputs are observed and their internal state changes. Synchronous the behavior can be defined from the knowledge of its signals at discrete instants of time e.g. latches. Asynchronous the behavior depends on the inputs at any instant of time and the order in continuous time in which the inputs change.

More complex asynchronous sequential circuits are very difficulty to design their behavior depends highly on the propagation delay of the gates and the timing of the input changes.
Almost all digital design done today is synchronous sequential design.
ENEL3DEH2 SEMESTER 2 2010

BISTABLE ELEMENTS

ENEL3DEH2

SEMESTER 2 2010

BISTABLE

ENEL3DEH2

SEMESTER 2 2010

ENEL3DEH2

SEMESTER 2 2010

LATCHES AND FLIPFLOPS Latches and flips-flops are the basic building blocks of most sequential circuits. A flip-flop is a sequential device that samples its inputs and changes its outputs only at times determined by a clocking signal. A latch is a sequential device that watches all of its inputs continuously and changes its outputs at any time.

Level sensitive devices are often referred to as latches, while edge triggered devices are called flipflops.

ENEL3DEH2

SEMESTER 2 2010

LATCHES A latch is a memory element whose excitation input signals control the state of the device. Excitation inputs: those inputs are used to excite or drive the circuit into a desired state.

If a latch has an excitation input signal that forces the output of the device to 1, it is called a set latch.
If a latch has an excitation input signal that forces the output of the device to 0, it is called a reset latch. If the device has both set and reset excitation signals, it is called a set-reset latch.

ENEL3DEH2

SEMESTER 2 2010

THE S-R LATCH

An S-R latch can be built with NOR gates. Q is usually the complement of Q. Case 1: S=0, R=0, Qt+1= Qt ; the state does not change. The circuit behaves like the bistable element. Case 2: S=0, R=1, Qt+1= 0, Reset operation, Q output to 0 Case 3: S=1, R=0, Q 1, Set operation, Q output to 1.
t+1=
Q S (a) Circuit R Q

S 0 0

Q Q0

Q0

Previous

0
1 1

1
0 1

0
1 0

1
0 0

Reset
Set Undesirable

Either S or R may be asserted to force the feedback loop to a desired state. Case 4: S= R=1, Q t+1= 0 , the case will be not allowed because it results metastable if S and R negative ENEL3DEH2 simulataneously..

B) Functional Table

SEMESTER 2 2010

S-R LATCH SYMBOL AND TIMING DIAGRAMS

t1 1 R 0 1 S 0 1 Q 0 1 Q

t2

t3

t4

t5

t6

t7

t8

t9

t10

Depending on gate delay

?

0
Time

After S or R is negated, the latch remains in the state that it was forced into.
ENEL3DEH2 SEMESTER 2 2010

S-R METASTABLE BEHAVIOR The SR latch with NOR gates can enter metastable state if S and R negative simulataneously.
simulataneously S Forcing Q and Q to be 0 R Gate delay results in metastable

Q is 1 if the delay of Gate 1 is less than gate 2. Q is 0 if the delay of Gate 1 is greater than gate 2.

2 (a) Circuit

ENEL3DEH2

SEMESTER 2 2010

THE S - R LATCH
We will sometimes use S-R for ease of notation An S-R latch can be built with NAND gates. Case 1: S =1, R=1, Qt+1 = Qt the state does not change. ;
R R
(a) Logic diagram

S S

Case 2: S=0, R=1, Qt+1= 1, Set operation, Q output to 1. Case 3: S=1, R=0, Qt+1= 0, Reset operation, Q output to 0 Either S or R may be asserted to force the feedback loop to a desired state.
S 0 R 0 1

Q 1

Undesirable

0
1 1

1
0 1

1
0 Q0

0
1 Q0

Set
Reset Previous

Case 4: S= R=0, Q 0 , the case will be not allowed.

t+1=

b) Functional Table

ENEL3DEH2

SEMESTER 2 2010

S S

S R

Q Q

R
t1 1 R 0 1 S 0 1 Q 0 1 Q

R
t2 t3 t4 t5 t6

Q
t7 t8 t9 t10

Logic symbol
Forcing Q and Q to be 1

S
?

R
Gate delay results in metastable

Time
ENEL3DEH2

(d) Timing diagram

SEMESTER 2 2010

S-R LATCH WITH ENABLE An S-R latch is sensitive to its inputs at all times. It may be modified to be sensitive to these inputs only when an enabling input C is asserted. The circuit behaves like an S-R latch when C=1. It retains its state when C=0.

ENEL3DEH2

SEMESTER 2 2010


C 0 1 1 1 1 S x 0 0 1 1 R x 0 1 0 1 t (+ 1) Q(t) (no change) Q(t) (no change) 0 1 x

1 C 0 1 R 0 1 S 0 1 Q 0 Q 1 0 Time ? ?

ENEL3DEH2

SEMESTER 2 2010

D LATCHES Latches are needed to store bits of information. A D latch can be used for that purpose. The D latch can be built from an S-R latch.

This latch eliminates the troublesome situation in S-R latches, where S and R may be asserted simultaneously.
When C = 1, the latch is open and the Q output follows the D input. When C=0, the latch is closed. Input value D is passed to output Q when C is high Input value D is ignored when C is low

ENEL3DEH2

SEMESTER 2 2010

D Latch Q0 indicates the previous state (the previously stored value) X D S

Q C Q

Y
D 0 1 X
ENEL3DEH2

1 1 0

Q 0 1 Q0

Q 1 0 Q0

X Y 0 0 1 1 X 0 1 0 1 X

Q Q Q0 0 1 1 Q0 Q0 1 0 1 Q0 Store Reset Set Disallowed Store

SEMESTER 2 2010

1 1 1 1 0

D Latch x
E

D C

Latches on following edge of clock z

E

x z Z only changes when E is high

If E is high, Z will follow X

The D latch stores data indefinitely, regardless of input D values, if C = 0 Forms basic storage element in computers
ENEL3DEH2 SEMESTER 2 2010

D (Data)

S
Q

Clk Q

D 0 1 X

1 1 0

Q 0 1 Q0

Q 1 0 Q0

(a) Circuit
t1
Clk D Q

Combinational logic Level sensitive

t2 t3 t4

Initial state
ENEL3DEH2

Time

(b) Timing diagram

SEMESTER 2 2010

Symbols for Latches

SR latch is based on NOR gates

SR latch based on NAND gates

D latch can be based on either.

D latch sometimes called transparent latch

ENEL3DEH2 SEMESTER 2 2010

SUMMARY OF LATCHES

Latches are based on combinational gates (e.g. NAND, NOR)

Latches store data even after data input has been removed

S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset)
With additional gates, an S-R latch can be converted to a D latch (D stands for data) D latch is simple to understand conceptually When C = 1, data input D stored in latch and output as Q When C = 0, data input D ignored and previous latch value output at Q
ENEL3DEH2 SEMESTER 2 2010

FLIP FLOPS Latches respond to trigger levels on control inputs Difficult to precisely time when to store data with latches A latch is transparent its input value can be seen from the outputs. Due to the feedback in a sequential circuit the state may keep changing. Flip flips store data on a rising or falling trigger edge. They are edge triggered. Latches are level sensitive
Example: control input transitions from 0 -> 1, data input appears at output Data remains stable in the flip flop until next rising edge.

In a flip-flop before an output can change, the path from its input to output is broken. A flip-flop cannot see the change of its output.
ENEL3DEH2 SEMESTER 2 2010

D LATCH + CLOCKING = D FF
D C Q

S S

R R When C is high, D passes from input to output (Q) Clocking- output only changed on a C transition Positive edge triggered
D C Q Q

D 0 1 X

1 1 0

Q 0 1 Q0

Q 1 0 Q0

D C Q 0 0 1 1 X 0 Q0
Lo-Hi edge

Q 1 0 Q0

ENEL3DEH2

Hi-Lo edge

SEMESTER 2 2010

Master-Slave D Flip Flop Consider two latches combined together.

Only one C value active at a time.

Output changes on falling edge of the clock.

ENEL3DEH2

SEMESTER 2 2010

MASTER-SLAVE D FLIP-FLOPChanges its

Master D Clock D Q Slave

state while Clock=1

Qm

Qs

Q Q

Q Q

Clk Q

Clk Q

(a) Circuit
Clock

Changes its state while clock=0

(b) Graphical symbol

D Q

CLK

D
Qm Q = Qs

0 1

0 1

Initial
ENEL3DEH2

gate d

hol d

gate d

(d) Function table

(c) Timing diagram

Pulse triggered

SEMESTER 2 2010

 From the external observers point of view, the master-slave circuit changes its state at the negative-going edge of the clock. The negative edge is the edge where the clock signal change from 1 to 0.

Regardless of the number of changes in the D input to the master stage during one clock cycle (clock is 1), the observer of the Qs signal will see only the change that corresponds to the D input at the negative edge of the clock.
D Q Q

Q = D and (Clock )

ENEL3DEH2

Negative edge of the clock

SEMESTER 2 2010

Clocked D Flip-Flop D gets latched to Q on the rising edge of the clock. Input changes at other times have no effect on output

ENEL3DEH2

SEMESTER 2 2010

Positive and Negative Edge D Flip-Flop D flops can be triggered on positive or negative edge

Bubble before Clock (C) input indicates negative edge trigger

Lo-Hi edge
ENEL3DEH2

Hi-Lo edge
SEMESTER 2 2010

MASTER SLAVE S-R FLIP FLOP

ENEL3DEH2

SEMESTER 2 2010

MASTER SLAVE J-K FLIP FLOP

ENEL3DEH2

SEMESTER 2 2010

Positive Edge-Triggered J-K Flip-Flop

Created from D flop J sets

J K CLK Q 0 0 1 1 0 1 0 1

K resets
J=K=1 -> invert output
ENEL3DEH2

Q0 Q0 0 1 1 0
TOGGLE
SEMESTER 2 2010

Clocked J-K Flip Flop Two data inputs, J and K

J -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table

ENEL3DEH2

SEMESTER 2 2010

T FLIP FLOP

ENEL3DEH2

SEMESTER 2 2010

 T FF

ENEL3DEH2

SEMESTER 2 2010

Positive Edge-Triggered T Flip-Flop

Created from D flop T=0 -> keep current

K resets
T=1 -> invert current
ENEL3DEH2

T C 0 1

Q0 Q0
TOGGLE

SEMESTER 2 2010

Asynchronous Inputs J, K are synchronous inputs o Effects on the output are synchronized with the CLK input. Asynchronous inputs operate independently of the synchronous inputs and clock o Set the FF to 1/0 states at any time.

ENEL3DEH2

SEMESTER 2 2010

Asynchronous Inputs

ENEL3DEH2

SEMESTER 2 2010

Asynchronous Inputs

Note reset signal (R) for D flip flop

If R = 0, the output Q is cleared This event can occur at any time, regardless of the value of the CLK

ENEL3DEH2

SEMESTER 2 2010

Parallel Data Transfer Flip flops store outputs from combinational logic

Multiple flops can store a collection of data

ENEL3DEH2

SEMESTER 2 2010

Sequential Switching Networks Latches vs. Flipflops

Input/Output Behavior of Latches and Flipflops

Type
unclocked latch

When Inputs are Sampled

always

When Outputs are Valid

propagation delay from input change

level sensitive latch

clock high

propagation delay from input change

positive edge FF

clock lo-to-hi transition propagation delay from input change

negative edge FF

clock hi-to-lo transition

propagation delay from input change

master/slave FF

clock hi-to-lo transition

propagation delay from input change

ENEL3DEH2

SEMESTER 2 2010

Flip-Flop Characteristic Tables

A characteristic table defines the logical properties of a flip-flop by describing its operation in tabular form.

48
ENEL3DEH2

SEMESTER 2 2010

Summary Flip flops are powerful storage elements They can be constructed from gates and latches! D flip flop is simplest and most widely used. Most FPGA families only have DFFs DFF is fastest, simplest (fewest transistors) of FFs. Other FF types (T, JK) can be built from DFFs Asynchronous inputs allow for clearing and presetting the flip flop output

Multiple flops allow for data storage The basis of computer memory!
Applications of FF: Data storage, Frequency division, Counting, etc

ENEL3DEH2

SEMESTER 2 2010