TestbenchesinVerilog Test benches in Verilog

TestBench Test Bench

As digital systems become more complex it complex, becomes increasingly important to verify the functionality of a design before implementing it in a system HDLs have become extremely popular because they can be used for both Designing and Testing

TheDeviceUnderTest The Device Under Test

The DUT is the behavioral or gate level representation of a design This is also known as a Register Transfer Level or RTL description of the design E hf Each feature of the d i should b tested to f h design h ld be d ensure that unexpected bugs have not been introduced i i d d into the d i h design

RoleofaTestbench Role of a Test bench

The Test bench provides the stimulus to the DUT A waveform capture is used to monitor/display the results
VerilogTest benchgives Stimulus

RTLDesign DUT

Waveform Waveform Capture

Testbenchcontinued Test bench continued

Let us write a Test bench for a 2:1 Mux g g Before going for the Test Bench, let us revisit the RTL of a 2:1 Mux
module mux 2to1(Y, A, B, sel); mux_2to1(Y, output Y; input A, B; input sel; reg Y; always @(A or B or sel) if (sel == 1'b0) Y = A; else Y = B; endmodule

LetuswriteaTestBench Let us write a Test Bench

`timescale 1ns / 100ps module Test_mux_2to1; wire Y; reg A, B; reg sel; mux_2to1 mydut(.Y(Y),.A( A), .B(B),.sel( sel)); initial begin Sel = 0; A = 0; B = 0; #10 A = 1b1 1b1; #10 sel = 1b1; #10 B= 1b1; end endmodule Let us start from the top of the test p bench and try to understand it line by line.

UnderstandingTestbench Understanding Test bench

`timescale 1ns / 100ps module Test_mux_2to1; wire Y; reg A, B; reg sel; mux_2to1 mydut(.Y(Y),.A( A), .B(B),.sel( sel)); initial begin Sel = 0; A = 0; B = 0; #10 A = 1b1 1b1; #10 sel = 1b1; #10 B= 1b1; end endmodule This line is called the timescale compiler directive directive This line is important in a Verilog simulation, because it sets up the time scale and operating precision for a module It causes the unit delays to be in nanoseconds (ns) and the precision at which the simulator will round the events down to at 100 ps. This causes a #5 or #1 in a Verilog assignment to be a 5 ns or 1 ns delay respectively The rounding of the events will be to .1ns or 100 pico seconds.

UnderstandingTestbench Understanding Test bench

`timescale 1ns / 100ps module Test_mux_2to1; wire Y; reg A, B; reg sel; mux_2to1 mydut(.Y(Y),.A( A), .B(B),.sel( sel)); initial begin Sel = 0; A = 0; B = 0; #10 A = 1b1 1b1; #10 sel = 1b1; #10 B= 1b1; end endmodule This line gives a name to our Test bench Observe the difference between this line of a test bench and normal verilog code Normal verilog code is like the line given below module mux_2to1(Y, A, B, sel); No need to give Ports in a testbench!!!!

UnderstandingTestbench Understanding Test bench

`timescale 1ns / 100ps module Test_mux_2to1; wire Y; reg A, B; reg sel; mux_2to1 mydut(.Y(Y),.A( A), .B(B),.sel( sel)); initial begin Sel = 0; A = 0; B = 0; #10 A = 1b1 1b1; #10 sel = 1b1; #10 B= 1b1; end endmodule There are two signal types in the test bench b h used to drive and monitor signals dt di d it i l during the simulation These two types of signals are reg and wire types The reg data type holds a value until a new value is driven onto it The wire type is a passive data type that gives a value driven on it by a port Since our aim is to simulate, inputs are to be given by the user. So, the inputs in the RTL code become reg type in test bench in order to hold the value given by the user The outputs in the RTL become wire type in testbench so that the user can it /di l the l monitor/display th value

UnderstandingTestbench Understanding Test bench

`timescale 1ns / 100ps module Test_mux_2to1; wire Y; reg A, B; reg sel; mux_2to1 mydut(.Y(Y),.A( A), .B(B),.sel( sel)); initial begin Sel = 0; A = 0; B = 0; #10 A = 1b1 1b1; #10 sel = 1b1; #10 B= 1b1; end endmodule The test bench applies stimulus to the DUT To do this the DUT must be instantiated in the test bench A name has to be specified during p g instantiation. (In this case, the name is mydut ) Port mapping is done in instantiation Port mapping is the logical connection of the names of the ports defined in RTL and in the Test bench The .Y represents the name of the port iin RTL t The (Y) represents the name of the port in testbench .Y(Y) logically maps the Y port of the ( ) g y p p RTL to the Y port in testbench

UnderstandingTestbench Understanding Test bench

`timescale 1ns / 100ps module Test_mux_2to1; wire Y; reg A, B; reg sel; mux_2to1 mydut(.Y(Y),.A( A), .B(B),.sel( sel)); initial begin Sel = 0; A = 0; B = 0; #10 A = 1b1 1b1; #10 sel = 1b1; #10 B= 1b1; end endmodule we can generate the required waveform on the A, B and SEL inputs in the initial block Initial blocks start executing sequentially at simulation time 0 Starting ith the first line between th St ti with th fi t li b t the begin end pair each line executes from top to bottom until a delay is reached. When a delay is reached, the execution of this block waits until the delay time has passed and then picks up execution p p p again.

UnderstandingTestbench Understanding Test bench

Sel = 0; A = 0; B = 0; First of all, Sel is set to 0, then A, then B. All three are set to 0 at simulation time 0. ; #10 A = 1; In terms of simulation, the simulator now advances by 10 time units and then assigns 1 to A. #10 SEL = 1; #10 B = 1; These two lines are similar to the one above. 10 time units after A iis set t 1 SEL iis set t 1 ti it ft t to 1, t to 1. Another 10 time units later (so we are now at simulation time = 30 time units), B is set to 1. Since our timescale compiler directive is set as `timescale 1ns / 100ps, one time unit is 1ns.

WaveformscapturedinXilinxISim Waveforms captured in Xilinx ISim

Testbenchfora4bitupcounter Test bench for a 4 bit up counter

module my_counter (clock , reset , enable , counter_out ) t t ); input clock ; input reset ; input enable ; output [3:0] counter_out ; reg [3:0] counter out ; counter_out always @ (posedge clock) begin if (reset == 1'b1) begin counter_out <= 4'b0000; end else if (enable == 1'b1) begin counter_out <= counter_out + 1; end end endmodule
timescale 1ns / 100ps // timescale directive module my counter tb; // No ports my_counter_tb; //Declare inputs as regs and outputs as wires reg clock, reset, enable; wire [3:0] counter_out; // Instantiation by giving a name and port mapping my_counter mc1(.clock(clock),.reset(reset),.enable(enable),.co unter_out(counter_out)); Initial begin clock = 1; reset = 0; enable = 0;//Initialise values #5 reset = 1; #10 reset =0; #10 enable = 1; #100 enable = 0; end always begin // clock pulse changes every 5ns #5 clock = ~clock; end endmodule

UnderstandingtheTestbench Understanding the Test bench

In the above testbench for a counter we come Intheabovetestbenchforacounterwecome acrossalways blockwhichisusedtogenerate theclock the clock initial andalways blocksexecuteconcurrently ineverymoduleatthestartofsimulation. in every module at the start of simulation

WaveformscapturedinXilinxISim Waveforms captured in Xilinx ISim