Errata 2nd Ed.

(6/3/09)

Page 1

Errata of CMOS Analog Circuit Design 2nd Edition

By Phillip E. Allen and Douglas R. Holberg

Page
Errata
82 Line 4 after figure 3.2-3, CISW  CJSW
88 Line between Eqs. (3.3-2) and (3.3-3) should read as The channel
transconductances, gm and gmbs, and the channel conductance, gds, are defined as
102 Line 2 from bottom: 2F  2F
115 Replace the NMOS symbol in Fig. 4.1-2 with the one for an NMOS transistor in
Fig. 3.1-1 of pp. 73 with the bulk connected to ground (assumed to be the lowest
potential).
117 Fig. 4.1-5, replace symbol with the NMOS symbol on pp. 73.
117 Fig. 4.1-6, replace symbol with the NMOS symbol on pp. 73.
125
1
1
Eq. 4.2-3 should be: rout =

g

gm
+
gds
m
126
130
133
133
134
134
138
138
138

138
146

146

Fig. 4.2-3, replace symbol with the NMOS symbol on pp. 73.
Eq. (4.3-11), no / sign in numerators
Solution part to Example 4.3-3: delete 2  in 2  500 10-6 when calculating
W/L
Solution part to Example 4.3-3: 0.0626  0.0625 when calculating W/L
Line 3 from the bottom, delete is greater thanVT2
Eq. (4.4-1): 1 vDS2  1 + vDS2
Line 2 of Example 4.4-1: Change the values from W1 = 5 0.05m and W2 = 20
0.05m W1 = 5 0.1m and W2 = 20 0.1m
Second and fourth lines of the solution: W1 = 5 0.05m  W1 = 5 0.1m
and W2 = 20 0.05m  W2 = 20 0.1m
Solution part to Example 4.4-1, line 6:
W2 = 20+0.05  W2 = 20+0.1 = 4 1(0.1/20)
4 10.1 1-0.1

1(0.1/5) 

50.06
50.1
20 

5 
W1
W1

0.1 0.4

4
1 20 - 20  = 4 - (0.03)
Last line of Ex. 4.4-1: ratio error is 1.25%  ratio error is 0.75%
Eq. (4.5-9):
VREF
VREF
 VDD 

 VDD 
1
1




S
=
 S
=


VDD
1+(VREF-VT)R
VREF
VDD
1+2(V -V )R
VREF
DD T


R2
R1



Eq. (4.5-10): VREF = VGS
1+R   VREF = VGS
1+R 
1

155
Eq. (4.6-10): =

VBE-VG0
V -V
k 

  = BE0 G0 + ( - ) k 
+
(


)

q
T0
T0

Errata 2nd Ed. (6/3/09)

156
171
172
175
178
188
188
197
198

Eq. (4.6-21): VBE2
VBE1

Eq. (5.1-15): Cout = Cbd1Cbd2 + Cgs2 + CL
Cout = Cbd1 + Cbd2 + Cgs2 + CL
Line 3: voltage gain is 1.92 V/V.
voltage gain is 2.098 V/V.
11018
-
0.72
11013
-
0.72
Eq. For vOUT(min): 1
-
 502 5
-
0.7 "
1
-
 502 5
-
0.7 "
Eq. (5.1-32): eout =
eeq =
Fig. 5.2-8(a): The VCCS in parallel with rds2 should be gm2vgs2 instead of
gm1vgs1.
Fig. 5.2-8(b): The VCCS in parallel with the i3 VCCS should be gm2vgs2 instead
of gm1vgs1.
Last line: P = 0.5V-1
P = 0.05V-1
First eq. in step 5.): Should be
VDS(sat) = VIC(min) VSS VGS1 = -1.5 + 2.5 -

198

198
198
198
211

Page 2

250A
0.7
110A/V2(18.4)

Last eq. on page: Should be

W5
2I5
=
L5 K ' VDS
(sat)2 = 306
N
3rd line from bottom: giving a smaller W5/L5.
to allow for a variation in
VTN.
2nd line from bottom: W1/L1 (W2/L2) = 25, which gives W5/L5 = 12.3.
W1/L1
(W2/L2) = 40, which gives W5/L5 = 82.
Last line: 111.1 V/V
147.4 V/V
2150A
2150A
1104.26 = 0.8 V
=
1102.73 = 1.0 V
Line between 1st and 2nd eqs.: VDS2(sat) = 0.7 V.
VDS2(sat) = 0.5 V.

First eq. on this page: =

211
211
211
225
225
225
225
256
266

2150
2150
= 5.57"
=
= 10.9"
2
1100.7
1100.52
Third eq. on this page: = 0.8 V + 0.7 V
= 1.0 V + 0.5 V
Fig. 5.5-7(a): The bulk VCCS for M1 should be gm1vbs1 instead of gm1vgs1.
Fig. 5.5-7(a): The VCCS for M2, gm2vgs2 should be pointing upward.
Fig. 5.5-7(a): The bulk VCCS for M2 should be gm2vbs2 instead of gm2vgs2.
Fig. 5.5-7(b): The fourth VCCS from the left should be gm2vin instead of
gm1vin.
Fig. 6.2-6: Replace GB with 0dB frequency
Fig. 6.2-16(a): M4
M12.
Second eq. on this page: =

Errata 2nd Ed. (6/3/09)

Page 3

268

Cc

Fig. 6.2-18(c): Corrected figure

is shown. A is replaced by A.

+
Vi
.-

-A

+
gmIIVi

CII

RII

Vout
-

268

Eq. (6.2-56) should be:


-ACc  s+gmII/ACc
Vout(s)


Vin(s) = Cc
+CIIs+1/[RII(Cc
+CII)]

274
274

Table 6.3-1, last line: The downward arrrow  should be upward .

Table 6.3-2, entry 3.): Delete the equation
VDD+|VSS|

I5  10

2Ts

274

gm2
gm22
Last line: S1 = S2 = K 'I  S1 = S2 = K 'I
2 5
2 5
Fig. 6.4-2c: Replace gds1Vdd of the left-most controlled source with gds1Vdd +
gm1Vout

288
303

304

1
rds6+R2+g
rds6+R2
1
1
m10
Eq. (6.5-12): RA = 1+g r  g  RA = 1+g r
g
m6 gs6
m6
m6 ds6
m6
gm2vin
gm2vin
=

=
Eq. (6.5-16): = 

R9(gds2+gds5
R9(gds2+gds5) =


21+ g r
21+ g r


m7 ds7

304

m7 ds7

R9(gds2+gds5)
R9(gds2+gds4)


k
=
gm7rds7
gm7rds7
Eq. (6.5-20) should be written as,
-1
pout = R 'C
II out
After Eq. (6.5-20), replace where Cout by where RII = [(2+k)/(2+2k)] RII and
Cout
-1
-1
Eq. (6.5-23): p6


p


6
1


R2+g C6

R + 1 C
m10
 2 gm10 6
Eq. (6.5-17): k =

305

305
305

305
307

Line 9 from the bottom: Figure 6.5-8  Figure 6.5-7

8I5
8I7
Table 6.5-3, Step 3, third column: S5 =
,
S
=

KPVSD52 7 KPVSD72
2I5
2I7
 S5 =
, S7 =

2
KPVSD5
KPVSD72

Errata 2nd Ed. (6/3/09)

307
307

VDD-Vout(max)
VDD-Vout(min)

Table 6.5-3, Step 3, fourth column:

2
2
8I11
8I9
Table 6.5-3, Step 4: S11=
,
S
=

KNVDS112 9 KNVDS92

S11=

307
307

Page 4

2I11

2 , S9 =

2I9

KNVDS11
KNVDS92
Table 6.5-3, Step 5: VSD14(sat)/I14
VSD13(sat)/I12
2I4
Table 6.5-3: Step 8: K (V -V (max)+V )

K (V
P
DD in
T1
P

308

308

313
313

343
343
344
360

200x10-6


-6
110x10 -1.5+2.5-

 = 20
100
2
11035.9-0.75

2I4
Last Eq: S4 = S5
K [V -V (max)+V ] =
P
DD in
T1
2I4

S4 = S5

=
KP[VDD-Vin(max)+VT1]2
Fig. 6.6-7(b): The polarity of the upper Vcm source should be reversed.
Fig. 6.6-7(b): Replace the lower controlled source designation of AcVcm with
Ac(V1+V2)

2
Fourth line of Table 6.6-3: 6.0 1U should be 6.01U
Caption of Fig. 6.6-17: Input common-node should be Input common
mode
Prob. 6.3-10, 5th line: Delete positive and
Fig. P6.3-10: Change the power supplies to 1.5V and increase the W/L value of
M6 to 100/1.
Prob. 6.3-10: Add sentence Assume the parameters of the MOSFETs are given in
Table 3.1-2.
1
Eq. (7.1-8): Rout =

gm2




(gds6+gds7)1+g (gm6+gm8)Ro 

320
321

DD-Vin(max)+VT1)

225A
212516
Third Eq: S6 = S7 =S13 =
= 50
= 80
50A/V2(0.25V)2
2125A
212516

S6 = S7 =S13 =
= 50
= 80
2
2
50A/V (0.25V)
200x10-6
Sixth Eq: =

 = 20
100

2
110x10-6-1.5+2.5- 10035.9-0.75

=

308

2I4

m4

Errata 2nd Ed. (6/3/09)

 Rout =

Page 5

1


gm2




1+(gds6+gds7)1+g (gm6+gm8)Ro
m4

362
363
363
364

Eq. (7.1-11): Replace = with 

First line: ..that RL is smaller than rds11.  ..that the load reflected from the
emitter to base of Q10 is negligible with respect to r
10.
Last line: 469S  300S
gm9N
4690.4
1st Eq.: gmbs9 =
=
= 57.1S
2 0.7+2
2 2 +V
F

 gmbs9 =
364

364
373
387

389
394
394
394
396
398
399

gm9N
2 2F+VBS9

405

3000.4
= 36.5S
2 0.7+2

469S
2nd Eq.: AMOS = 469S+57.1S+4S+5S = 0.8765 V/V
300S
 AMOS = 300S+36.5S+4S+5S = 0.8683 V/V
4th Eq.: Avd(0) = (7777)(0.8765)(0.951) = 6483 V/V
 Avd(0) = (7777)(0.8683)(0.951) = 6422 V/V
-gm8
-gm8rds8gm10
Top line: p8  C  p8 

C8
8
1st complete paragraph: Replace this entire paragraph with the following:
The input common mode range of the differential-out op amps may appear to be
better because of the current source loads (M3 and M4 of Fig. 7.3-3). However, the
upper input common mode range becomes restricted by M6 and M7 of Fig. 7.3-3.
For example, in Fig. 7.3-3, the upper input common mode range is VDD + VT
where it is VDD + VT. for the folded-cascode differential output op amp of Fig. 7.35.
Eq. (7.3-4): = (vsg1 + vgs4) =  = (vgs1 + vsg4) =
Line after Eq. (7.4-5): gm1/C  gm1/Cc
ID1
ID1
Eq. (7.4-6): GB = (n kT/q)C  GB = (n kT/q)C
1
1
c
ID5
ID1
ID5
ID1
Eq. (7.4-7): SR = C = 2 C =  SR = C = 2 C =
c
c
3rd line from bottom: Figure 7.7-4  Figure 7.4-4
Line 1: M5 to M4  M6 to M4 and M7 equals M6  M7 equals M9
1st Eq.: Vds1(sat) =

404

BS9

2I1
KN
(W2/L2) =  Vds1(sat) =

Eq. (7.5-3): gm6RII2  gm6

2 RII2
Line following Eq. (7.5-8): Fig. 7.4-1  Fig. 7.5-1

2I1
KN
(W1/L1) =

Errata 2nd Ed. (6/3/09)

407
420
434
434
434
436
436
436
436
442
442
444
446
446
446

447

Line 7 including eqs.: 0.202 (Vrms)2  0.202 (Vrms)

Line 3 (2 lines after Eq. 7.6-10): above Vonn should be above Vonp
Prob. 7.1-10, 3rd line: Example 7.1-1  Example 7.1-2
Prob. 7.1-10: Add the sentence, Assume C
= 10 pF and C = 1 pF.
Prob. 7.1-10: Replace Example 7.1-1 with Example 7.1-2
Prob. 7.4-2, 2nd and 3rd line: all transistor widths are  transistors M1
through M11 widths are
Prob. 7.4-2, 5th line: ..the correct bias voltage for M10 and M11  the
W/L values of M12 through M15
Prob. 7.4-2, last line: np = 1.5 and nn = 2.5.  np = 1.5, nn = 2.5 and Vt =
26mV.
Prob. 7.5-5, 2nd line: of a  over a
Fig. 8.1-5, 1st line after Fig: VOH for (vP-vN) > 0  VOH for (vP-vN) > VIH
Fig. 8.1-5, 3rd line after Fig: VOL for (vP-vN) < 0  VOL for (vP-vN) > VIL
Next to last line: 2.5V should be -2.5V.
-(gds2+gds4)
-1
Eq. (8.2-4a): p1 = C (g +g )  p1 =

CI
I ds2 ds4
-(gds6+gds7)
-1

Eq. (8.2-4a): p2 = C (g +g )  p2 =
CII
II ds2 ds4
Av(0)
Av(0)
Eq. (8.2-5): Av(s) = 


A
(s)
=
v

 s

s

 s

s

+
1
+
1

-
1
-
1
p1
 p2

p1  p2 
1st eq.: p1 =

gds2
+
gds4 15x10-6(0.04+0.05)
=
= 6.75x106 (1.074MHz)
CI
0.2x10-12

gds2
+
gds4
15x10-6(0.04+0.05)
 p1 = == -6.75x106 (1.074MHz)
CI
0.2x10-12
447

gds6
+
gds7 95x10-6(0.04+0.05)
2 eq: p2 =
=
= 1.71x106 (0.670MHz)
CII
5x10-12
nd

gds6
+
gds7
95x10-6(0.04+0.05)
=
= -1.71x106 (0.670MHz)
CII
5x10-12


p2e--tp1 p1e--tp2

Eq. (8.2-6): vout(t) = Av(0)Vin 1
+
p -p
-
p -p 

1 2
1 2 
 p2 = -

447



p2e-tp1 p1e-tp2

 vout(t) = Av(0)Vin 1
+
p -p
-
p -p 

1 2
1 2
447

Page 6

t
Eq. (8.2-11): tn = tp1 =   tn = -tp1
1

Errata 2nd Ed. (6/3/09)

448

Page 7

tn
Eq. (8.2-12): vout(tn) = 1 - p1e-tn - p e-tn = 1 - e-tn - tne-tn
1

e tp1

448
448
454

e-tp1

 vout(tn) = 1 + tp1
= 1 e-tn - tne-tn
Line after Eq. (8.2-12): Delete where p1 is assumed to be unity.
Fig. 8.2-2: Normalized Time (tn = tp1 =t/1)  Normalized Time (tn = -tp1)
Eq. at bottom of page: = 0.7 +

2342
11038 = 1.035 V

2342
5038 = 0.496 V
Line 2: VTRP2 = 2.5 - 1.035 = 1.465 V  VTRP2 = 2.5 - 1.196 = 1.304 V
Line 3:
V1 = 2.5 V - 1.465 V = VSG6 = 1.035 V.

V1 = 2.5 V - 1.304 V = VSG6 = 1.196 V.
1.035V
1.196V
Line 5: tfo1 = 0.2pF  30A
 = 6.9 ns  tfo1 = 0.2pF  30A
 = 8 ns

 = 0.7 +
455
455
455
455
455
455
455

455

455
455

456
456
456
457
459
465

Line 9: 1.465 V  1.304 V

Line 13: 1.465 V  1.304 V
Line 14: 0.232 V.  0.152 V and 2.27 V  2.348 V
6
3850
Line 15: I6 = 2 (VSG6-|VTP|)2 = 2 (2.27 - 0.7)2 = 2,342A
6
3850
 I6 = 2 (VSG6-|VTP|)2 = 2 (2.348 - 0.7)2 = 2,580A
 2.5V 
Line 19: trout = 5pF 2,342A
 = 5.3ns


2.5V
 trout = 5pF 2,580A-234A
 = 5.3ns
Line 21: 12.2 ns  13.3 ns
1.465V-(-2.5)

= 26.43ns
Last line: tro1 = 0.2pF 

30A
1.304V-(-1.000)

= 15.4ns
 tro1 = 0.2pF 

30A
Line 3: 79.85 ns.  68.82 ns.
Line 5: about 44.93 ns.  about 41 ns.
Fig. 8.2-7: VTRP6 = 1.465V  VTRP6 = 1.304V Also, lower the dashed line.
VOH+VOL
VOH -VOL
Table 8.2-2, step 5: Av(0) = V (min)  Av(0) = V (min)
in
in
VOH+VOL
VOH -VOL
Tab;e 8.2-3, step 6: Av(0) = V (min)  Av(0) = V (min)
in
in
Fig. 8.4-1(b): The polarity of the voltage on CAZ should be reversed.

Errata 2nd Ed. (6/3/09)

468
469

Page 8

Fig. 8.4-7: VTRP

+ = -

R1VOL
R1VOH
and
V


=
TRP
R2
R2

R1
+
R2
R1
+
R2
V

REF
R1
R2 VREF
R1+R2
R1
+
Eq. (8.4-10): VTRP =  R VREF - R VOL
1
2
R1+R2
R1
 VTRP+ =  R VREF - R VOL
Fig. 8.4-8:

470

470

R1+R2
R1
Eq. (8.4-12): VTRP+ =  R VREF - R VOH
1
2
R1+R2
R1
 VTRP- =  R VREF - R VOH
2

470
470
470
470
471
471
478
480
480
481

First line after Eq. (8.4-12): (R1 + R2)/R1  (R1 + R2)/R2

 R 
 R2 
1

Eq. (8.4-13) and Eq. (8.4-14): + R +R VREF  + R +R VREF
1 2
1 2
First line after Eq. (8.4-14): R1/(R1 + R2)  R2/(R1 + R2)
R1
R2
Fig. 8.4-10: R
+
R VREF  R
+
R VREF
1
2
1
2
R1
R2
1st and 2nd equations: + R
+
R VREF  + R
+
R VREF
1
2
1
2
Last line of Ex. 8.4-1: VREF = 2 V  VREF = 0.667 V


Vo1
Vo1




Eq. (8.5-5): +sC1Vo1-
s  =  +sC1Vo1-
s  =
Ex. 8.5-1, line 3:
Vi = 0.01Vin(min) and
Vi = 0.1Vin(min).

Vi = 0.01(VOH VOL) and
Vi = 0.1(VOH VOL).
3rd line from bottom: given a latch gain of 59.2 V/V.  gives a latch gain
of 370 V/V.
Last eq. on page should be:

L = 0.67Cox
482
482
482
485
486
489

WL3
-4
2K'I = 0.67(24.7x10 )

(101)x10-24
= 0.112 ns
2110x10-610x10-6

First line: t = 4.6L = 496 ns  t = 4.6L = 0.515 ns

Second line: that t = 2.3L = 284 ns.  that t = 2.3L = 0.258 ns.
Third line: and is 174 ns and 422 ns and is 0.438 ns and 0.180 ns
Fig. 8.6-4: The pins FB and Reset associated with M2 should be reversed.
Fig. 8.6-5 Disconnect the line connecting the gate-drains of M3 and M4
Prob. 8.3-1,3rd line: what is the propagation  what is the slew rate
limited propagation

Errata 2nd Ed. (6/3/09)

502
502

543
543
549
552
554
557
563
564
565
567
572

Page 9

Eq. (9.1-34): v(n no)T  z -noTV(z)  v(n no)T  z -noV(z)

 C2  -1

C1  -1 o
o
Eq. (9.1-36): V 2 (z) =  1
-
C +C 
z
 = C +C  z
V 1 (z)
1
2
1
2
 C2  -1

C1  -1 o
o
 V 2 (z)  1
-
C +C 
z
 = C +C  z
V 1 (z)
1
2
1
2
Line 9: EODD  EVEN
Line 10: EVEN  EODD
Line 1: Eq. (9.5-1)  Eq. (9.5-2)
Line 3: Eq. (9.6-4)  Eq. (9.6-3)
Ex. 9.6-1, 2nd line of solution: 1/31.83.  1/0.0314 = 31.83.
Ex. 9.6-2, 2nd line of solution: 1/15.92.  1/0.0628 = 15.92.
PB
SB
Eq. (9.7-4):
n =  
n = 
SB
PB
Caption for Fig. 9.7-3: for = 1.  for  = 1.
Title for Table 9.7-1: for = 1.  for  = 1.
3rd and 4th line after Eq. (9.7-9): ( = 0.0233)  ( = 0.1526)
nd

2 line: 4252 =

2
0.1789Tn

 4252 = 0.1789Tn =
572
Last line: 63 =

573
557
580
587
607
613

618

0.1789PB2
fc2

0.17892

= 0.05620
20

0.1789PB 0.17892

=
= 0.05620
fc
20

2
0.4684Tn

0.4684PB2
fc2

0.46842

= 0.1472
20

0.4684PB 0.46842

=
= 0.1472
 63 = 0.4684Tn =
20
fc
Line 2: 43 = 0.1472.  63 = 0.1472.
Eq. (9.7-24): Numerator term, + (35 - 15 - 23)z + 
+ (35 + 15 - 23)z +
SW SB2
-
SB1
SW SB2
-
SB1
Eq. (9.7-42): n = BW = BP2
-
PB1  n = BW = PB2
-
PB1
Fig. 9.7-18: The upper input capacitor should be labeled 21C2
Prob. 9.7-4, 1st line following eq.: to 1000 Hz  to be 1000 Hz
b1 b2 b3
bN
Eq. (10.1-3): vOUT = KVREF = 21
+
22
+
23
+
...
+
2N
b1 b2 b3
bN
 vOUT = KVREF 21
+
22
+
23
+
...
+
2N
Eq. (10.1-15):
Vcx

Vs
V

  100% =  cx
-
1 LSBs
Differential nonlinearity (DNL)=  V

V

s

Errata 2nd Ed. (6/3/09)

Page 10

Vcx
-Vs
Vcx 

 Differential nonlinearity (DNL)= (Vcx  Vs) =  V  Vs =  V
-
1

 LSBs
s
s
621
629

Line 14: LSB  0.5LSB

vstep(actual)
-
vstep(ideal) vstep(actual)
= v (ideal) - 1
Eq. (10.2-15): DNL =
v (ideal)
step

step

vstep(actual)
-
vstep(ideal)

v (ideal)
 DNL = vstep(actual) - vstep(ideal) = 
vstep(ideal)
 step
vstep(actual)
= v (ideal) - 1 LSBs
step
630

1 64  64  1 
Last line of solution: DNL = 100 64
 = 100
 64
 = 0.64 LSBs
1
 DNL = 100 LSBs = 0.01 LSBs

641

Eq. 10.3-11 The summation should be i=0 through 7 not 8.

8

biVREF

2i

i=0

biVREF

2i

i=0
= 1C

644

 CM-1
Fig. 10.3-9: CM-2 =
CM = 2C  CM = C

644
645

5th line below Eq. (10.3-17): 2K-1.  2M-1.


R
C 
Eq. (10.3-24): INL = INL(R) + INL(C) = 2M-1
R
+
2N-1
C

 LSBs

R
C 
 INL = INL(R) + INL(C) = 2K-1
R
+
2N-1
C

 LSBs

645

R
C 
Eq. (10.3-25): DNL = DNL(R) + DNL(C) =  R
+
(2N-1)
C

 LSBs

22C

, CM-1 = 2C  CM = C and

R
C 
 DNL = DNL(R) + DNL(C) =  R
+
(2N-2K) C

 LSBs
645
646

647
647

3rd line after Eq. (10.3-25): of 2K  of 2M

2nd sentence in Ex. 10.3-4: To minimize the capacitor element spread and the
number of resistors, choose M = 5 and K = 7.  To emphasize the accuracy of
the capacitors, choose M = 7 and K = 5.
R
C
R
C
4th line: 1 = R + (212-1) C  1 = R + (212-27) C
C
C
24
-
2
th
6 line: C = 16 11 4 = 0.000221  C = 0.0211% is replaced by

2
-
2
-
2

C
C
24
-
2
C = 16 11 11 = 0.000228  C = 0.0228%

2
-
2
-
2

Errata 2nd Ed. (6/3/09)

647
647
667
671
675
701
702

Page 11

Lines 11 and 12 of Ex. 10.3-4, Solution: increase the value of M and decrease
 decrease the value of M and increase
Line 13 of Ex. 10.3-4, Solution: choose K = 5 and M = 7  choose M
= 5 and K = 7
v
in*
v
in*
 Nout = NREF V

Eq. (10.6-4): Nout = NREF - V

REF
REF
Line 2: than  then
Eq. (10.7-8): + 22b2 +  + 22b1 +
Fig. 10.9-5 The sign of the output of the integrator (v[nTs]) returned to the
summing junction in the left shaded box should be + and not -.
The correct Fig. 10.9-6 is shown:

x[nTs]+

Integrator 1

+
-

Delay

Integrator 2
Delay

+
-

y[nTs]

Quantizer

Figure 10.9-6 Sampled-date model of a second-order modulator.

704
719
719

720
720

723

723
724
725
729
753

3 2L+1
3 2L+1
Eq. (10.9-12): 2 2L M2L+12B-1  2 2L M2L+1(2B-1)2




Prob. 10.3-2: if the divisor is 3 and 6.  if the divisor is 3 and 5.
Fig. P10.3-7: The vertical resistor connected to the right of the resistor Rx, should
have the value of 2R rather than 4R and the 4R between the horizontal
resistors Rx and 4R should be deleted.
Fig. P10.3-8: The subscripts of the bits, bi, should all be decreased by 1. I.e. b1
 b0, b2  b1, etc.
Fig. P10.3-10: The subscripts for b should increase from right to left and not left
to right. In addition, a vertical line should be drawn from the left most switch
terminal labeled b0 (old labeling) to the VREF battery.
Prob. 10.4-4, lines 4-6: If the attenuation factors of 0.5 become 0.55, at what bit
does the converter create an error? What is the analog output for this case?
Replace with If the attenuation factors of 0.5 become 0.55, what is the analog
output for this case?
Prob. 10.4-7, 1st line: ADC  DAC
Prob. 10.6-2, 1st line: Give a switched For Fig. 10.6-2, give a switched
Prob. 10.7-12, last line: in part (a)?  in part (a) if VREF = 1V.
Fig. P10.9-9: fs = 2fo  fs = 4fo
Ex. B1.-4, 1st line of Solution: Eq. (B.1-40),  Eq. (B.1-34),