A PFC Rectifier for Telecommunications High Power Applications

J.E. Baggio, H.L. Hey, H.A. Grndling, H. Pinheiro, J.R. Pinheiro

Federal University of Santa Maria CT / NUPEDEE / GEPOC 97105-900 Santa Maria RS Brazil e-mail: josebaggio@ieee.org, renes@ctlab.ufsm.br
Abstract - This paper presents a new power factor corrected rectifier for telecommunications applications, where main switches support only half of the dc bus voltage at both preregulator and dc-dc converter. The power factor correction is performed by a three-level boost pre-regulator that produces a half-shared dc bus. This dc bus supplies an isolated dc-dc converter, which is composed of two half-bridge converters connected in series. The dc-dc converter is phase-shift modulated and operates with ZVS in full-load range. The main features of the dc-dc isolated converter are: (i) each switch is designed to support only half of the maximum dc voltage; (ii) the current stresses are equally distributed among the switches, allowing conduction losses reduction; (iii) the use of two high frequency transformers connected in series makes this converter appropriate for high-power applications; (iv) the voltage ratings of input capacitors of the dc-dc converter is one-quarter of the bus voltage; (v) there is no low frequency dynamics on input capacitors voltage, associate to duty-cycle variations. Experimental results for 1.5W/60V/25A, design procedures and comparisons between the use of phase-shift-modulation and pulse-width-modulation are presented.

I. INTRODUCTION In last decades, telecommunications has presented a great expansion, requiring isolated PFC rectifiers of higher and higher power capability. Moreover, standards have become more restrictive, demanding rectifiers with high performance and low EMI. One of the most explored converter which attend telecommunications specifications is the isolated PWM-ZVS dc-dc full-bridge converter. This converter achieves softswitching and operates with fixed frequency with a simple logic command, which is similar to conventional hardswitched dc-dc full-bridge converter [1,2,3]. The main drawback of this converter comes from the ratio between the desired ZVS operation range and the output load current. When the desired ZVS operation range is wide, the efficiency is penalized due to increasing of conduction losses. In this way, designers sacrifice soft-commutation at light load to obtain a converter with better efficiency. Moreover, the fullbridge converter presents disadvantages for high voltage applications because main switches are designed to support the entire dc bus voltage. As a result, conduction losses become significative when MOSFETs are used, since they increase with switches breakdown voltage capability. Alternatives to reduce the switches voltage sustaining ratings are the neutral-point-clamped (NPC) [16] and flyingcapacitor (FC) converters [15]. However, NPC converters

need additional diodes while FC converters require additional care to regulate the flying-capacitors voltage [15]. Other alternatives to reduce the maximum voltage across main switches are presented in [5] and [7], where two halfbridge converters connected in series are presented. In [5], the converter operates with phase-shift modulation (PSM), however the voltages across main switches are not equally distributed, since these voltages are function of the output voltage. In [7], the series converter operates with PWM and the voltages across the switches are equally shared. This converter dispenses with the use of extra components, and it is appropriate for high power applications due to the use of two high frequency transformers connected in series with reduced voltage across transformers terminals. On the other hand, the main disadvantages of this converter are related to the use of PWM in half-bridges cells. Due to this modulation, input capacitors must be designed to half of dc bus voltage. Moreover, the current through main switches are not equal, resulting in higher conduction losses when MOSFETs are used. In this paper, a rectifier composed of a three-level boost pre-regulator and a dc-dc ZVS isolated converter is proposed, as illustrated in Fig.1. The dc-dc converter is composed of two half-bridges converters connected in series. The use of phase-shift modulation reduces the input capacitors voltage stresses and the converter volume, when compared with the PWM converter [7]. Moreover, the current stresses are equally shared among switches, resulting in a higher efficiency converter.
Sb1 v1
Vo

Sb2 v2

Fig. 1 Proposed converter.

The commutation of the upper half-bridge converter is performed by the load current. This way, soft-commutation is naturally assured at high load current values. On the other hand, the lower half-bridge commutation is function of the energy stored in leakage transformers, similar to the fullbridge ZVS converter. This way, for both upper and lower half-bridges, ZVS is naturally obtained only with high load current. Therefore, an inductor can be placed in parallel with each transformer, or an appropriate magnetizing inductance

can be designed to enlarge the ZVS capability to entire loadrange. Due to the use of PSM in the series converter, two nonisolated dc sources are necessary to keep the half-shared dc bus voltage. This way, the three-level boost (TLB) converter, which can regulate two output dc bus voltages even for unbalanced loads [12], is utilized as PFC pre-regulator. Moreover, the TLB converter allows the use of switches and diodes rated for half of maximum dc bus voltage, attending the desired characteristic of the proposed rectifier. This way, switches with smaller conduction losses and diodes with smaller reverse recovery time can be used. Finally, the inductor volume of the TLB converter is one-quarter of the conventional boost inductor volume [10,11], reducing the overall converter volume. II. THE DC-DC CONVERTER 2.1 Operation Principle The dc-dc converter shown in Fig. 1 is composed of two half-bridge converters connected in series, controlled by

phase-shift modulation. The series connection of the transformers T1 and T2, a rectifier (Dr1, Dr2) and a second order filter (Lf, Cf) form the output stage of this converter. To describe the operation stages, transformers T1 and T2 turns ratio are the same; and magnetizing and leakage inductances are considered. All semiconductor devices are considered ideal. Each switch conducts 50% of the time, thus guaranteeing demagnetization of the high frequency transformers. The transformers leakages are represented by the series inductors Ls1 and Ls2, and can be represented as on the primary side as on the secondary side, without loss of generality. The output filter is considered large enough, and can be represented by a constant load current. Operation stages for half-cycle operation of the dc-dc series converter are presented as follows. The corresponding figures, representing these stages are depicted in Fig. 2. Stage 1 (t0-t1): Initially, it is assumed that switches S1 and S3 are on and transformers T1 and T2 transfer energy to the load. The parallel inductors currents evolve with a positive slope due to capacitors voltages Cin1 and Cin3.

(a) Stage 1;

(b) Stage 2;

(c) Stage 3;

(d) Stage 4;

(e) Stage 5;

(f) Stage 6;

(g) Stage 7; Fig. 2 Operation Stages of the series converter with PSM

P h a se sh if t vG S1 vG S2 vG S3 vG S4

D T /2 T

T /2

E /2

vD SS1 vD SS3 vT1

E /2

E /4

iL p 1

side of the transformers, diodes Dr1 and Dr2 are on, applying zero Volt on the load. Stage 6 (t5-t6): At t5, the sum of current through transformer T1 and the current through parallel inductor Lp1 reaches zero and diode D2 blocks. Stage 7 (t6-t7): At t6, the sum of current through transformer T2 and the current through parallel inductor Lp2 reaches zero and diode D4 blocks. This stage ends when the current trough secondary side of transformers reaches the load current value and diode Dr1 blocks, at t7. The second half period is identical to the first one, considering the symmetrical operation of the converter. Main theoretical waveforms of the proposed converter are presented in Fig. 3. III. THEORETICAL ANALYSIS

E /4

iL p 2

vT2
E /2

vT1+ vT2 Io iT1 = iT2 -I o

t0 t1 t2 t3 t4 t5 t6 t7 t8

Fig. 3 Main theoretical waveforms.

Stage 2 (t1-t2): At t1, switch S1 is turned off. The load current and the inductor Lp1 current perform the commutation of capacitors C1 and C2 in a linear way. The parallel inductor Lp1 must be designed to perform the ZVS in a maximum defined time, when there is no load current. Stage 3 (t2-t3): At t2, the voltage across C2 reaches zero and the diode D2 turn on under ZVS. Switch S2 is turned on under ZVS too. The load current freewheels through diodes Dr1 and Dr2. The current through parallel inductor Lp1 decreases with constant slope due to the capacitor Cin2, and parallel inductor Lp1 current increases due to capacitor Cin3. Stage 4 (t3-t4): At t3, the switch S3 is turned off. The energy stored in series inductors (Ls1 and Ls2) and parallel inductor Lp2 evolves in a resonant way with the energy stored in capacitors C3 and C4. The voltage across capacitor C3 increases and the voltage across capacitors C4 decreases in a resonant way. Stage 5 (t4-t5): At t5, the voltage across C4 reaches zero and diode D4 turns on. Switch S4 is turned on with ZVS. The current through the primary side of transformers decreases linearly until zero, at the end of this stage. In the secondary

3.1 Transformers turn-ratio The transformer design must consider the duty-cycle reduction due to the presence of leakage transformer. The maximum output voltage V0max is given by (1). E 2 Vomax = min V DSon (2 Dmax Dloss ) V Fdiode (1) 4 n where Emin is the minimum input voltage, VDSon is the voltage on the MOSFET, VFdiode is the conduction voltage on the rectifier diodes, n is the transformer turn-ratio and Dloss is the duty-cycle reduction due to the leakage transformers inductance, given by (3). 8 f .L .I Dloss = s s o (2) n.Emin where fs is the switching frequency, Ls is the sum of transformers leakage inductances (Ls1+Ls2) and Io is the maximum output load current. The transformers turn-ratio can be obtained by substituting (2) in (1) and isolating n, as (3). (3) Fig. 4 presents the relation between the transformers turnratio and the leakage transformers inductance for the set of specification defined in Table 1.
3 2.5 n 2 1.5 1

6 9 Ls(H)

12

15

Fig. 4 Transformers turn-ratio versus transformers leakage inductance.

n=

Emin .Dmax (4VDSon Emin ) + Emin (4VDSon Emin ) E min .Dmax2 (4VDSon Emin ) + 16 fs.Ls .Io. Vomax + VFdiode 2 Emin V0 max + VFdiode

)]

(3)

3.2 Input capacitors analysis The input capacitors are designed for one quarter of the maximum dc bus voltage due to the phase-shift modulation. The high frequency voltage ripple across the capacitors is calculated considering the current through the capacitors in one operation cycle. The maximum ripple on input capacitors can be approximate by (4), if the duty-cycle reduction is not considered. 0.5I 0 T VCin1 4 = (4) 2nC where C=Cin1=Cin2=Cin3=Cin4, T = 1 / f s and fs is the switching frequency. The value of input capacitors can be obtained by (5), for a maximum defined input capacitor voltage ripple (VCmax). 0.5I 0 T C= (5) 2nVCmax In [12] it has been shown that when two half-bridges are connected in series, the use of PSM produces an undesired energy transference from the lower half-bridge to the upper one. This transference occurs in stage 3 where input capacitor Cin3 transfers energy to Cin2, and in stage 10, where input capacitor Cin4 transfers energy to Cin1. The leakage inductances keep the current flow in the capacitors forcing energy transference between the capacitors. The input capacitor voltage variation due to this effect is presented in (6). i (0.5 D)T VCin3 = o (6) nC Consequently, the energy transferred between the capacitors can be obtained as follows: 1 (7) E Cin3 = CVCin3 2 2 Due to this amount of energy transferred from the lower half-bridge to the upper one, an unbalance of voltage occurs, and the input capacitors Cin1 and Cin2 voltages increase, while Cin3 and Cin4 voltages decrease [12]. To compensate this voltage unbalance across the two half-bridges, it is employed the three-level boost converter, with the technique proposed in [11], which can perform the voltage equalization on unbalanced loads. 3.3 Commutation trade-off Two types of commutations occur on the proposed converter. The commutation on stage 2 is performed by the load current. This way, the use of a parallel inductor or the design of an appropriate transformer magnetizing inductance is necessary to assure ZVS when there is no load current. The current necessary to perform ZVS in switches S1 and S2 in a maximum defined commutation time (Tcom) is given by (8). E = 2Ccom iC (8) com 2Tcom where Ccom=C1=C2=C3=C4.

The current peak IpeakLp1 in parallel inductor Lp1 is defined by (9). Assuming that the parallel inductor current is high enough and can be seen as a current source by the commutation capacitor, the parallel inductor Lp1 value can be obtained by adopting iCcom = IpeakLp1. As a result, (10) is obtained. T .E I peakL p1 = (9) 16 L p1 T .Tcom (10) 16C com On the other hand, the commutation of the lower halfbridge (stage 6) depends of the energy stored in the series and in the parallel inductor Lp2. If there is no load current, there is no enough energy to perform the soft switching. The same procedure to obtain the parallel inductor value Lp1 can be adopted to obtain the parallel inductor value Lp2. This way, Lp2 is given by: T .Tcom L p2 = (11) 16C com L p1 = IV. PHASE-SHIFT VERSUS PULSE WIDTH MODULATION The use of two half-bridges converters connected in series allows the use of either PSM or PWM. Each modulation presents particular characteristics that are highlighted in this section. In [7], the converter with PWM was presented, and in [14] an optimization method to minimize switches conduction losses for this converter operating with ZVS in entire load range was presented. The same optimization method can be applied for the series converter operating with PSM. For comparison between the use of PSM and PWM on the series converter with ZVS in entire load range the following aspects are analyzed: i) parallel inductor values, and consequently, the reactive circulating energy; ii) the current sharing among the switches; iii) the input capacitor; iv) the dc bus half-sharing . The output rectifier stage is identical for both modulations and is not considered in this analysis. 4.1 Parallel Inductors values In [14] it was shown that when PWM is used, the parallel inductors values are function of the series inductors, the dutycycle and the load current. This way, to obtain the parallel inductor value, it is assumed the worst case, where the load current is null and a minimum duty-cycle is defined. Therefore, when the converter operates at nominal load where the duty-cycle in near to 0.5, the parallel inductor peak current increases and, consequently, the reactive circulating energy is increased too. On the other hand, when PSM is adopted, the duty-cycle is 50% and the parallel inductor peak current is constant. As a consequence, the reactive circulating energy is constant and smaller than the reactive circulating energy of the PWM dcdc converter. This way, higher efficiency can be obtained.

4.2 Current share among the switches In converters with PSM, each switch conducts 50% of the time, and consequently, the current is equally shared among the switches. On the other hand, when PWM is used, one switch is penalized, conducting the load current a longer time than the other, considering a single leg. This unbalance is more critical when the converter operates in current mode and small duty-cycles are necessary, with high load current. Moreover, when MOSFETs are utilized as main switches, the conduction losses of converter with PWM become higher than the one of the converter with PSM. This way, the converter efficiency is reduced when PWM is used. 4.3 Input capacitors values When PWM is used, the voltages across input capacitors Cin1-4 are function of the duty-cycle [7], and are given by (12). E VCin1 = VCin 4 = D , 2 (12) E VCin 2 = VCin3 = (1 D) . 2 As a consequence, two input capacitors (Cin2, Cin3) must be designed to support half of dc bus voltage, and the other two capacitors (Cin1, Cin4) are designed to support one-quarter of the dc bus voltage. Moreover, the input capacitors values are different [7]. This is an additional point to be analyzed for industry stock management and manufacturing procedures. On the other hand, when PSM is utilized, all input capacitors are designed to support only one-quarter of the dc bus voltage. In addition, all capacitors present the same value. Other important point to be analyzed about the input capacitors is the low frequency dynamics present in the input capacitors voltages when PWM is used. Since the input capacitors voltages are function of the duty-cycle, dynamics associated to duty-cycle variation occur when there is load current perturbations, such as load connected or disconnected from the converter. These voltage dynamics consist an additional care to be analyzed in the point of view of the converter control. However, the effects of such dynamics are overcome when PSM is used, since the input capacitors keep the voltage equal to one-quarter of dc bus voltage. 4.4 Dc bus half-sharing As presented in [7], the use of PWM produces the halfsharing of the dc bus voltage between the two half-bridges. On the other hand, as shown in this paper, the use of PSM produces a voltage unbalance between the half-bridges. Therefore, two dc non-isolated sources are necessary to supply the series converter The adopted solution to implement these dc sources is the use of the TLB converter, due to its capability of maintain the half-shared dc bus voltage even for unbalanced loads, such as the series converter with PSM.

V. EXPERIMENTAL RESULTS Experimental results are presented to demonstrate the feasibility of the proposed converter. The design specifications are presented in Table 1 and the devices and components utilized in the prototype are presented in Table 2.
TABLE 1 DC-DC CONVERTER SPECIFICATIONS

E Vout Iout fs Tcom

400V 60V 25A 90kHz 250s

TABLE 2 PARAMETERS AND COMPONENTS UTILIZED IN THE PROTOTYPE

DEVICE PARAMETER S1, S2, S3, S4 IRFP 360 D1, D2, D3, D4 MOSFETs intrinsic diodes C1, C2, C3, C4 1F Dr1, Dr2 MUR 3060 T1, T2 EE 65/26 Thornton 12:5 turns Cin1-4 5 X 1F Icotron Ls Series transformers leakage 10 H Lp1, Lp2 174 H EE 30/14 Thornton 14 turns Lf 24H EE 55/21 Cf 220 F- Icotron Figures 5 and 6 show the ZVS for operation at full-load and at no-load, respectively. It can be seen in both figures that the gate signal is applied only after the switch drainsource voltage reaches zero, characterizing the ZVS.

vDS

vgate

Fig. 5 Switch S1 drain-source voltage and gate-source voltage.

1% in the converter efficiency, when compared to the use of PWM in the series converter.

vDS

vgate iDr1
Fig. 6 Switch S1 drain-source voltage and gate-source voltage.

In Fig. 7 are presented the current trough the primary winding of transformer T2, iTr2 and the parallel inductor current iLp2. It can be seen that the peak current in parallel inductor is much smaller than the load current through the transformer. This way, the reactive energy due to parallel inductor presence is small.

Fig. 8 Rectified secondary transformers voltage and rectifier diode current iDr1.
93,0% 92,5% 92,0%

PSM PWM

iTr2 iLp2

91,5% 91,0% 90,5% 90,0% 89,5% 89,0% 0 500

Output Power

1000

1500

Fig. 9 Measured efficiency of the series converter with PSM and with PWM.

VI. CONCLUSIONS
Fig. 7 Transformer current iTr2 and parallel inductor current iLp2.

Fig. 8 shows the voltage applied in the second order filter vT1+vT2 and the current trough diode Dr1. It can be seen the peak current due to the diode reverse recovery current as well as the effect of the clamper utilized in the rectifier diodes. The efficiencies of the series converter with PSM and with PWM are presented in Fig. 9. As previously presented, the PSM allows the converter to operate with higher efficiency than with PWM. An exception occurs at low load, since the duty-cycle is reduced, and consequently, the parallel inductor current is reduced, when PWM is used. However, at high load, the use of PSM produces and improvement of around

This paper presents an alternative to the full-bridge converter for high-voltage high-power applications, where the main switches are rated for half dc bus voltage. This way, switches with reduced conduction losses can be used providing higher efficiency. The proposed rectifier is composed of a PFC three-level boost pre-regulator and a dc-dc converter that performs the isolation and output voltage regulation. The dc-dc converter operates with ZVS in entire load range due to the inductor placed in parallel with each transformer. The proposed converter presents the following advantages when compared to the series converter operating with PWM [7]: (i) voltage reduction across dc-dc converter input capacitors; (ii) there is no input capacitors low frequency

voltage disturbances due to duty-cycle variations; (iii) symmetric load current share through switches; (iv) lower rms current through switches, resulting in a converter with higher efficiency. Two non-isolated dc sources are necessary to supply the series arrangement of the half-bridge converters with PSM. Here, a TLB-PFC rectifier is utilized due to its capability of maintain the half-shared dc bus voltage even for unbalanced loads, such as the series converter with PSM. Experimental results for 60V/25A are presented to demonstrate the feasibility of the proposed converter. Comparisons between the use of PSM and PWM on the series converter are presented, where an improvement in the converter efficiency of 1% at full load can be obtained due to the use of PSM instead of PWM.

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