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FPGA Implementation Of Direct Sequence Spread Spectrum (DSSS)

A Mid Term Thesis Report

Thesis Examiners:

1) Prof. M.V. Joshi 2) Prof. Deepak Ghodgaonkar

Examiners: 1) Prof. M.V. Joshi 2) Prof. Deepak Ghodgaonkar Thesis Supervisor: Prof. Rahul Dubey Submitted by:

Thesis Supervisor:

Prof. Rahul Dubey

Submitted by:

Vivek Kr. Choudhary

[200611029]

Dhirubhai Ambani Institute of Information and Communication Technology Gandhinagar India November 2007

Contents

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Introduction

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Problem Definition

 

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Progress on the Problems

 

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Future Work

 

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References

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18

1. Introduction

Error free communication is an important aspect of high speed wireless communication development. It depends on the thoroughness with which, the building blocks and atmospheric condition .Noise, attenuation causes main problem i.e. bits of information may lost in communication medium, so it is necessary to detect and correct a bits of information at receiving end because retransmission not possible for high speed data communication. One way to solve this problem is to use Direct Sequence Spread Spectrum (DSSS) Technique. Because of spread spectrum signal are highly resistant to noise and interference. Direct Sequence Spread Spectrum (DSSS) involves spreading the data signal in frequency domain by multiplying it with a PN-sequence [6] .A common technique for generating this sequence is by using a Linear Feedback Shift Register (LFSR). In some situations it is required that a communication signal be difficult to detect, and difficult to demodulate even when detected. Here the word „detect‟ is used in the sense of „to discover the presence of‟. The signal is required to have a low probability of intercept - LPI. In other situations a signal is required that is difficult to interfere with, or „jam‟. The „spread spectrum‟ signal has properties which help to achieve these ends. Spread spectrum signals may be divided into two main groups - direct sequence spread spectrum (DSSS), and frequency hopping spread spectrum (FHSS).

1.1 Principle of DSSS

Consider the frequency translation of a baseband message (of bandwidth B Hz) to a higher part of the spectrum, using DSBSC modulation [6]. The resulting signal occupies a bandwidth of 2B Hz, and would typically override the noise occupying the same part of the spectrum. This makes it easy to find with a spectrum analyser (for example), and so the probability of intercept is high. A local carrier, synchronized with that at the transmitter, is required at the receiver for synchronous demodulation. The recovered signal-to-noise ratio is 3 dB better than that measured at its original location in the spectrum. This 3 dB improvement comes from the fact that the contributions from each sideband add coherently, whereas the noise does not. This can be called a 3 dB Processing gain‟, and is related to the fact that the transmission bandwidth and message bandwidth are in the ratio of 2:1. In a spread spectrum system literally thousands of different carriers are used, to generate thousands of DSBSC signals each derived from the same message. These carriers are spread over a wide bandwidth (much wider than 2B Hz), and so the resulting DSBSC signals will be spread over the same bandwidth. If the total transmitted power is similar to that of the single DSBSC case, then the power of an individual DSBSC in the spread spectrum case is thousands of times less. In fact, over the bandwidth occupied by one of these DSBSC signals, it would be literally „buried in the noise‟.

1.1.1

Processing gain:

To achieve most of the claims made for the spread spectrum it is necessary that the bandwidth over which the message is spread be very much greater than the bandwidth of the message itself. Each DSBSC of the DSSS signal is at a level below the noise, but each is processed by the synchronous demodulator to give a 3 dB SNR improvement. The total improvement is proportional to the number of individual DSBSC components. In fact the processing gain of the system is equal to the ratio of DSSS bandwidth to message bandwidth.

1.1.2 A DSSS generator:

To generate a spread spectrum signal one requires:

1. A modulated signal somewhere in the RF spectrum

2. A PN sequence to spread it

These two are combined as shown in Figure 1.

to spread it These two are combined as shown in Figure 1. Figure 1: Basis of

Figure 1: Basis of spread spectrum

There are two bandwidths involved here: that of the modulated signal, and the spreading sequence. The first will be very much less than the second. The output spread spectrum signal will be spread either side of the original RF carrier (ω0) by an amount equal to the bandwidth of the PN sequence. Most of the energy of the sequence will lie in the range DC to ωs, where ωs is the sequence clock. The longer the sequence the more spectral components will lie in this range. The modulated signal can be of any type, but typically digitally-derived, such as binary phase shift keyed - BPSK. In this case the arrangement of Figure 1 can be expanded to that of Figure 2. A digital message is preferred in an operational spread spectrum system, since it makes the task of the eavesdropper even more difficult.

Figure 2: A spread BPSK signal The arrangement of Figure 2 can be simplified by

Figure 2: A spread BPSK signal The arrangement of Figure 2 can be simplified by noting that, if the clock of the bipolar message is a sub-multiple of the clock of the PN sequence, then the modulo two sum of the message and the PN sequence can be used to multiply the RF carrier, generating a DSSS signal with a single multiplier.

1.1.3 A DSSS demodulator: A demodulator for the DSSS of Figure 1 is shown in block form in Figure 3.

for the DSSS of Figure 1 is shown in block form in Figure 3. Figure 3:

Figure 3:

DSSS demodulator

The input multiplier performs the de-spreading of the received signal, and the second multiplier translates the modulated signal down to baseband. The filter output would probably require further processing - not shown - to „clean up‟ the waveform to binary format. The PN sequence at the receiver acts as a „key‟ to the transmission. It must not only have the same clock and bit pattern; it must be aligned properly with the sequence at the transmitter.

1.2 Transmission basics of spread spectrum:

1.2 Transmission basics of spread spectrum: Fig 4: A baseband model of a DS-CDMA transceiver Spread

Fig 4: A baseband model of a DS-CDMA transceiver

Spread Spectrum uses wide band noise-like signals. Because Spread Spectrum signals are noise-like, they are hard to detect. Spread Spectrum signals are also hard to intercept or demodulate .further Spread Spectrum signal are harder to jam (interfere with) than narrowband signals. These low probability of intercept (LPI) and anti-jam (AJ) feature are why the military has used Spread Spectrum for so many years. Spread Signals are intentionally made to be much wider band than the information they are carrying to make them more noise-like and even for some case the transmitted signal power goes down the noise power.

1.3 Pseudo Random noise codes and code rates:

noise power. 1.3 Pseudo Random noise codes and code rates: Fig 5: Bit duration of data

Fig 5: Bit duration of data signal, PN code and coded signals.

Spread Spectrum signal use speedy code that runs many times the information bandwidth or data rate. These codes are fast or have a much higher data rate than the original information signal. This is done, so that the actual timing of data is still same, but we have smaller bit duration of codes that are being used. These special “Spreading” code called “Pseudo Random” or “Pseudo noise” codes (also referred as PN). These pseudorandom codes themselves have high data rate or low bit duration, and this enables for us to maintain of the original source signal. Code rate from under a bit per second to several hundred mega bits per second. But long PN-sequence generation takes many register and Flip Flop which occupy significant area of VLSI technology.

2. Literature survey:

As I mentioned earlier the problem , Long Feedback Shift Register Implementation[1] has been solve by Synchronous RAM (on chip FPGA). In general ,the implementing long Shift register as PN sequence generator can occupy significant area in VLSI technology or large number of CLBs in FPGA technology. Figure 6 shows implementation of LFSR

using 32x1 synchronous RAM takes 3 CLBs (6 flip flop). The standard implementation of shift register based only one FFs will require 32 FFs plus additional control logic. Rest of two problems still remain same and need to be solved. I am trying to solve error detection and correction when data bits are lost due to:

1)

Attenuation and attenuation distortion

2)

Delay distortion

3)

Noise

Above problem could be solved in many ways as there are many algorithm which can solve digital error detection and correction problem [3]. In CRC-16 over 16 bits of data are using detection multiple bit error detection and single bit error correction on

FPGA. These things are used in internet and computer networking having speed of Gbps range. In this case if header bits or data bits are lost, retransmission will take place, but in case of wireless network, again retransmission of data is not possible. Because of this reason wireless network requires detection and correction of data at receiving end.This can be made possible by some useful error detection and correction algorithm. Same thing is happening in high speed wireless system network. Following are the some algorithms which can solve above problem:

a) Hamming Code Logic

b) Cyclic Redundancy Check (CRC)

c) Viterbi Algorithm

Fig 6: LFSR Implementation using on-chip FPGA RAM 3. Problem Definitions The problems are defined

Fig 6: LFSR Implementation using on-chip FPGA RAM

3. Problem Definitions

The problems are defined as follows:

1. Implementation of Long feedback shift register (LFSR):

Problem of generation of long PN-sequence it‟s needed more number of flip flop to implement LFSR.

2. Synchronization of PN-sequence between transmitter

and receiver: Long PN sequence and high speed communication causes synchronization problem.

3. Error correction and detection at receiving end: Digital-Bit

errors caused by

a) Attenuation and attenuation distortion

b) Delay distortion

c) Noise

Data can be corrupted during transmission. For reliable communication, error must be

detected and corrected.

3.1 TYPES OF ERRORS

Whenever bits flow from one point to another, they are subject to unpredictable changes because of interference. There are two types of error .

3.1.1 Single Bit Error

In a single-bit error, only one bit in the data unit has changed.

3.1.2 Burst Error

A Burst error means that 2 or more bits in the data unit have changed.

3.2 Error Detection and Correction

Error detection is the ability to detect errors; Error correction has an additional feature that enables identification and correction of the errors. Error detection always precedes error correction, both can be achieved by having extra or redundant or check bits in addition to data deduce that there is an error i.e. Original Data is encoded with the redundant bit(s) and new data formed is known as code word.

3.2.1 Hamming Code Logic

Hamming provide s a practical solution and can be applied to data units of any length and uses the relationship between data and redundancy bits [3]. In figure 6 bits are placed in position 1, 2, and 8. For clarity in the examples below, we are referring to these bits as r1, r2, r4, and r8.

below, we are referring to these bits as r1, r2, r4, and r8. Each data bit

Each data bit may be including in more than one calculation. In the sequences above, for example, each of the original data bits is included in at least two sets, while the r bits are included in only one.

3.2.1.1 Calculating the r values

Fig 8 shows a Hamming code implementation for an ASCII character [3]. In first step, we place each bit of the original character in its appropriate position in 11-bit unit. In the subsequent steps, we calculate the even parities for the various bit combinations. The parity value for each combination is the value of the corresponding r bit.

3.2.1.2 Error Detection and Correction

Now imagine that by the time the above transmission is received, the number 7 bit has been changed from 1 to 0. The receiver takes the

Fig 8: Example of redundancy bit calculation Transmission and recalculation 4 new parity bits, using

Fig 8: Example of redundancy bit calculation

Transmission and recalculation 4 new parity bits, using the same sets of bits used by the sender plus relevant parity r bit for each set(fig 9).Then it assembles the new parity values into a binary number in order of r position (r8, r4, r2, r1). In our example, this step gives us the binary number 0111(7 in decimal), which is the precise location of the bit error.

In our example, this step gives us the binary number 0111(7 in decimal), which is the

Once the bit is defined, the receiver can reverse its value and correct the error. The beauty of the technique is that it can easily be implemented in hardware and the code is correct before the receiver knows about it.

4 Progress on the Problems

I have done encoding part (4 bit data input) of hamming code Logic and rest of part i.e. decoding will be done in next month ,then I will try to go for implement of higher data inputs . After this I will try to use Viterbi Algorithm because its work only receiving end, so no need of encoding. Some simulation result is shown in fig 11: Fig12: and table.

receiving end, so no need of encoding. Some simulation result is shown in fig 11: Fig12:

Fig 10: RTL schematic

Fig 11: Test Bench Waveform Test bench wave form is showing that how input data

Fig 11: Test Bench Waveform

Fig 11: Test Bench Waveform Test bench wave form is showing that how input data is

Test bench wave form is showing that how input data is being encoded as output. Some simulation results have been shown in the table.

5

Future Work

Adding of redundancy bits increases channel bandwidth therefore implementation of hamming code logic in wide band CDMA is best choice , because higher redundancy bit can detect and correct high data input bits. Viterbi algorithm also may be used because it work at the receiving end. All of above algorithm can detect multiple errors but correct only one bit error so we have to developed new algorithm that can detect and correct multiple bits errors.

7. References

[1] Predrag Markovic, Milan Markovic, FPGA/VLSI Implementation Analysis of PN Sequence Generator for Direct Sequence Spread Spectrum Systems. IEEE conference, Nis, Yugoslavia,13-15 October 1999. [2] Sunil Shukla, Neil W. Bergmann, SINGLE Bit Error Correction Implementation in CRC-16 on FPGA. IEEE conference, 6-8 Dec. 2004. [3] Behrouz A. Forouzan. Data Communications and Networking. McGraw-Hill 3rd edition, 1 Nov. 1994, pp. 257-259. [4] Bob Zeidman. “Verilog Designer‟s Library. Prentice Hall Modern Semiconductor Design Series, pp. 237-259. [5] K.H. Tsoi, K.H. leung and P.H.W. Leong, Compact FPGA based True and Pseudo random Number Generators”.IEEE conference, 9-11 April 2003. [6] Taub.Schilling. Principles of Communication System. TATA McGRAW-HILL EDITION, 2nd edition, pp 720-751.