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CHAPTER I
1. INTRODUCTION
1.1 Overview :
has become more sophisticated, the tools have evolved to fill new needs.
requirements that existing instruments could not meet. The designer needed
data registration or synchronisation between the two systems, data capture, data
sector of business and industry emphasises the need of an equipment for new
the most convenient trouble shooting tool for micro-computers. Despite its
name, the logic analyser does not analyse the data. Instead, it displays digital
digital data or in tabular forms as binary 1s and 0s that can be analysed by the
test engineer.
iii) In its spike mode, the analyser captures and displays the short
by conventional methods.
Although originated only in the early 1970's the logic analyser has
Data and control signals are given on the respective buses. When the
control signal matches with the data, the data is transferred on to the latches.
The point at which the data event is captured is called the trigger event.
From the latch, the data goes on to the decoder where it is decoded and given to
The trigger switch is used to clear the latches and the display and
set up and hold times, clock line reflections and other electrical phenomena that
can cause improper operation of a logic circuit. When these happenings need to
internal clock can store the logic value of each input at the sample time and
its glitch mode it can detect glitches, which are very narrow pulses coming in
n-waveforms.
algorithmic state machines where knowledge of the state sequences are most
defined by the system under test. Each channel is then interpreted as a logic
columns.
where each element of the matrix is a ‘zero’ or a ‘one’. Each row shows one
input and the n-elements of each row show the state of that input over a period
of n-clock pulses.
For example, when you analyse digital circuits, that have many
display and compare eight or more signals at the same time. This is one of the
functions of a logic state analyser. In its simplest form, a logic state analyser
is just a device that chops or alternates between eight or more input channels to
produce an oscilloscope trace for each. A word recogniser allows you to trigger
when a specific word or pattern of 1s and 0s is present on the input lines. Logic
analysers also may display the information from these channels as a string of 1s
CHAPTER II
As we have seen, there are two types of logic analysers. They are
logic state and logic time analysers. In both instruments, the input block
captures the logic sequence of 0s and 1s from the system under test and store
it in a digital storage unit. But display sections are different. In the time
wavefrom of voltage versus time. So if there are 'n' input channels, we get a
form. Each row of the matrix denotes a single word, and each element of the
16 bits of input data sequence for each clock pulse and stores it in a Random
Access Memory. Once the storing of a fixed number of words of 'zeros' and
'ones' is over, the control goes to the display section. Here, an internal clock
addresses the RAM through a memory address counter. The output of the RAM
is selected by the same clock serially and, using a digital multiplexer fed to
the 'Y'-input of the CRT through a D/A converter. For displaying a voltage
versus time waveform, a ramp is fed to the 'X' input. For state display, the
the beam is at a different level on the screen. Likewise, we can display all the
CRT and the same sinewave shifted by 90 in phase and slightly reduced in
'one', the cosine wave superimposing over the X-input is the output.
When a match between incoming data and a preset trigger word occurs, the data
acquisition block will store 16 or 32 words that follow the trigger word,
The start delay mode is essentially the same except that data
acquisition starts after the preset number of clock pulses are counted. Then
the acquisition continues for the next 16 or 32 clock pulses and stops.
In the end display mode, the trigger word comes in the last so that
on the screen, we get 15 words that come before the trigger word and finally the
trigger word also. This mode is useful to study what actually is happening
CHAPTER III
SYSTEM PLANNING
The two types of logic analyzers, viz. Time and state have been
analysers are superior. With this in mind, it was decided to build a simple
d) Good results can be obtained by limiting the band width in the range of
tens of kilohertz.
b) Display block
The functions of the two blocks are clear from the names itself.
As the name indicates, this is the block where the input data is
classify them as 'HIGH' or 'LOW'. This threshold level is made variable using
comparing of any family i.e., TTL, CMOS, ECL etc. Since each family has a
different threshold level. From the output of the temporary storage where
they are stored temporarily. The system clock also is taken through a
memory and to the trigger word comparator where they are compared with front
panel trigger word switch settings. When a match occurs, it will give an output
pulse which will enable the write enable pulse to reach RAM thus initiating the
storage process. Once 8 words are stored, the data index flip flop is set, thus
disabling the write pulse. Data ready output goes high which will enable the
display section. The Read/Write pin of the RAM becomes 'one' which will
Display Block :
counters. These select the word (8-bit) in the memory to be displayed and
positions the CRT beam by way of digital to analog converter. The required
CRT beam positioning waveforms are as shown in the Fig. . The count of
the horizontal counter is also applied to 1 of 8 selector that select the bit in a
and it steps through all of its 8 states before resetting. While resetting it
increments the memory address counter and the vertical counter. Thus all the 8
0's and l's only, these can be displayed on the CRO screen by making use of
the property of Lissajous figures. The lissajous figures are shown in Fig.
amplitude so that an ellipse is written. To trace a '1', the sine wave to the
switch.
sections, it is found that the following circuit blocks are required for system
realization :
a) Voltage comparators
c) Binary counters
d) Magnitude comparators
e) Monoshot multivibrator
g) Multiplexer
circuit form.
a) Voltage comparator :
provides 4 operational amplifiers in one chip thus reducing the number of chips
bit, 16 words capacity. So two 7489 RAMs in parallel provide the required 8-bit
word length. For temporary storage of data, before storing it in the RAM, 7475
c) Binary counters :
the display section, two 3-bit binary counters are required. 7493 is a suitable
choice as it provides both, the counter and also it can be reset to zero by simply
d) Magnitude comparator :
set any 8-bit word as a trigger word so that when the input word is the same,
the trigger word comparator triggers the data acquisition. To provide the
magnitude comparator. So, two 7485 ICs have been used to give the required
8-bit comparator. In each chip, A 0- A0 , are connected to the input and B 0,- B 0 ,
e) Monostable multivibrator
In the display section, the input has to be selected one by one and
they have to be displayed at a fast rate. For this, a clock of about 100 KHz is
g) Multiplexer unit :
The RAM gives out all the 8 lines in a parallel form. It has to be multiplexed
h) Flip-flops :
Two flip-flops are needed in the circuit. IC. 7476 is used since it
has two flip-flops on a single chip as also the necessary preset and clear
terminals.
CHAPTER IV
CIRCUIT DESIGN
The system planning of the logic state analyzer has been discussed
in the previous chapter. In this chapter, we shall discuss the .actual circuit
design.
output of the comparator will be in any of the two states, either 'HIGH' or
'LOW i.e., this circuit converts any input to a two level output. A comparator
compares the input with a reference voltage and tells whether it is greater
gain and hence it can be used as a comparator. We give the reference voltage to
the non-inverting terminal and input to the inverting terminal of the operational
amplifier. When input is less than V ref, the output goes 'high' and when the input
follows.
Let as assume that the Op-amp output is varying between 0 and V cc.
e1 < e1
e 0 = vcc
V ref R 2 + V cc R 1
e i1 =
R1 + R2
Once e1 < e0
e0 = 0
and V ref R 2
e i1 =
R1 + R2
So e i1 < ei2
Hence, even if e1 varies slightly’ the operational amplifier will not oscillate.
Whenever the input voltage goes higher than the reference level, the output
comes down. When the input voltage is less than the reference level, the output
goes 'high'.
R 1 = 10 Kilo Ohms
R 1 = 1 Mega Ohms
output of each Op-amp, makes it the standard TTL input to the latch.
There are two basic units here. First, the outputs of LM 324 is
stored in 7475 Quad Latch. This latch will take the input to its output when
clock goes 'high' and retain it when clock goes 'low'. The outputs of the latch
seconds pulse width. This is provided by monoshot 74123. For each rising
edge of clock, it will give a pulse of about 20 microseconds pulse width. The
where,
t w is the microseconds
R T is in Kilo Ohms
R = 10 Kilo Ohms
C = 6 K pF = 6 micro Farads
the pulse width of clock (coming out of the multivibrator) by choosing proper
values of R T and C ext in accordance with write enable pulse width of the RAM.
When we give proper address and write enable pulse, the RAM
will store the input word in that particular location. The chip select is grounded
so that always the RAM will be enabled. When the Read/Write pin is kept
'high', the output of RAM will be enabled. This is the Read Mode.
necessary to have a trigger word. We should be able to set any 8-bit word as
trigger word so that when the input word is same, the trigger word comparator
are connected in parallel and give the required 8-bit comparator. In each chip, A 0
- A3 are connected to the input word and B 0 - B 3 are the programmable trigger
any 8-bit reference word. Whenever a match occurs, the output of 7485 goes
'high'. This will set the 7476 master slave flip-flop which in turn enables the
on the screen. This requires a high frequency clock. LM 555 timer has been
t 1 = 0.693 R AC
R AR B R B - 2R A
t2 = .Cl n - RA
RA + RB 2 RB
This circuit will not oscillate if RB > ½ R A
R A = 18 Kilo Ohms
4 bit binary counter chip 7493 can be used as memory address counter. The
clock to this counter is the same as the write enable pulse of RAM. So, each
time the pulse goes 'low', it will enable the RAM for writing and when it goes
high, the counter increases one count and addresses the next location. When
the count reaches 9, a second master slave flip-flop is set. Thus Q becomes
zero. This will disable the write enable pulse. Also, the data ready
The display section also contains two such counters, one gives the
Resetting of horizontal counter will set vertical counter which helps to align
4.6 Multiplexer :
to one line 74151 multiplexer chip has been used for this. 3 bit address is given
to the chip to select the data. This address is derived from the horizontal
counter. The weighted resistor arrangement helps the beam to scan through
each bit and display it as either a '0' or a '1'. For different combinations of
counter outputs, the current flowing through the resistor will change and
hence the voltage drop across it also changes. This drop is given to 'X' and 'Y'
inputs.
X – input Y – input
There are two types of D/A converters; one which uses a binary
weighted resistor network, and the other which uses an R and 2R resistor
staircase waveform for positioning the CRO beam, an inverter is used along
with the D/A converter. The values of the resistors used are;
for Horizontal :
for Vertical :
CHAPTER V
Fabrication :
the whole circuit was rearranged in a proper way i.e., according to the
respective pin positions of each I.C. Next, the connections were made in such a
way so as to avoid any overlap as far as possible. Whenever, this was not
This circuit was then redrawn on an inch graph sheet with exact
dimensions of the ICs and pin distances. This circuit is called the 'art work'.
This was then pasted or fixed on to a single sided copper clad board. Holes were
then drilled into the board at the points of all the components. 0.7 mm φ
drill bit for ICs and 1 mm φ drill bit for resistors, capacitors etc., was used. The
graph sheet was then removed and using a 'marker' pen, all the circuit
connections were drawn on the copper board. This board was then dipped in
board was removed and washed throughly with water, it was ready to be
soldered upon, since all the area other than where the 'marker' pen was used,
was now devoid of copper. Marks of the marker pen are removed either by
and soldered and the circuit was then ready for testing. The PCBs copper
side is then coated with wax to avoid corrosion of copper due to ageing.
Testing :
For testing the circuit, a 7493, 4 bit counter IC was used. The
outputs of the counter are connected to the first four LSB bits of the input lines
of the analyser. The other four lines are grounded. The trigger word is set at
'0000' so that data acquisition starts as soon as the power is switched on.
oscilloscope and the oscilloscope is put in the external mode. On the CRO, we
got an output which showed us the states of the four counter outputs for eight
clock pulses.
The trigger word was then set at another value and it was seen
that the data acquisition started after that word and the data upto eight clock
APPENDIX – 1
8. number of channels 8
APPENDIX – II
LIST OF COMPONENTS
LM 324 3
7475 2
7485 2
7489 2
7476 1
7493 3
74151 1
74123 1
LM555 1
7408 1
7400 2
7404 1
10 Kilo ohms/1/4 W 12
1 Kilo ohms 9
1 Mega ohms 14
390 ohms 9
18 Kilo ohms 1
470 ohms 1
2N2222 1
10 Kilo ohms 1
47 Kilo ohms 1
22 Kilo ohms 2
REFERENCES
Adi. J. Khambatta.
by J.A. McCrindle.
by Doughlous. V. Hall.
by B.S. Sonde.
by Ramakant. A. Gayakwad.
CONTENTS
Sr. No. Particular Page No.
1. Introduction
1.1 Overview 1
1.2 Logic Analysers 1
1.3 Basic Logic Analyser 2
1.4 Types of Logic Analysers 3
2. A review of Logic Analysers
2.1 Working of a Typical Logic Analyzer 6
2.2 Modes of Operation 7
3. System Planning
3.1 Logic State Analyzer 9
3.2 Circuit Blocks 10
3.3 System Operation 10
3.4 Detailed Circuit Blocks 12
3.5 Choice of Devices and Integrated Circuits 13
4. Circuit Design
4.1 Operation Amplifier Comparator 15
4.2 Storage Unit 17
4.3 Trigger Word Comparator 18
4.4 Internal Clock Generator 19
4.5 Binary Counters 19
4.6 Multiplexer 20
4.7 Digital to Analog Convertors 21
5 Fabrication And Testing
5.1 Fabrication 22
5.2 Testing 23
Appendices 24
References 27