MOSFET Scaling and Small Geometry Effects

The lateral geometric dimensions oI devices and interconnects are reduced. This
reduction in size is reIerred to as 'Scaling dimensions oI the integrated circuit
(IC).
Minimum Ieature size is smallest size oI object (interconnect line width) on IC.
Minimum Ieature size oI ICs has shrunk considerably over the time oI several
decades. As a consequence, the number oI transistors has increased over time.






What is Scaling?
O #eduction in size oI an MOS chip by reducing the dimensions oI MOSFETs
And interconnects.
O #eduction is symmetric and preserves geometric ratios which are important
to the Iunctionality oI the chip. Ideally, allows design reuse.
O Assume that S is the Scaling Iactor. Then a transistor with original
dimensions oI L and W becomes a transistor with dimensions L/S and W/S.
O Typical values oI S : 1.2 1.5 per biennium.




GATE

Figure 3.24 $.,3 of , typ., MO$ET by , s.,3 f,.tor of S.
Scallng
Two major Iorms oI scaling
Full scaling (constant-Iield scaling) - All dimensions are scaled by S
and the supply voltage and other voltages are so scaled.
Constant-voltage scaling - The voltages are not scaled and, in some
cases, dimensions associated with voltage are not scaled.

Full Scaling (Constant Field Scaling)
In this method the device dimensions (both horizontal and vertical) are
scaled down by 1/S, where S is the scaling Iactor. In order to keep the
electric Iield constant within the device, the voltages have to be scaled also
by 1/S such that the ratio between voltage and distance (which represents
the electric Iield) remain constant. The threshold voltage is also scaled down
by the same Iactor as the voltage to preserve the Iunctionality oI the circuits
and the noise margins relative to one another. As a result oI this type oI
scaling the currents will be reduced and hence the total power per transistor
(PIxV) will also be reduced, however the power density will remain
constant since the number oI transistors per unit area will increase. This
means that the total chip power will remain constant iI the chip size remains
the same (this usually the case).
















W CaLe
L
Lox
x[
@e Lable below summarlzes ow eac devlce parameLer scales wlL S (S1)

arameLer 8efore scallng AfLer scallng
Cannel lengL L L/S
Cannel wldL W W/S
Cxlde Llckness Lox Lox/S
S/u [uncLlon depL x[ x[/S
ower Supply vuu vuu/S
@resold volLage
v
@C
v
@C
/S
uoplng uenslLy
n
A
n
u
n
A
*S and n
u
*S
Cxlde CapaclLance Cox S*Cox
uraln CurrenL
l
uS
l
uS
/S
ower/@ranslsLor /S
2

ower uenslLy/cm
2


Constant Voltage Scaling

In this method the device dimensions (both horizontal and vertical are scaled
by S, however, the operating voltages remain constant. This means that the electric
Iields within the device will increase (Iiled Voltage/distance). The threshold
voltages remain constant while the power per transistor will increase by S. The
power density per unit area will increase by S
3
! This means that Ior the same chip
area, the power chip power will increase by S
3
. This makes constant-voltage-
scaling (CVS) very impractical. Also, the device doping has to be increased more
aggressively (by S
2
) than the constant-Iield scaling to prevent channel punch-
through. Channel punch-through occurs when the Source and Drain Depletion
regions touches one another. By increasing the doping by S
2
, the depletion region
thickness is reduced by S (the same ratio as the channel length). However, there is
a limit Ior how much the doping can be increased (the solid solubility limit oI the
dopant in Silicon). Again, this makes the CVS impractical in most cases.

The Iollowing table summarizes the changes in key device parameters under
constant-voltage scaling:

arameLer 8efore scallng AfLer scallng
Cannel lengL L L/S
Cannel wldL W W/S
Cxlde Llckness Lox Lox/S
S/u [uncLlon depL x[ x[/S
ower Supply vuu vuu
@resold volLage
v
@C
v
@C

uoplng uenslLy
n
A
n
u
n
A
* S
2
and n
u
* S
2

Cxlde CapaclLance Cox S*Cox
uraln CurrenL
l
uS
l
uS
* S
ower/@ranslsLor *S
ower ueslLy/cm
2
* S
3

In almost all cases, the scaling is a combination oI constant-Iield scaling and
constant-voltage scaling, such that the number oI devices is increased and the total
power/chip does not increase much.

Short Channel Effects
As the channel length L is reduced to increase both the operation speed and the
number oI components per chip, the so-called short-channel eIIects arise.
The short-channel eIIects are attributed to two physical phenomena:
1. The limitation imposed on electron driIt characteristics in the channel,
2. The modiIication oI the threshold voltage due to the
shortening channel length.

Velocity Saturation and Surface Mobility Degradation
DriIt velocity vd Ior channel electrons is proportional to electric Iield along
channel Ior electric Iields along the channel oI 10`5 V/cm (as occur as becomes
small with JDD Iixed), vd saturates and becomes a constant vd(SAT) 10`7 cm/s.
This reduces ID(SAT) which no longer depends quadratically on JGS.

vd(SA1) unE(SA1)
unJD(SA1)/L
JD(SA1) L vd(SA1)/ un

Hence,
ID(SA1) ID(JDSJDSA1)
unCox(W/L)(JCS-J1) JDSA1-JDSA12/2]

vd(SA1) CoxW(JCS-J1 -JDSA1/2)


ThereIore, the drain current is linearly dependent on JGS when Iully velocity
saturated.

The vertical Iield (Ex) eIIects cause nn to decline represented by eIIective surIace
mobility nn(eff).
Empirical Iormulas Ior nn(eff) use parameters O and p.





Channel Depletion Region Charge Reduction
OIten viewed as the short channel eIIect
At the source and drain ends oI the channel, channel depletion region charge is
actually depletion charge Ior the source and drain region charge is actually
depletion charge Ior the source and drain.
For L large, attributing this charge to the channel results in small
errors
But Ior short-channel devices, the proportion oI the depletion
charge tied to the source and drain becomes large.

The reduction in charge is represented by the change oI the channel depletion
region cross-section Irom a rectangle oI length L and depth xdm to a trapezoid with
lengths L and L-ALS- ALD and depth xdm. This trapezoid is equivalent to a
rectangle with length :



Thus, the channel charge per unit area is reduced by the Iactor:

Next, need ALS and ALD in terms oI the source and drain junction depths and
depletion region junction depth using more geometric arguments. Once this is
done, the resulting reduction in threshold voltage JT due to the short channel eIIect
can be written as:







For 5 n, eIIect is negligible. But at 0.5 n, JT0 reduced to 0.43 Irom 0.76 volts
(AJT00.33V).





arrow Channel Effects

W is on the same order oI the maximum depletion region thickness xdm.
The channel depletion region spreads out under the polysilicon at its rises over the
thick oxide. Thus, there is extra charge in the depletion region.
The increase in JT0 due to this extra charge is


k is an empirical parameter dependent upon the assumed added charge cross-
section. This increase oI JT0 may oIIset much oI the short channel eIIect which
is subtracted Irom JT0.






Other Limitations Imposed by Small Geometry Effects
Subthreshold Condition
The potential barrier that prevents channel Iormation is actually controlled by
both the gate voltage JGS and the drain voltage JDS.
JDS lowers this potential, an eIIect known as DIBL (Drain-Induced Barrier
Lowering).
II the barrier is lowered suIIiciently by JGS and JDS, then there is channel
Iormation Ior JGS JT0.
Subthreshold current is the result.
Upward curvature oI the ID versus JGS curve Ior JGS JT with JDS= 0.


!unch-Through
Merging oI depletion regions oI the source and drain.
Carriers injected by the source into the depletion region are swept by the strong
Iield to the drain.
With the deep depletion, a large current under limited control oI JGS and JSB
results.
Thus, normal operation of devices in punch-through not feasible. Might cause
permanent damage to transistors by localized melting oI material.



Thinning of 9ox

As oxide becomes thin, localized sites oI nonuniIorm oxide growth (pinholes) can
occur, and can cause electrical shorts between the gate and substrate.

The dielectric strength oI the thin oxide may permit oxide breakdown due to
application oI an electric Iield in excess oI breakdown Iield. May cause
permanent damage due to current Ilow through the oxide.
ot Electron Effects
High electric Iields in both the channel and pinch-oII region Ior short channel
lengths occur Ior small L.

Particularly apparent in the pinch-oII region where voltage JDS - JD(SA1) large
with L - Leff small causes very high Iields.

High electric Iields accelerate electrons which have suIIicient energy with the
accompanying vertical Iield to be injected into the oxide and are trapped in deIect
sites or contribute to interIace states.

These are called hot electrons.

#esulting trapped charge increases J1 and otherwise aIIects transconductance,
reducing the drain current. Since these eIIects are concentrated at the drain end oI
the channel, the eIIects produce asymmetry in the I-J characteristics.

EIIect Iurther aggravated by impact ionization.