A MAJOR PROJECT SYNOPSIS ON

DESIGN

AND SIMULATION OF UART USING VERILOG

Synopsis submitted on Design and simulation of UART using verilog Fulfilled as a part of curriculum in Sem VII/Yr. IV of Bachelor of Engineering (Electronics and Communication) for RAJIV GANDHI PROUDYOGIKI VISHWAVIDYALAYA, BHOPAL, SESSION-201112
Guided by: Prof. Shubha Duwasha Dept. of Elec. & Comm. Engg. IES IPS Academy Indore Submitted By: Akshay Barkiya (0808EC081008) Amrut Moghe (0808EC081012) Ankush Khandelwal (0808EC081018) Nitin Monas (0808EC081064)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

INSTITUTE OF ENGINEERING & SCIENCE, IPS ACADEMY INDORE (M.P)-452012

INSTITUTE OF ENGINEERING & SCIENCE, IPS ACADEMY INDORE (M.P) Department of Electronics & Communication Engineering

CERTIFICATE
This is to certify that the synopsis entitled Design And Simulation Of UART Using Verilog submitted to the Rajiv Gandhi Vishwavidyalaya, Bhopal, by Akshay Barkiya (0808EC081018),Amrut Moghe (0808EC081012), Ankush Khnadelwal (0808EC081018) Nitin Monas(0808EC081064) during the academic year 2011-2012, is a record of their own work and is accepted as a partial fulfillment of part of curriculum in Sem VII/Yr. IV Bachelor of Engineering (Electronics and Communication), Major Project.

(Prof. Shubha Duwasha) Project Guide

(Prof. Rupesh Dubey) HOD EC

TABLE OF CONTENTS
List of figures List of Tables Abstract CHAPTER 1CHAPTER 22.1 Sub Section 2.2 Sub Section CHAPTER 33.1 Sub Section 3.2 Sub Section CHAPTER 41 3 6 8 9 10 10 11 12 13 13 14 15 16 CHAPTER 517 17 20 CHAPTER 6CHAPTER 740 52 52 53

CHAPTER 8-

54

LIST OF FIGURES
S. No. Fig. 1.1 Fig. 2.1 Content Block Diagram of Transmitter Circuit Diagram Page No. 07 15

LIST OF TABLES
S. No. Table 1.1 Table 2.1 Content Table of Comparison of Technology Table of Specifications Page No. 09 16

R EFERENCES BOOKS:
[1]

G. Eason, B. Noble, and I. N. Sneddon, On certain integrals of Lipschitz-Hankel type involving products of Bessel functions, Phil. Trans. Roy. Soc. London, vol. A247, pp. 529551, Apr. 1955. J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2. Clarendon, 1892, pp. 68-73. Oxford:

[2]

[3]

I. S. Jacobs and C. P. Bean, Fine particles, thin films and exchange anisotropy, in Magnetism, vol. III, G. T. Rado and H. Suhl, Eds. New York: Academic, 1963, pp. 271-350.

RESEARCH PAPERS:
[4]

T. L. Gilbert, Formulation, Foundations and Applications of the Phenomenological Theory of Ferromagnetism, Ph.D. dissertation, Illinois Inst. Tech., Chicago, IL, 1956. S. O. Demokritov and V. E. Demidov, Micro-Brillouin light scattering spectroscopy of magnetic nanostructures, IEEE Trans. Magn., p.407, 2009.

[5]

[6] C. J. Kaufman, Rocky Mountain Research Laboratories, Boulder, CO, private communication, 2004.
[7]

Y. Yorozu, M. Hirano, K. Oka, and Y. Tagawa, Electron spectroscopy studies on magnetooptical media and plastic substrate interface, IEEE Transl. J. Magn. Jpn., vol. 2, pp. 740741, August 1987 [Dig. 9th Annual Conf. Magn. Jpn., p. 301, 1982]. M. Young, The Technical Writers Handbook. Mill Valley, CA: University Science, 1989.

[8]

WEBLINKS:
[9]

www.cesca.centers.vt.edu/research/papers/Park/06SECON.pdf

Abstract
UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core part. UART includes three kernel modules which are the baud rate generator, receiver and transmitter. The UART implemented with VHDL language can be integrated into the FPGA to achieve compact, stable and reliable data transmission. It's significant for the design of SOC. The simulation results with Quartus II are completely consistent with the UART protocol .

FUNCTIONAL SPECIFICATIONS Introduction:

UART is a device that has the capability to both receive and transmit serial data. UART exchanges text data in an American Standard Code for Information Interchange (ASCII) format in which each alphabetical character is encoded by 7 bits and transmitted as 8 data bits. For transmission the UART protocol wraps this 8 bit subword with a start bit in the least significant bit (LSB) and a stop bit in the most significant bit (MSB) resulting in a 10 bit word format.

start

data 0

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

Stop

Basic Concept:
UART transmitter controls transmission by fetching a data word in parallel format and directing the UART to transmit it in a serial format. Likewise, the Receiver must detect transmission, receive the data in serial format, strip of the start and stop bits, and store the data word in a parallel format.

Since the UART is asynchronous in working, the receiver does not know when the data will come, so receiver generate local clock in order to synchronize to transmitter whenever start bit is received. Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. The transmitter and receiver agree on timing parameters in advance and special bits are added to each word which is used to synchronize the sending and receiving units. When a word is given to the UART for Asynchronous transmission, a bit called the Start Bit is added to the beginning of each word that is to be transmitted. The Star Bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter. After the Start Bit, the individual bits of the word of data are sent, with the Least Significant Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly the same amount of time as all of the other bits, and the receiver looks at the wire at approximately halfway through the period assigned to each bit to determine if the bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the receiver will examine the signal to determine if it is a 1 or a 0 after one second has passed, then it will wait two seconds and then examine the value of the next bit, and so on. Then at least one Stop Bit is sent by the transmitter. Because asynchronous data is self synchronous, if there is no data to transmit, the transmission line can be idle .

Serial Connection :
Serial Port used for UART is RS-232. It is a nine pin connector with each pin assigned with different functionality.

Approach:
We approached the given problem statement by implementing the UART receiver and transmitter independently. First we tried to implement the UART transmitter due to its less complexity in working and implementation. We used 9600 BAUD rate for transmission of serial data and divided the system clock accordingly. Then we started to implement the UART receiver. We learned the concept of clock synchronization by taking the clock many times higher that the transmitting rate. For this we generated clock which is 8 times the transmitter BAUD rate to minimize the distortions in the incoming data. We followed the Finite State Machine (FSM) approach to code both UART transmitter and receiver.

System diagram:

Diagram no. 1.1:-System diagram The above figure shows the overall working of the UART and the HyperTerminal. UART as transmitter takes 8 bit data from the switches and then transmits it bitwise through the RS-232 port and is displayed on the HyperTerminal of target machine. The load switch is used to load the transmit register of the UART and the shift switch is used to shift the data out from the shift register of the UART. UART as a receiver accepts the 8 bit data word from the HyperTerminal through the RS-232 port and displays it on the LEDs. The clock used by the UART receiver is 8 times the clock of the transmitter.

Software Used: Xilinx ISE:

Xilinx ISE[1] is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer to synthesize("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. 1:

Functional Block Diagram :

There are two functional parts in UART one is transmitter and another is receiver.the block diagram of transmitter and receiver are as follows.

Transmitter:

Diagram no. 2.1: block diagram of transmitter

Receiver :

Diagram no. 2.2: Block diagram of receiver

WORKING:

Transmitter:
The working of transmitter is explained with the help of FSM of transmitter . A finite-state machine (FSM) or finite-state automaton (plural: automata), or simply a state machine, is a mathematical model used to design computer programs anddigital logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one state at a time; the state it is in at any given time is called the current state. It can change from one state to another when initiated by a triggering event or condition, this is called a transition. A particular FSM is defined by a list of the possible states it can transition to from each state, and the triggering condition for each transition.

Diagram no.3.1:UART Transmitter FSM

Receiver : The working of receiver of UART is explained with help of flow diagram

RTL SCHEMATIC :

Transmitter :

Receiver :