B.V.V.SATYANARAYANA* et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 10, Issue No.

2, 266 - 269

FPGA Implementation of QAM Transmitter and Receiver Architectures for Wimax Applications
B.V.V.SATYANARAYANA*, A.PRAVIN # Department of ECE, BVC Engineering College Odalarevu, AP, India Email:*vvs403@yahoo.com & #akula.pravin@gmail.com

ABSTRACT
Wi-max is emerging a promising technology to provide high speed broadband connectivity to the mobile phone using latest modulation and multiplexing techniques. Wi-max mainly used QAM modulation technique due to its spectrum efficiency and several other added advantages. In such Wi-max communication systems, synchronization which consists of both carrier and symbol level is the most challenging task. There have been several researchers paying attention to solve synchronization problem in particular, hence build a whole communication system. The FPGA technology has been playing a considerable role in portable and mobile communication. This is due to the features of flexibility, accuracy and configurability in designing and implementation. This project presents a complete design for a 16-QAM transmitter and receiver based on VHDL. The implemented system can be used in typical Wi-max system and any other QAM based communication systems. The carrier synchronization and timing synchronization both issues are covered in the implementation. The transmitter of QAM consists of symbol mapper, NCO and modulator blocks. The NCO is used for carrier generation. The receiver of QAM consists of NCO, carrier synchronization block, time synchronization block, symbol demapper and clock managing unit. All blocks will be realized in VHDL and will be aimed to with generic feature so that the designs are scalable for different bit sizes. Modelsim Xilinx edition (MXE) will be used for simulation and functional verification. Xilinx ISE will be used for synthesis, P&R and bit file generation. Xilinx FPGA board will be used for testing and demonstration of the implemented system. KEYWORDS: FGPA design, Carrier Synchronization, Symbol Recovery, 16-QAM Modulation, WiMax, CORDIC.

I. INTRODUCTION

The development of mobile and portable communications requires not only high performance of hardware systems but also affectivity and flexibility in design and implementation. In such situation, silicon technology is one of the best choices which allow us to produce high execution, high integrated density and dedicated purpose integrated circuits (IC). However, silicon s-olution is not sufficient for incessantly developing wireless communication at the moment and in the future. Fortunately FPGA and ASIC technology has been merging as a suitable selection for the next communication systems design. With flexibility in design and precision in timing control, FPGA makes it easier and more accurate in simulating, testing, validating and implementing components. In communication, synchronization which consists of both carrier and symbol level is the most challenging task. There have been several researchers paying attention to solve synchronization problem in particular, hence build a whole communication system. The new Wimax standards demand higher bandwidth signals being offered between mobile communication units. There is tremendous research going on for development of related algorithms. Neither ASIC nor processor based solutions are suitable for experimenting such algorithms. The FPGA implemented QAM communication system is test bench for any Wimax related algorithms.

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ISSN: 2230-7818

In this paper, we present a diagram of a complete 16-QAM Transmitter and receiver and the implementing results based on Xilinx Spartan -2E FPGA Kit as well. The modulator and the demodulator are performed in the same FPGA kit. Both carrier synchronization and symbol

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synchronization are taken into account in this model using fast computing tool (CORDIC) .The remaining of this paper presented as QAM Transmitter, QAM Receiver, implemented results and conclusions. II. QUADRATURE AMPLITUDE MODULATION

Quadrature amplitude modulation (QAM) is a modulation scheme in which two sinusoidal carriers, one exactly 90 degrees out of phase with respect to the other, are used to transmit data over a given physical channel. Because the orthogonal carriers occupy the same frequency band and differ by a 90 degree phase shift, each can be modulated independently, transmitted over the same frequency band, and separated by demodulation at the receiver. For a given available bandwidth, QAM enables data transmission at twice the rate of standard pulse amplitude modulation (PAM) without any degradation in the bit error rate (BER). QAM and its derivatives are used in both mobile radio and satellite communication systems. These two carrier waves represent the in-phase (I) and Quadrature-phase (Q) components of our signal. Individually each of these signals can be represented as:

Note that the I and Q components are represented as cosine and sine because the two signals are 90 degrees out of phase with one another. Using the two identities above and the following trigonometric identity

cos ( + ) = cos()cos() sin()sin(), Rewrite a carrier wave A cos (2fct + ) as

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I = A cos () and Q = A sin ().

B.V.V.SATYANARAYANA* et al. / (IJAEST) INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING SCIENCES AND TECHNOLOGIES Vol No. 10, Issue No. 2, 266 - 269

III. QAM TRANSMITTER

A cos (2fct + ) = I cos (2fct) Q sin(2fct). The sent signal can be expressed in the form:

Where vc[n] and vs[n] are the voltages applied in response to the nth symbol to the cosine and sine waves respectively.

The transmitter of QAM consists of Signal source, symbol mapper, NCO, modulator blocks and adder. The NCO is used for carrier generation.. In this paper, we use random data source to capture all possibilities of data statistic. However, that can be from file without any trouble. Two four level random data sequences are generated corresponding to I and Q signal of 16-QAM at the rate of 4 clock periods. These signals then go to the mapping block. A symbol mapper takes symbols as inputs and maps them to appropriate constellation points as dictated by the modulation method specified. This process generates I and Q values.

Fig. Representation of QAM Signal (i) QAM-Constellation diagram

The constellation diagrams show the different positions for the states within different forms of QAM, quadrature amplitude modulation. As the order of the modulation increases, so does the number of points on the QAM constellation diagram.

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ISSN: 2230-7818

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The numerically controlled oscillator (NCO) accurately generates the in-phase and Quadrature carriers used by a QAM modulator. The carrier frequency of each sinusoid can be set to any precision by defining the phase increment input to the NCO.I and Q modulated signals are combined in the adder and produces the composite signal. This composite signal is transmitted to the receiver. The Numerically controlled oscillator is designed using CORDIC algorithm, implementation is shown in the below figure. All the blocks are connected with common clock and reset signals. The delta phase value decides the phase increment for each clock pulse. Hence decides the resulting signal frequency. The Frequency modulating instantaneous value is added to the delta phase value which causes instantaneous change in frequency. Due to the digital nature of the modulator only at each clock tick the modulating signal value shall affect the resulting frequency. If the modulating signal is analog then an Analog Digital converter must be used to digitize the modulating signal which can be used in DDFS.

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Fig .Block Diagram of QAM transmitter.

Fig. CORDIC Architecture.

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IV. QAM RECEIVER

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ISSN: 2230-7818

The receiver of QAM consists of NCO, carrier synchronization block, time synchronization block, symbol demapper and clock managing unit. The numerically controlled oscillator (NCO) accurately generates the in-phase and Quadrature carriers. These carriers are multiplied with the received signal so as to separate I and Q modulated signals. An adaptive equalizer is an equalizer that automatically adapts to time-varying properties of the communication channel. It is frequently used with coherent modulations such as phase shift keying, mitigating the effects of multipath propagation and Doppler spreading. A symbol demapper performs the reverse operation of the mapper. It takes I and Q values and generates the corresponding data symbols. If the signal transmitted is the analog signal, we can use ADC to obtain the original transmitted signal. Carriers used at the receiver must be synchronized with the transmitter carriers. This synchronization is provided by the separate module called carrier recovery. The carrier recovery module is shown in the below figure.

Fig. Block Diagram of QAM Receiver.

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Simulated Result

The phase accumulator produces accumulated phase value for each clock pulse. In case if the DDFS is used for phase modulation then instantaneous phase modulating signal value is added to the phase output of phase accumulator. This resulting phase value is given to the four Look Up Tables. Each Look Up Table is configured to produce a specific waveform. The logic used to generate the Look Up Tables is discussed in the further sections. The outputs of the Look Up Tables are given to the input lines a 4 to 1 Multiplexer. This multiplexer connects one of the inputs to the output depending on the select lines. The output of Multiplexer consists the 8 amplitude bits which is the final output in case required modulation schemes are FM or PM. In case of Amplitude modulation, the output of Multiplexer is multiplied with instantaneous modulating signal. CORDIC engine is used for phase to amplitude conversion required for the generation of Cos and Sin functions. In three modulation schemes if modulating signal is analog in nature then an appropriate Analog to Digital converter is required to convert into 8 bit digital output. From the figure the basic blocks in DDFS can be identified as PIPO registers, adders, Look Up Tables, CORDIC engine and other combinational circuits. The following sections presents the implementation details and results obtained for all these blocks.

Fig. carrier Recovery.

After testing model on simulation, the simulation design is compiled to ISE file before generating the programming file, bit file. Figure shows the resources used in this model which just takes a small part in Xilinx Spartan-2E FPGA Kit.

Functional verification of QAM system can be done with ModelSim XE III 6.0d.

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V. RESULTS

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Technological View

VLSI Signal Processing, Vol 36, p 57-71,2004. [4] Joaquin Garcia, Rene Cumplido, On the design of an FPGA-Based OFDM modulator for IEEE 802.11a, Proceeding of ICEEE, September 7-9, 2005, Mexico. [5] John G. Proakis, Digital Communication, McGrawHill 1993. [6]VLSI for Wireless communication, Bosco Luen Pearson Education and VLSI series [7] http://www.xilinx.com

Package View of Implementation

VI.CONCLUSIONS

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VII.REFERENCES
ISSN: 2230-7818

A computationally efficient algorithm is developed for a low power and versatile ASIC design of QAM transmission system. Utilization of this algorithm in the development of mobile and portable communications requires not only high performance of hardware systems but also affectivity and flexibility in design and implementation. Simulation (ModelSim XE III 6.0d), synthesis (Xilinx ISE8.1i), implementation (Spartan 3e) and verification of design after implementation is successfully completed.

[1] 16 QAM transmitter and receiver design based on FPGA IEEE 2010, Xuan-thang Vu, Nguyen Anh Duc, Trinh Anh Vu [2] C. Dick, F.Harris, M.Rice, Synchoronization in Software Radios-Carrier and Timing Recovery Using FPGAs, Proceeding of 2000 IEEE Symposium on FieldProgrammable Custom Computing Machines. [3] C.Dick, F.Harris, M.Rice, FPGA Implementation of Carrier Synchronization for QAM Receivers, Journal of

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