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Chapter 1

Introduction of Digital Circuit

1.1 Digital Circuits: The term digital refers to fact that the signal is limited to only a few
possible values. In general, digits signal are represented by only two possible voltage on a wire-0 volts which is called binary 0 and 5 volts which is called binary 1.we some time called these value low/high.

Boolean Values:

0 /low/false 1/high/true

Boolean Variables can assume any one of 0 or 1 value at a time. NOT Inversion

AND

Logical AND

Logical OR operation. ExOR NAND NOR XNOR

OR Exclusive OR Complement of AND Complement of OR Complement of XOR

1.2

De Morgans Theorems:

NOT(A+B) = ( NOT A) . ( NOT B) The complement of the SUM (OR) of two boolean variables is equivalent to the PRODUCT ( AND)of the complements of the two variables. NOT(A.B) = ( NOT A) + ( NOT B) The complement of the PRODUCT (AND) of two boolean variables is equivalent to the SUM(OR) of the complements of the two variables .

1.3 Duality Principle :


If the dual of the expression is desired,we simply interchange OR and AND operators and replace 1s by 0s and 0s by 1s

3-input Combination block

1.4 Combinational Circuits:


Always gives the same output for a given set of Inputs Do not store any information (memory less). It is combination of gate and logic circuits. Present input state of output depends upon present input state.

Examples: adder, decoder, multiplexer (mux), shifter These are combined to form larger units such as ALU
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We will apply the knowledge of Boolean Algebra to realize these circuits and have example one by one.

1.4.1 Half Adder


Used for addition of two bits. The truth table summaries the outputs of the 1 bit addition based on values of x and y The two outputs are sum and carry As we see, the sum can be found using the XOR operation and the carry using the AND operation

1.4.2 Full Adder:


Used for addition of three bits. The two outputs are sum and carry as a function of three inputs. As we see, the sum can be found using the XOR operation of all three inputs and the carry using the AND operation of the same.

1.4.3 Binary adder:


Binary adder that produces the arithmetic sum of binary numbers It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain Note that the input carry C0 in the least significant position must be 0.

For example to add A= 1011 and B= 0011 subscript i: Input carry: Augend: 3 0 1 2 1 0 1 1 1 0 0 1 Ci Ai
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Addend:

Bi

-------------------------------Sum: 1 1 0 1 0 0 1 Si 1 Ci+1

Output carry:

1.4.4 Binary Subtractor


The subtraction A B can be done by taking the 2s complement of B and adding it to A because A B = A + ( B) It means if we use the inveters to make 1s complement of B (connecting each Bi to an inverter) and then add 1 to the least significant bit (by setting carry C0 to 1) of binary adder, then we can make a binary subtractor.

1.4.5 Decoder:
Is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines For example if the number of input is n=3 the number of output lines can be m=23 . It is also known as 1 of 8 because one output line is selected out of 8 available lines:

Decoder with enable line: Decoders usually have an enable line, If enable=0 , decoder is off. It means all output lines are zero If enable=1, decoder is on and depending on input, the corresponding output line is 1, all other lines are 0. The truth table is given below: E a2 a1 a0 D7 D6 D5 D4 D3 D2 D1 D0

----------------------------------------------------------0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 x x x 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 01

. ..

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1.4.6 Encoder:
Encoder is a digital circuit that performs the inverse operation of a decoder Generates a unique binary code from several input lines. Generally encoder produce 2bit, 3bit,or 4bit code. N bit encoder has 2^n input lines.

2-bit encoder: If one of the four input lines is active encoder produces the binary code corresponding to that line. If more than one of the input lines will be activated or all the output is undefined. We can consider dont care for these situations but in general we can solve this problem by using priority encoder.

1.4.7 Multiplexer:
It is a combinational circuit that selects binary information from one of the input lines and directs it to a single output line. Usually there are 2n input lines and n selection lines whose bit combinations determine which input line is selected. For example for 2-to-1 multiplexer if selection S is zero then I0 has the path to output and if S is one I1 has the path to output.

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2-to-1 multiplexer:

1.4.8 Demultiplexer:
Performs the reverse action which is performed by MUX. The 1-bit demultiplexer receives 1-bit data on a single input and re-directs it into one-out-of m = 2n 1 outputs selected by an n-bit number x. .

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1.4.9 Parity Generator:

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1.4.10 Magnitude Comparator:

Now let discuss the Sequential Circuits:

1.5

Sequential Circuits: These are those whose output depends upon the present

input and past output. Basic element latch and flip flop. Latch:to store one bit element. Eg: register and counters.

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. let us discuss one by one: Register:Group of Flip-Flop. Four bit register is shown below

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1.5.1 There are different type of registers: Serial in serial output Serial input parallel output Parallel input parallel output Parallel input serial output Shift register

Registers consist of a group of D-type latches or flip-flops which are clocked simultaneously to store a binary word set-up and hold times must be observed Shift registers allow data to be moved from one bit position to another

used for parallelserial conversion and some types of arthmetic operations now discussion on Counters:

1.5.2 Counters:
Combinations of register that count pulses. Counter is used to count the sequence of input pulse. Connect teo or more flip flops.

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Two types of counter: Asynchronous Synchronous

In Asynchronous clk is connected to the output of first flip flop. Faster in action and less reliable. In synchronous each flip flop have its own clock. Slower in action and more reliable.

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Chapter 2

Introduction of VLSI

VLSI
Very-large-scale integration:2.1 Very-large-scale integration (VLSI) 2.1 Very Large Scale Integration(VLSI) is the process of creating integrated circuits by combining thousand of transistors based circuits into a single chip. VLSI began in the 1970s .When complex semiconductor and communication technologies were being developed. The Microprocessor is a VLSI device. he term is no longer as common as it once was, as chips Have increased in complexity into the hundreds of millions of transistors. The first semiconductors chips held one transistor each. Subsequent advances added more and more transistors, and as a consequence, more individual function or system was integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitor, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as small-scale integration(SSI),Improvement in techniques led to device with hundreds of logic gates, known as large scale integration(LSI),i.e. system at least a thousand logic gates. Current technology has moved far past this mark and todays microprocessors have many millions of gates and hundreds of millions of individual transistors.

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2.2 VLSI Universal Board:

The universal VLSI board is designed for the various application to implementon programmable Devices.The flexibility is its main feature i.e. it can be used to program both CPLD and FPGA. Various section given on this board are 1. Power Supply Section. 2. JTAG Cable Section.

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3. Seven Segment Section. 4. LCD Section. 5. Input LED Section 6. Output Led Section.. 7. Oscillator . Power Supply Section The power supply section is on the right most side and behind the LCD section in the board having two power connector with power indicator LED. The main function of this section is to provide three voltages i.e. 5 Volt , 3.3 Volt and 2.5 Volt for various section. JTAG Cable Section The JTAG cable section is situated on left most side of the board having 9 serial connector pin .Through which the bit stream generated by operating system is supplied to programmable device.Serial connector is used for this purpose. Any fault in JTAG section will lead to error in programming the device. Seven Segment Section The seven segment section is situated right most of the board having current driving IC .The four seven segment is provided in this section for display. The driving pins of this section are internally connected to pre specified pins of programmable device. LCD Section The LCD section is situated near power supply section. LCD display function can be performed through the section. Veriac is provided to control the contrast. Jumper setting should be keep in mind for proper functioning .Short circuit the pins those situated on power supply section side through jumpers. The driving pins of this section is internally connected to pre specified pins of programmable device. Input LED Section The input LED section is provided to give digital input signal to programmable device .It gives provision of external input by removing jumpers. Dip switches are provided to change input Logic. Twenty four input LEDs are here to give input. The driving pins of this section is internally connected to pre specified pins of programmable device.
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Output Led Section The output LED section is provided to show digital output signal from programmable device .It gives provision of external output by removing jumpers. Sixteen output LEDs are here to show output. The driving pins of this section is internally connected to pre specified pins of programmable logic.. Oscillator 8 Mhz oscillator is provided to give clock to programmable device .The frequency of this section determines the time taken or any operation

2.3 Hardware used for VLSI Designing


CPLD FPGA

2.3.1 CPLD stands for Complex Programmable Logic Device. It is a programmable logic device with complexity between that of FPGAs and PALs, and architectural features from both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations.

2.3.2 Features in common with with PALs Non-volatile configuration memory. Unlike many FPGAs an external configuration ROM isnt required, and the CPLD can function immediately on system start-up. For all but the largest devices, routing constrains most logic blocks to have input and output signals connected to external pins (little opportunity for internal state storage or deeply layered logic). 2.3.3 Features in common with FPGAs: Large number of gates available. CPLDs typically have the equivalent of thousand to tens of thousand of logic gates, allowing implementation of moderately complicated data processing

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device. PALs typically have a few hundered gates equivalent at most, while FPGA typically range from tens of thousand to several millions. Some provisions for logic, more flexible than some of product expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly used functions such as integer arithmetic. The most noticeable difference between large CPLD and a small FPGA is the presence of onchip non-volatile memory in the CPLD. The differences in architectural approach become more apparent further from this intermediate region. This characteristic of non-volatility means that CPLDs are often used in modern digital design to perform boot loader functions before handling over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory. CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs and PALs. As FPGAs became more advanced the differences between the two devices types become blurred. This trend will continue until the two types are essentially indistinguishable. 2.3.4 Field programmable gate array: A field programmable gate array(FPGA) is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as And, or, not, Xor or more complex combiunational functions such as decoder or simple maths functions. In most FPGAs, these programmable logic components also include memory elements, which may be simple flipflops or more comple blocks of memories. A hierarchy of programmable interconnects allow the logic blocks of an FPGA to be interconnect as needed by the system designer, somewhat like a one-chip programmable bread board. These logic blocks and interconnects can be programmed after the manufacturing process by the customer/designer so that FPGA can perform whatever logical function is needed. FPGAs are generally slower than their application specific integrated circuits (ASIC)

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Counterparts, cant handle as complex a design, and draw more power.

2.4 SOFTWARE DESCRIPTION


XILINX ISE 8.1i

Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Step 1: Start the Xilinx Project Navigator by using the desktop shortcut or by using Start->programs-> Xilinx ISE->Project Navigator. Step 2: In the project Navigator window go to FILE->New project Give a specific project name and project location.Then click next.

Step 3: select a particular device and device properties. For example the device properties for XC9572PC44-10C are:23

FOR CPLD DEVICE SETTING:

Product Category: Family: Device: Package: Speed:

All

xc9500CPLDs xc9572 PC84 -10

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Then click next. In next window, click on new source. A new source wizard window will appear on screen.Here select VHDL module and give a particular file name and click next.

Step 4:- Define the ports in this window and click next. Now press finish. Then click next-->next-->finish.

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Step 5: Generate the behavioral VHDL Code for the basic gates. Step5: Check syntax , and remove errors if present.Check syntax given below:

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Step6: Simulate the design using Modelsim. Highlight basicgates.vhd file in the sources in project window.To run the Functional

Simulation,Click on the symbol of FPGA device and then right click->Click on new source>click on test bench waveform->give file name->Select The modelsim window setting shown n

entity->Finish->Give inputs-> Click on simulate behavioral model->see the output. Step7: Synthesis the design using XST. Highlight basicgates.vhd file in the Sources in Project window.To run synthesis,right-click on

synthesis,and choose the run option,or double-click on Synthesize in the processes for Current Source window.Synthesis will run,and agreen check will appear next to synthesis when it is successfully completed. A yellow exclamation mark indicates an error was generated.Warnings are OK. If there are any errors,you can view the error through the console window on to the next step Step8: Write User Constraint file wherein the FPGA or CPLD pins are locked as per the otherwise continue

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Manual.UCF window shown on next page.

UCF window

Step9: Make the setting of JTAG clock .Go to Generate Programming file right click On that and then select properties.

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Then go to startup option and select JTAG clock.

Step10: Run the Xilinx implementation Tools. Once synthesis is complete, you can place and route your design to fit into a Xilinx device, and you can also get some post place-and-route timing information about the design. This procedure runs you through the basic flow for implementation. Right-click on Implement Design, and choose the Run option,or double left-click on Implementation Design. NOW click on plus sign in front of generate programming file and right click on configure device and click run.

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PROGRAMMING THROUGH PARALLEL PORT


An IMPACT window will appear on screen. Select the first option AND CLICK FINISH

Step11: Assign the configuration file (jed file) and Right click on XILINX device and program the device.

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Chapter 3
Introduction of VHDL
3.1 Hardware description language
In electronics, a hardware description language or HDL is any language from a class of computer languages and/or programming languages for formal description of electronic circuits. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. The two most widely-used and well-supported HDL varieties used in industry are: * VHDL * Verilog VHDL (VHSIC hardware description language) is a Hardware Description Language (HDL). This Hardware Description Language is a language used to describe a digital system, for example, a computer or a component of a computer. One may describe a digital system at several levels. For example, an HDL might describe the layout of the wires, resistors and transistors on an Integrated Circuit (IC) chip, i. e., the switch level. Or, it might describe the logical gates and flip flops in a digital system, i. e., the gate level.

WHAT IS VHDL

VHDL is one of the two major Hardware Description Languages (HDL) used by hardware designers in industry and academia. Verilog is the other one. The industry is currently split on which is better. Many feel that VHDL is easier to learn and use than Verilog. VHDL was made an IEEE Standard in 1987 and Verilog in 1985.

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VHDL allows a hardware designer to describe designs at a high level of abstraction such as at the architectural or behavioral level as well as the lower implementation levels (i. e. , gate and switch levels) leading to Very Large Scale Integration (VLSI) Integrated Circuits (IC) layouts and chip fabrication. A primary use of HDLs is the simulation of designs before the designer must commit to fabrication.

3.2 WHY USE VHDL

Digital systems are highly complex. At their most detailed level, they may consist of millions of elements, i.e., transistors or logic gates. Therefore, for large digital systems, gate-level design is dead. For many decades, logic schematics served as the lingua franca of logic design, but not any more. Today, hardware complexity has grown to such a degree that a schematic with logic gates is almost useless as it shows only a web of connectivity and not the functionality of design. Since the 1970s, Computer engineers and electrical engineers have moved toward hardware description languages (HDLs). The most prominent modern HDLs in industry are Verilog and VHDL. The VHDL language provides the digital designer with a means of describing a digital system at a wide range of levels of abstraction, and, at the same time, provides access to computer-aided design tools to aid in the design process at these levels. VHDL allows hardware designers to express their design with behavioral constructs, deterring the details of implementation to a later stage of design in the design. An abstract representation helps the designer explore architectural alternatives through simulations and to detect design bottlenecks before detailed design begins.

3.3 Basic Structure of a VHDL file


A digital system in VHDL consists of a design entity that can contain other entities that are then considered components of the top-level entity. Each entity is modeled by an entity
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declaration and an architecture body. One can consider the entity declaration as the interface to the outside world that defines the input and output signals, while the architecture body contains the description of the entity and is composed of interconnected entities, processes and components, all operating concurrently, as schematically shown in Figure below. In a typical design there will be many such entities connected together to perform the desired function.

A VHDL entity consisting of an interface (entity declaration) and a body (architectural description). VHDL uses reserved keywords that cannot be used as signal names or identifiers. Keywords and user-defined identifiers are case insensitive. Lines with comments start with two adjacent hyphens (--) and will be ignored by the compiler. VHDL also ignores line breaks and extra spaces. VHDL is a strongly typed language which implies that one has always to declare the type of every object that can have a value, such as signals, constants and variable. a. Entity Declaration The entity declaration defines the NAME of the entity and lists the input and output ports. The general form is as follows, entity NAME_OF_ENTITY is [ generic generic_declarations);] port (signal_names: mode type;

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signal_names: mode type); end [NAME_OF_ENTITY] ;

An entity always starts with the keyword entity, followed by its name and the keyword is. Next are the port declarations using the keyword port. An entity declaration always ends with the keyword end, optionally [] followed by the name of the entity.

b.

Architecture body

The architecture body specifies how the circuit operates and how it is implemented. The architecture body looks as follows, architecture architecture_name of NAME_OF_ENTITY is -- Declarations -- components declarations -- signal declarations -- constant declarations -- function declarations -- procedure declarations -- type declarations begin -- Statements; end architecture_name; c. Library and Packages: library and use keywords
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A library can be considered as a place where the compiler stores information about a design project. A VHDL package is a file or module that contains declarations of commonly used objects, data type, component declarations, signal, procedures and functions that can be shared among different VHDL models.

3.4 DESIGN FLOW: We start the design by writing the VHDL code, which is saved in a file
with the extension .vhd and the same name as its ENTITYs name. the first step in the synthesis process is compilation. Compilation is the conversion of high level VHDL language, which describes the circuit at the Register Transfer level(RTL), into a netlist at gate level. The second step is optimization, which is performed on the gate level netlist for speed or area. At this stage, the design can be simulated. Finally a place and route(filter) software will generate the physical layout for a PLD/FGPA chip or will generate the masks for an ASIC.

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Chapter 4

Lexical Elements of VHDL


The Elements in VHDL are:
4.1 Identifiers Identifiers are user-defined words used to name objects in VHDL models. We have seen examples of identifiers for input and output signals as well as the name of a design entity and architecture body. When choosing an identifier one needs to follow these basic rules: May contain only alpha-numeric characters (A to Z, a to z, 0-9) and the underscore (_) character The first character must be a letter and the last one cannot be an underscore. An identifier cannot include two consecutive underscores. An identifier is case insensitive (ex. And2 and AND2 or and2 refer to the same object). An identifier can be of any length. Examples of valid identifiers are: X10, x_10, My_gate1. Some invalid identifiers are: _X10, my_gate@input, gate-input. 4.2 Keywords (Reserved words) Certain identifiers are used by the system as keywords for special use such as specific constructs. These keywords cannot be used as identifiers for signals or objects we define. We have seen several of these reserved words already such as in, out, or, and, port, map, end, etc.

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4.3 Data Objects: Signals, Variables and Constant 4..3.1 Constant A constant can have a single value of a given type and cannot be changed during the simulation. A constant is declared as follows, constant list_of_name_of_constant: type [ := initial value]; 4.3.2 Variable A variable can have a single value, as with a constant, but a variable can be updated using a variable assignment statement. Variables must be declared inside a process (and are local to the process). The variable declaration is as follows: variable list_of_variable_names: type [ := initial value] ;

4.3.3 Signal Signals are declared outside the process using the following statement: signal list_of_signal_names: type [ := initial value] ; 4.4 Data types Each data object has a type associated with it. The type defines the set of values that the object can have and the set of operations that are allowed on it. The notion of type is key to VHDL since it is a strongly typed language that requires each object to be of a certain type. In general one is not allowed to assign a value of one type to an object of another data type (e.g. assigning an integer to a bit type is not allowed). 4.4.1 Data Types defined in the Standard Package VHDL has several predefined types in the standard package as shown in the table below. To use this package one has to include the following clause: library std, work;

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use std.standard.all; example:bit,integer,etc. 4.4.2 User-defined Types One can introduce new types by using the type declaration, which names the type and specifies its value range. The syntax is type identifier is type_definition; Here are a few examples of type definitions, Integer types type small_int is range 0 to 1024; type my_word_length is range 31 downto 0; subtype data_word is my_word_length range 7 downto 0;

4.4.3 Enumerated Types An enumerated type consists of lists of character literals or identifiers. The enumerated type can be very handy when writing models at an abstract level. The syntax for an enumerated type is, type type_name is (identifier list or character literal); Here are some examples, type my_3values is (0, 1, Z); type PC_OPER is (load, store, add, sub, div, mult, shiftl, shiftr); type hex_digit is (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F); type state_type is (S0, S1, S2, S3);

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4.5 Attributes: Attributes are used to return various types of information about a signal, variable or type.Attributes consist of a quote mark () followed by the name of the attribute. 4.5(1) Signal attributes The following table gives several signal attributes.

Attribute signal_nameevent

Function returns the Boolean value True if an event on the signal occurred, otherwise gives a False

signal_nameactive

returns the Boolean value True there has been a transaction (assignment) on the signal, otherwise gives a False

signal_nametransaction

returns a signal of the type bit that toggles (0 to 1 or 1 to 0) every time there is a transaction on the signal.

signal_namelast_event

returns the time interval since the last event on the signal

signal_namelast_active

returns the time interval since the last transaction on the signal

signal_namelast_value

gives the value of the signal before the last event occurred on the signal

signal_namedelayed(T)

gives a signal that is the delayed version (by time T) of the original one. [T is optional, default T=0]

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signal_namestable(T)

returns a Boolean value, True, if no event has occurred on the signal during the interval T, otherwise returns a False. [T is optional, default T=0]

signal_namequiet(T)

returns a Boolean value, True, if no transaction has occurred on the signal during the interval T, otherwise returns a False. [T is optional, default T=0]

4.5.2 Scalar attributes Several attributes of a scalar type, scalar-type, are supported. The following table shows some of these attributes.

Attribute scalar_typeleft

Value returns the first or leftmost value of scalar-type in its defined range

scalar_typeright

returns the last or rightmost value of scalar-type in its defined range

scalar_typelow

returns the lowest value of scalar-type in its defined range

scalar_typehigh

returns the greatest value of scalar-type in its defined range

scalar_typeascending

True if T is an ascending range, otherwise False

scalar_typevalue(s)

returns the value in T that is represented by s (s stands for string value).

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4.6 Operators:
VHDL supports different classes of operators that operate on signals, variables and constants. The different classes of operators are summarized below.

Class 1. operators 2. operators 3. Shift operators Sll Srl sla sra rol Ror Relational = /= < <= > >= Logical And Or nand nor xor Xnor

4.Addition operators 5. Unary operators

&

6. Multiplying op.

mod

rem

7. op.

Miscellaneous

**

abs

not

4.6.1 Logic operators The logic operators (and, or, nand, nor, xor and xnor) are used to define Boolean logic expression or to perform bit-per-bit operations on arrays of bits. They give a result of the same type as the operand (Bit or Boolean). These operators can be applied to signals, variables and constants. 4.6.2 Relational operators

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The relational operators test the relative values of two scalar types and give as result a Boolean output of TRUE or FALSE.

Operator = /= <

Description Equality Inequality Smaller than

Operand Types any type any type scalar or discrete array types

Result Type Boolean Boolean Boolean

<=

Smaller than or equal

scalar or discrete array types

Boolean

>

Greater than

scalar or discrete array types

Boolean

4.6.3 Shift operators These operators perform a bit-wise shift or rotate operation on a one-dimensional array of elements of the type bit (or std_logic) or Boolean.

Operato r Sll

Description

Operand Type

Result Type

Shift left logical (fill right vacated bits with the 0)

Left:

Any

one-

Same as left type

dimensional array type with elements of type bit or Boolean; Right:

integer Srl Shift right logical (fill left vacated bits with 0) same as above Same as left type

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Sla

Shift left arithmetic (fill right vacated bits with rightmost bit)

same as above

Same as left type

Sra

Shift right arithmetic (fill left vacated bits with

same as above

Same as left type

leftmost bit) Rol Rotate left (circular) same as above Same as left type Ror Rotate right (circular) same as above Same as left type

The operand is on the left of the operator and the number (integer) of shifts is on the right side of the operator. As an example, variable NUM1 NUM1 srl 2; will result in the number 00100101. When a negative integer is given, the opposite action occurs, i.e. a shift to the left will be a shift to the right. As an example NUM1 srl 2 would be equivalent to NUM1 sll 2 and give the result 01011000. Other examples of shift operations are for the bit_vector A = 101001 :bit_vector := 10010110;

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variable A: bit_vector :=101001; A sll 2 results in A srl 2 001010 A sla 2 100111 A sra 2 111010 A rol 2 100110 A ror 2 011010 4.6.4 Addition operators The addition operators are used to perform arithmetic operation (addition and subtraction) on operands of any numeric type. The concatenation (&) operator is used to concatenate two vectors together to make a longer one. In order to use these operators one has to specify the ieee.std_logic_unsigned.all or std_logic_arith package package in addition to the ieee.std_logic_1164 package. results in results in results in results in 100100

results in

Operato r +

Description

Left Operand Type

Right Operand Type Same operand as left

Result Type

Addition

Numeric type

Same type

Subtraction

Numeric type

Same operand

as

left

Same type

&

Concatenation

Array element type

or

Same operand

as

left

Same array type

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4.6.5 Unary operators The unary operators + and - are used to specify the sign of a numeric type.

Operator +

Description Identity

Operand Type Any numeric type

Result Type Same type

Negation

Any numeric type

Same type

4.6.6 Multiplying operators The multiplying operators are used to perform mathematical functions on numeric types (integer or floating point).

Operator

Description

Left Operand Type

Right Operand Type

Result Type

Multiplication

Any integer or floating point

Same type

Same type

Any physical type Any integer or real type

Integer or real type Any physical type

Same as left

Same as right

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Division

Any integer or floating point

Any integer or floating point

Same type

Any physical type Any physical type Mod Modulus Any type Rem Remainder Any type integer integer

Any integer or real t ype Same type

Same as left

Integer

Same type

Same type

4.6.7 Miscellaneous operators These are the absolute value and exponentation operators that can be applied to numeric types. The logical negation (not) results in the inverse polarity but the same type.

Operator

Description

Left Operand Type

Right Operand Type

Result Type

**

Exponentiation

Integer type

Integer type

Same as left

Floating point

Integer type

Same as left

Abs

Absolute value

Any numeric type

Same type

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Not

Logical negation

Any

bit

or

Same type

Boolean type

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Chapter 5

Statements
5.1 Behavioral Modeling: Sequential Statements
5.1.1 Process :A process statement is the main construct in behavioral modeling that allows you to use sequential statements to describe the behavior of a system over time. The syntax for a process statement is [process_label:] process [ (sensitivity_list) ] [is] [ process_declarations] begin list of sequential statements such as: signal assignments variable assignments case statement if statement procedure call wait statement end process [process_label]; 5.1.2 If Statements:The if statement executes a sequence of statements whose sequence depends on one or more conditions. The syntax is as follows: if condition then
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sequential statements [elsif condition then sequential statements ] [else sequential statements ] end if; Each condition is a Boolean expression. The if statement is performed by checking each condition in the order they are presented until a true is found. Nesting of if statements is allowed. 5.1.3 Case statements:The case statement executes one of several sequences of statements, based on the value of a single expression. The syntax is as follows, case expression is when choices => sequential statements when choices => sequential statements -- branches are allowed [ when others => sequential statements ] end case; 5.1.4 Loop statements:A loop statement is used to repeatedly execute a sequence of sequential statements. The syntax for a loop is as follows: [ loop_label :]iteration_scheme loop

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sequential statements [next [label] [when condition]; [exit [label] [when condition]; end loop [loop_label]; 5.1.5 While-Loop statement:The while loop evaluates a Boolean iteration condition. When the condition is TRUE, the loop repeats, otherwise the loop is skipped and the execution will halt. The syntax for the whileloop is as follows, while condition loop sequential statements end loop[ loop_label ]; The condition of the loop is tested before each iteration, including the first iteration. If it is false, the loop is terminated. 5.1.6 For-Loop statement: The for-loop uses an integer iteration scheme that determines the number of iterations. The syntax is as follows, for identifier in range loop sequential statements end loop[ loop_label ]; 5.1.7 Next and Exit Statement:The next statement skips execution to the next iteration of a loop statement and proceeds with the next iteration. The syntax is next [label] [when condition]; The when keyword is optional and will execute the next statement when its condition evaluates to the Boolean value TRUE.
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The exit statement skips the rest of the statements, terminating the loop entirely, and continues with the next statement after the exited loop. The syntax is as follows: exit [label] [when condition]; The when keyword is optional and will execute the next statement when its condition evaluates to the Boolean value TRUE. Notice that the difference between the next and exit statement, is that the exit statement terminates the loop. 5.1.8 Wait statement:The wait statement will halt a process until an event occurs. There are several forms of the wait statement, wait until condition; wait for time expression; wait on signal; wait; A few examples :-wait until CLK=1; wait until CLK=0; wait until CLKevent and CLK=1; wait until not CLKstable and CLK=1; 5.1.9 Null statement:The null statement states that no action will occur. The syntax is as follows, null; It can be useful in a case statement where all choices must be covered, even if some of them can be ignored. As an example, consider a control signal CNTL in the range 0 to 31. When

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the value of CNTL is 3 or 15, the signals A and B will be xor-ed, otherwise nothing will occur. entity EX_WAIT is port ( CNTL: in integer range 0 to 31; A, B: in std_logic_vector(7 downto 0); Z: out std_logic_vector(7 downto 0) ); end EX_WAIT; architecture arch_wait of EX_WAIT is begin P_WAIT: process (CNTL) begin Z <=A; case CNTL is when 3 | 15 => Z <= A xor B; when others => null; end case; end process P_WAIT; end arch_wait;

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5.2 Dataflow Modeling Concurrent Statements


Behavioral modeling can be done with sequential statements using the process construct or with concurrent statements.This method is usually called dataflow modeling. The dataflow modeling describes a circuit in terms of its function and the flow of data through the circuit. This is different from the structural modeling that describes a circuit in terms of the interconnection of components. Concurrent signal assignments are event triggered and executed as soon as an event on one of the signals occurs. 5.2.1 Simple Concurrent signal assignments. A simple concurrent signal assignment is given in the following examples, Sum <= (A xor B) xor Cin; Carry <= (A and B); Z <= (not X) or Y after 2 ns; The syntax is as follows: Target_signal <= expression; 5.2.2 Conditional Signal assignments The syntax for the conditional signal assignment is as follows: Target_signal <= expression when Boolean_condition else expression when Boolean_condition else

expression; The target signal will receive the value of the first expression whose Boolean condition is TRUE. If no condition is found to be TRUE, the target signal will receive the value of the final expression. If more than one condition is true, the value of the first condition that is TRUE will be assigned.

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5.2.3 Selected Signal assignments:The selected signal assignment is similar to the conditional one described above. The syntax is as follows, with choice_expression select target_name <= expression when choices, target_name <= expression when choices, : target_name <= expression when choices; An example of a 4-to-1 multiplexer is given below. entity MUX_4_1_Conc2 is port (A, B, C, D: in std_logic; SEL: in std_logic_vector(1 downto 0);

Z: out std_logic) end MUX_4_1_Conc2; architecture concurr_MUX41b of MUX_4_1_Conc2 is begin with SEL select Z <= A when 00, B when 01, C when 10, D when 11; end concurr_MUX41b;
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5.3 Structural Modeling


A structural way of modeling describes a circuit in terms of components and its interconnection. Each component is supposed to be defined earlier (e.g. in package) and can be described as structural, a behavioral or dataflow model. At the lowest hierarchy each component is described as a behavioral model, using the basic logic operators defined in VHDL. In general structural modeling is very good to describe complex digital systems, though a set of components in a hierarchical fashion. A structural description can best be compared to a schematic block diagram that can be described by the components and the interconnections. VHDL provides a formal way to do this by Declare a list of components being used Declare signals which define the nets that interconnect components Label multiple instances of the same component so that each instance is uniquely defined. The components and signals are declared within the architecture body, architecture architecture_name of NAME_OF_ENTITY i -- Declarations component declarations signal declarations begin -- Statements component instantiation and connections end architecture_name;

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5.3.1 Component declaration:Before components can be instantiated they need to be declared in the architecture declaration section or in the package declaration. The component declaration consists of the component name and the interface (ports). The syntax is as follows: component component_name [is] [port (port_signal_names: mode type; port_signal_names: mode type);] end component [component_name]; A few examples of component declaration follow: component OR2 port (in1, in2: in std_logic; out1: out std_logic); end component; component PROC port (CLK, RST, RW, STP: in std_logic; ADDRBUS: out std_logic_vector (31 downto 0); DATA: inout integer range 0 to 1024); component FULLADDER port(a, b, c: in std_logic; sum, carry: out std_logic); end component;

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Chapter 6

Seven Segment Display And LCD


6.1 Seven Segment Display
There are two important types of 7-segment LED digital display

The Common Cathode Display (CCD) All cathodes are common and ground is being provided. The Common Anode Display (CAD) All anodes are common and Vcc is being provided

6.1.1 Interfacing common anode display


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6.2 Seven segment interfacing

Displaying numbers
0--- 1--- 2--- 3--- 4--- 5--- 6--- 7--- 8--- 9---
a 1 0 1 1 0 1 1 1 1 1 b 1 1 1 1 1 0 0 1 1 1 c 1 1 0 1 1 1 1 1 1 1 d 1 0 1 1 0 1 1 0 1 1 e 1 0 1 0 0 0 1 0 1 0 f 1 0 0 0 1 1 1 0 1 1 g 0 0 1 1 1 1 1 0 1 1

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6.3 LCD: Liquid Crystal Display


Liquid Crystal Displays HD44780(LCDs) cheap and easy way to display text, Displays numbers, letters and fixed symbols Various configurations (1 Line, 2 Line or 4 Line LCDs ). The display has two register

command register. data register.

By RS you can select register. Data lines (DB7-DB0) used to transfer data and commands.

6.3.1 Inside LCD


RAM In LCD we have two types of RAM DDRAM - Display Data RAM Display data RAM (DDRAM) stores display data represented in 8-bit character codes. CGRAM - Character Generator RAM CGRAM area is used to create custom characters in LCD. In the character generator RAM, the user can rewrite character patterns by program.

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Instruction Register (IR) and Data Register (DR) Instruction register corresponds to the register where you send commands to LCD e.g LCD shift command, LCD clear, LCD address etc. Data register is used for storing data which is to be displayed on LCD. 6.4.3 Pin Information of LCD

UNDERSTANDING LCD

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Pin Out
8 data pins D7:D0

Bi-directional data/command pins. Alphanumeric characters are sent in ASCII format.


RS: Register Select

. .

RS = 0 -> Command Register is selected. RS = 1 -> Data Register is Selected.


R/W: Read or Write 0 -> Write, 1 -> read E: Enable (Latch data) Used to latch the data present on the data pins A high-to-low edge is needed to latch the data. VO : contrast control

6.4.4 Instruction Set

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Chapter 7

Relay and Buzzer

In CPLD/FPGA we cant process AC.So for this we use Relay.

7.1 Relay
A relay is an electrical switch that opens and closes under the control of another electrical circuit. In the original form, the switch is operated by an electromagnet to open or close one or many sets of contacts. It was invented by Joseph Henry in 1835. Because a relay is able to control an output circuit of higher power than the input circuit, it can be considered to be, in a broad sense, a form of an electrical amplifier.To off dc to ac we use relay,having 5 pins.eg TV works on 220v and remote works on 5v.If we have to on/off the TV then it is done by Relay.because 5v cant be compare with 220v. Operation When there is a current through the coil, the resulting magnetic field attracts an armature that is mechanically linked to a moving contact. The movement either makes or breaks a connection with a fixed contact. When the current to the coil is switched off, the armature is returned by a force approximately but gravity is also used commonly in industrial motor starters. Most relays are manufactured to operate quickly. In a low voltage application, this is to reduce noise. In a high voltage or high current application, this is to reduce arcing. If the coil is energized with DC, a diode is frequently installed across the coil, to dissipate the energy from the collapsing magnetic field at deactivation, which would otherwise generate a spike of voltage and might cause damage to circuit components. Some automotive relays already include that diode inside the relay case. Alternatively a contact protection network, consisting of a capacitor and resistor in series, may absorb the surge. If the coil is designed to be energized with AC, a small copper ring can be crimped to the end of the solenoid. This "shading ring" creates a small out-of-phase current, which increases the minimum pull on the armature during the AC cycle.

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By analogy with the functions of the original electromagnetic device, a solid-state relay is made with a thyristor or other solid-state switching device. To achieve electrical isolation an optocoupler can be used which is a light-emitting diode (LED) coupled with a photo transistor.

Since relays are switches, the terminology applied to switches is also applied to relays. A relay will switch one or more poles, each of whose contacts can be thrown by energizing the coil in one of three ways:

Normally-open (NO) contacts connect the circuit when the relay is activated; the circuit is disconnected when the relay is inactive. It is also called a Form A contact or "make" contact.

Normally-closed (NC) contacts disconnect the circuit when the relay is activated; the circuit is connected when the relay is inactive. It is also called a Form B contact or "break" contact.

Change-over (CO), or double-throw (DT), contacts control two circuits: one normallyopen contact and one normally-closed contact with a common terminal. It is also called a Form C contact or "transfer" contact ("break before make"). If this type of contact utilizes a "make before break" functionality, then it is called a Form D contact.

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7.1.1 Applications Relays are used:

to control a high-voltage circuit with a low-voltage signal, as in some types of modems or audio amplifiers,

to control a high-current circuit with a low-current signal, as in the starter solenoid of an automobile,

to detect and isolate faults on transmission and distribution lines by opening and closing circuit breakers (protection relays). We cant use FPGA direct to relay because back current flow which damage FPGA. To overcome this we use Optocoupler(IC) in between relay and FPGA.

7.2 Optocoupler:
Optocoupler is used to direct the current in inward directions In electronics, an opto-coupler (or optical isolator, optocoupler, photocoupler, or

photoMOS) is a device that uses a short optical transmission path to transfer a signal between elements of a circuit, typically a transmitter and a receiver, while keeping them electrically isolated since the signal goes from an electrical signal to an optical signal back to an electrical signal, electrical contact along the path is broken.

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A common implementation involves a LED and a phototransistor, separated so that light may travel across a barrier but electrical current may not. When an electrical signal is applied to the input of the opto-isolator, its LED lights, its light sensor then activates, and a corresponding electrical signal is generated at the output. Unlike a transformer, the optoisolator allows for DC coupling and generally provides significant protection from serious overvoltage conditions in one circuit affecting the other. With a photodiode as the detector, the output current is proportional to the amount of incident light supplied by the emitter. The diode can be used in a photovoltaic mode or a photoconductive mode. In photovoltaic mode, the diode acts like a current source in parallel with a forward-biased diode. The output current and voltage are dependent on the load impedance and light intensity. In photoconductive mode, the diode is connected to a supply voltage, and the magnitude of the current conducted is directly proportional to the intensity of light. An opto-isolator can also be constructed using a small incandescent lamp in place of the LED; such a device, because the lamp has a much slower response time than a LED, will filter out noise or half-wave power in the input signal. In so doing, it will also filter out any audio- or higher-frequency signals in the input. It has the further disadvantage, of course, (an overwhelming disadvantage in most applications) that incandescent lamps have relatively short life spans. Thus, such an unconventional device is of extremely limited usefulness, suitable only for applications such as science projects. The optical path may be air or a dielectric waveguide. The transmitting and receiving elements of an optical isolator may be contained within a single compact module, for
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mounting, for example, on a circuit board; in this case, the module is often called an optoisolator or opto-isolator. The photosensor may be a photocell, phototransistor, or an optically triggered SCR or TRIAC. Occasionally, this device will in turn operate a power relay or contactor. For analog isolation, special "analog" optoisolators are used. These devices have two independent, closely matched phototransistors, one of which is typically used to linearize the response using negative feedback.

Schematic diagram of a very simple opto-isolator with an LED and phototransistor. The dashed line represents the isolation barrier, over which no electrical contact can be permitted.

A simple circuit with an opto-isolator. When switch S1 is closed, LED D1 lights, which triggers phototransistor Q1, which pulls the output pin low. This circuit, thus, acts as a NOT gate.

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Chapter 8
Function and Procedure
8.1 Function
A FUNCTION is very similar to a PROCESS . The same statements that can be used in a process (IF, WAIT, CASE, and LOOP) can also be used in a function, with the exception of WAIT. Other two prohibitions in a function are SIGNAL declarations and COMPONENT instantiations . Function Body FUNCTION function_name [<parameter list>] RETURN data_type IS [declarations] BEGIN (sequential statements) END function_name; Function Call A function is called as part of an expression. Examples of function calls: 1. x <= conv_integer(a); 2. y <= maximum(a, b) 3. <parameter _list>= SIGNAL signal_name: signal_type; 4. <parameter _list>=[CONSTANT] constant_name: mode type; 5. Parameter list can contain only CONSTANT (default) or SIGNAL (VARIABLES are not allowed).
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6. Parameters can be only of IN mode 7. No range specification should be included (for example TO/DOWNTO when using STD_LOGIC_VECTOR). 8. Produce a single return value 9. Called by expressions 10. Cannot modify the parameters passed to them 11. Require a RETURN statements

For example: ARCHITECTURE behavior OF adder IS


BEGIN PROCESS (enable, x, y) BEGIN IF (enable = '1') THEN result <= add_bits(x, y); carry <= x AND y; ELSE carry, result <= '0'; END PROCESS; END behavior;

8.2 Procedure
In this there is multiple output. No return statements.

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Procedure name is call by it self. Procedure Body PROCEDURE procedure_name [<parameter list>] IS [declarations] BEGIN (sequential statements) END procedure_name; Procedure call Compute_min_max(in1, in2, 1n3, out1, out2); <parameter list>=[CONSTANT] constant_name: mode type; <parameter list>=SIGNAL signal_name: mode type; <parameter list>=VARIABLE variable_name: mode type; A PROCEDURE can have any number of IN, OUT, or INOUT parameters. May produce multiple output values Are invoked by statements May modify the parameters For example ARCHITECTURE behavior OF adder IS BEGIN PROCESS (enable, x, y) BEGIN add_bits3(x, y, enable, result, carry); END PROCESS; END behavior;

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8.3 Difference between Function and Procedure:


In function signal,constant is in perameter list.But in procedure variable are also included. Function has return statements.Procedure has no return statement. Only inmode is allowed in function.In procedure in,out,inout are allowed.

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Chapter 9

PCB DESIGNING
9.1 PCB
PCB stands for PRINTED CIRCUIT BOARD. The PCB manufacturing process is very important for anyone involved in the electronics industry. Printed circuit boards are very widely used as the basis for electronic circuits. Printed circuit board (PCB) provides both the physical structure for mounting and holding the components as well as the electrical interconnection between the components using conductive pathways, tracks or signal traces etched from copper sheets laminated onto a nonconductive substrate. It is also referred to as printed wiring board (PWB) or etched wiring board. A PCB populated with electronic components is a printed circuit assembly (PCA), also known as a printed circuit board assembly(PCBA). This assembly is the basic building block for all the electronic appliances such as television, computer and other goods.

9.1.1 PCB has two main parts:


(1) Track side (2) Components side

The printed circuit boards consists of an insulating substrates metallic circuit photo chemically formed upon that substrate. Inter-connection between components is achieved by means of conductivity paths running on or through the substrate called TRACK. Track meet components to which they are to be connected by means of larger conductor area called a LAND or PAD. The electrical connection between a land components terminal is achieved by means of a solder.

9.2 Types of PCB:


PCB may be of different types:1) Single-sided 2) Double-sided
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3) Multilayer
Single sided PCBs: - As the name suggest in these designs the conductive pattern is only at in

one side. And also the size is large in these case but these are cheap.
Double sided PCBs: - These are the PCBs on which the conductive pattern is in on both sides.

The size of board is small in this case but it is costlier than single sided PCBs.
Multilayer PCBs: - In this case the board consists of alternating layers of conducting pattern

and insulating material. The conductive material is connected across the layers through plated through holes. The size of this PCB is smaller than that of double sided PCB but it is very costly.

9.3 ADVANTAGES of Using PCBs:

1. Circuit characteristics can be maintained without introducing variation in inter-circuit

capacitance. 2. Components wiring and assembly can be mechanized by ware soldering. 3. Mass production can be achieved at lower cast. 4. The size components assembly can be reduced with corresponding decreases in weight. 5. Inspection time is reduced as probability of error is eliminated.

9.4 DISADVANTAGES of PCBs:


1. As the copper strips are very thin they can carry little hence PCB cannot be used for heavy

currents, because in that case the strips will be heated and can cause problem. 2. Soldering need precautions as the risk of strips being over heated and destroyed is always there. 3. For big circuits, PCB cannot be used because it cannot carry heavy components
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9.5 PCB designing softwares:


There many softwares which are used for PCB designs. Some of them are given below:-

Mentor The most commonly software which are used for PCB design in India are Protel and OrCad.

OrCad CADSTAR Protel TANGO

9.5.1 PCB designing Using ORCAD:


OrCad has a long history of providing individuals and teams with a complete set of technologies that offer unprecedented productivity, seamless tool integration, and exceptional value. New 10.5 release continues that tradition.Today's lower cost and yet highly sophisticated electronic design automation systems have created a unique challenge to nearly every engineering department. Therefore the use of EDA tools has become increasingly important as product lifecycles have become shorter and shorter. Modern electronic design automation (EDA) tools are beginning to support a more efficient and integrated approach to electronic.OrCad Capture design entry is the most widely used schematic entry system in electronic design today for one simple reason: fast and universal design entry. Whether you're designing a new analog circuit, revising schematic diagram for an existing PCB, or designing a digital block diagram with an HDL module, OrCad Capture provides simple schematic commands you need to enter, modify and verify the design for PCB. OrCad Layout offers PCB designers and PCB design teams the power and flexibility to create and share PCB data and constraints across the design flow. OrCad Layout delivers all the capabilities to designers need from netlist to place and route, to final output. The ease-of use and intuitive capabilities of OrCad Layout provides for quick startup and rapid learning right out of the box. 9.5.1(1) BASIC DESIGN STEPS IN ORCAD:
1-Draw schematic on CAPTURE.

2-Check for DRC. 3-Extract .MNL file (netlist) 4-Designing PCB on LAYOUT.
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5-Gerber file extraction.

6-PCB fabrication.

CAPTURE: Capture is used to drawn a circuit on the screen, known formally as schematic capture. It
offers great flexibility compared with a traditional pencil and paper drawing, as design changes can be incorporated and errors corrected quickly and easily.CAPTURE stores all of a designs schematics, schematic pages and parts in a single file. This makes it easy to handle designs. Schematic diagram provides the functional flow and the graphical representation of an electronic circuit. The entry of schematic diagram is the first step in PCB design using OrCad.

Electrical connections(nets) Junctions Integrated circuits symbols

A schematic diagram consists of:-

Discrete components symbols like resistors, capacitors etc. Input / output connectors Power and ground symbols Buses No connection symbols Components reference names Text The Schematic Page Editor:
The schematic page editor is used to display and edit schematic pages. So that one can parts; wires; buses and draw graphics. The schematic page editor has a tool palette that you can use to draw and place everything you need to create a schematic page. One can print from within the schematic page editor, or from the project window.

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The Session Log:

The session log lists the events that have occurred during the current Capture session, includes message resulting from using captures tools. To display context-sensitive help for an error message, put the cursor in the error message line in the session log press F1. The ruler along the top appears in either inches or mill meters, depending on which measurement system is selected in the window panel. Your tab setting are saved and used each time you start capture.

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One can search for information in the session log using the find command on the Edit menu. You can also save the contents of the of the session log to a file, which is useful when working with Orcads technical support to solve technical problems. The default filename is SESSION.TXT.

The Toolbar:
Captures toolbar is dock able (that means you can select and drag the toolbar to new location) as well as resizable, and displays tool tips for each tool; by choosing a tool button you can quickly perform a task. If tool button is dimmed, you cant perform that task in the current situation.

The Capture Toolbar:

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Some of the tools operate only on what you have selected, while others give you a choice of either operating on what is selected or expanding the scope to entire project.

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You can hide the toolbar, then display it again when u need it. For hiding select from the schematic page editors view menu, choose TOOLBAR.

The Part editor:


The part editor is used to create and edit parts. From the view menu of the part editor you can choose either part or package. In part view one can:-

Create and edit parts and symbols, then store in new or existing libraries. Create and edit power and ground symbols, off-page connector symbols, and title
block

Use the tool palettes electrical tools to place pins on parts, and its drawing tools to
draw parts and symbols.

The Tool Palette:


Capture has two tool palettes: one for the schematic page editor and one for the part editor. Both tool palettes are dock able and resizable. They can also display tool tips that identify each tool. The drawing tools on the two tool palettes are identical, however, each tool palette has different electrical tools after you choose a tool, and you press the right mouse button to display a context- sensitive pop-up menu. The schematic page editor tool palette: The first group of tools on the tool palette is electrical tools, used to place electrical connectivity objects. The second group of tools is Drawing tools, used to create graphical objects without electrical connectivity.

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The part editor tool palette:


The first group of tools on the part palette is electrical tools, used to place pins and symbols. They have been already explained above within the schematic page editor tools. The second group of tools is drawing tools, used to create graphical objects without objects any electrical connectivity and is described:

Pin Tools: Place pins on part Pin Array: Place multiple pins on part Selecting and deselecting of objects Once one selects an object, one can perform operations on it, include moving, copying, cutting, mirroring, rotating, resizing, or editing. One can also select multiple, objects and edit

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them, or group them in to a single object. Grouping objects maintain relation ship among them while one moves them to another location.

Creating Net list File


Net-list file is a document file which contains information about the logical interconnections between signals and pins. Before one create a net list file, be sure ones project is completed, annotated and it is free from electrical rule violations. A net list file consists of nets, components, connectors, junctions, no connection symbol, power and ground symbols.

Creation of net list in capture: Select your design in the project manager. From the tools, choose create net list. The net list dialog box displays. Choose a net list format tab. If necessary, set the part value and PCB foot print combined property strings to reflect
the information you want in the net list.

Click ok to create the net list. In the net list file text box, enter a name for the output file. If the selected format
creates an additional file, enter its file name in the second text box

LAYOUT PLUS
OrCAD Layout is a powerful printed circuit board layout tool that is a part of a full line of design and simulation tools available from OrCAD. OrCAD Layout makes it easy to place, route and prepare printed circuit boards for fabrication. In Layout we place as well as route the components and set unit of measurement, grids, and spacing in OrCad. For the placement and routing of the components auto-placement and auto-routing options are also available. In layout plus we also define the layer stacks, pad stacks and via's.

Some files used in Layout:


Template files:

A template (.TPL) file describes the characteristics of a physical board. A template can include information, such as the board outline, the design origin, the layer definitions, grid settings, spacing rules, and default track widths.

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Technology file:

A technology file (.TCH) can be considered as a subset of the template files. This is because technology files contain information, such as default line width, spacing, grid settings, layer definitions, and via padstacks, but they do not provide any information regarding physical characteristics of a board.
MNL file:

A Layout netlist file (.MNL) describes the parts and interconnections in a schematic. Steps for board design: At first, we have created a net list from our schematic diagram by using capture.

Layout plus includes design rules in order to guide logical placement and routing. That
means, load the net list into layout to create the board. At the same time you have to specify the board parameters.

Specify board parameters: Specifying global setting for the board, including nits of
measurements, grid, and spacing

Place components: Use the components tool in order to place manually the
components which are fixed by the system designer on the board or otherwise use auto-placement.

Route the board: Use different routing technologies to route the board and take
advantage of push and shove (a routing technology), which moves track you are currently routing as well as you can also auto route the board.

Provide finishing of the board: Layout supplies an ordered progression of commands


on the auto menu for finishing your design. These commands include design rule check, cleanup design, rename components, back annotate, run post processor, and create reports.

The design window:

The design window provides a graphical display of printed circuit board, it is primary window you use when designing your board. It also provides tools to facilitate the design process such as to update components and design rule violation.

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Method to create a board with Layout Plus: Ensure that net list with all footprints and necessary information has been created.

Create a directory in which the schematic design, net list, and boar will co-exit and put
the schematic design and net list. OrCad provides a directory for this purpose.

From the layout session frames file menu, choose New. The load template file in the
dialog box displayed.

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Select the technology template (.TCH), then choose the open button and load the net list in other box. Then apply the auto ECO. If necessary, respond to link footprints to component dialog. Draw the board outline by using the obstacle tool in the tool bar.

Setting board parameters: There is some parameter which should be set before placing the components on board. They are as follows:-

Set Datum Create a board outline Set units of measurements Set system grid Add mount holes
Creating of board outline: Board outline is the graphical representation of the size of the actual PCB board. So it is the main step in layout, to draw the board outline of the actual size of PCB board. Placement of components:
Placement of components means that to place the components in designed box. A designer should follow the following steps before going for it:-

Optimize the board for component placement. Load the placement strategy file. Place components on the board. Optimize placement using various placements

Components can be placed by using two techniques:-

1) Manual placement of components 2) Auto placement of components Choose the components tool bar button. From the pop up men, choose the queue for placement. The components selection criteria dialog box appears. Enter the reference

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designator of the components that you want to place in the appropriate text box, and click ok. Drag the components to desired location, place it there.
Conductor Routing in Layout:-

After placing all the components the other main step is to route the board from the electrical connections between the components. One may route board manually or automatically by auto router. 100% auto routing can be achieved only when components are placed in the order of functional flow of electronic circuit. The main routing tool available in OrCad is as flow:-

Add/edit route mode Edit segment mode Shove track mode


Auto path route mode

Design Rule Check:-

In manual designs every thing was checked as a possible source of error. Components sizes, hole sizes, conductor widths and clearance, land-to-hole-ratio, board areas to be free of components, clearance to the edges, positional accuracy and of course electrical interconnections had tad to be personally reviewed with a great deal of care. After completing the design of printed circuit board with the help of an EDA-Tool, a designer has again to verify the PCB in order to find out errors. Such type of verifications/design rule check contains beside the general verifications commonly two types:Physical verification Electrical verification

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Chapter 10
Wireless
10.1 Introduction Wireless communic action is a rapidly growing segment of the communic action industry,with the potential to provide high speed high quality information exchange between portable devices located anywhere in the world. Wireless telecommunications is the transfer of information between two or more points that are not physically connected. Distances can be short, such as a few meters for television remote control, or as far as thousands or even millions of kilometers for deep-space radio communications. Wireless operations permits services, such as long range communications, that are impossible or impractical to implement with the use of wires. The term is commonly used in the telecommunications industry to refer to telecommunications systems (e.g. radio transmitters and receivers, remote controls, computer networks, network terminals, etc.) which use some form of energy (e.g. radio frequency (RF),acoustic energy, etc.) to transfer information without the use of wires.[1] Information is transferred in this manner over both short and long distances.The various techniques of wireless communication are: Bluetooth-transfer of data having range 10 meter Zigbee- advancement of bluetooth having range 100 meter.In Zigbee we can connect 128 devices for transmission of data at a time. GPS-Globle Position of Settelite.to tell the position. RFID-Radio Freequency Identification

10.2 RFID The acronym refer to small electronic device that consist of small chip and antenna.The chip typically is capable of carrying 2000 bytes of data or less. RFID is the reading of physical tags on single products, cases, pallets, or re-usable containers that emit radio signals to be
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picked up by reader devices. These devices and software must be supported by a sophisticated software architecture that enables the collection and distribution of locationbased information in near real time. The complete RFID picture combines the technology of the tags and readers with access to global standardized databases, ensuring real time access to up-to-date information about relevant products at any point in the supply chain. A key component to this RFID vision is the EPC Global Network. Tags contain a unique identification number called an Electronic Product Code (EPC), and potentially additional information of interest to manufacturers, healthcare organizations, military organizations, logistics providers, and retailers, or others that need to track the physical location of goods or equipment. All information stored on RFID tags accompanies items as they travel through a supply chain or other business process. All information on RFID tags, such as product attributes, physical dimensions, prices, or laundering requirements, can be scanned wirelessly by a reader at high speed and from a distance of several meters.

10.2.1 Tag or TransponderAn RFID tag is a tiny radio device that is also referred to as a transponder, smart tag, smart label, or radio barcode. The tag comprises a simple silicon microchip (typically less than half a millimeter in size) attached to a small flat aerial and mounted on a substrate. The whole device can then be encapsulated in different materials (such as plastic) dependent upon its intended usage. The finished tag can be attached to an object, typically an item, box, or pallet, and read remotely to ascertain its identity, position, or state. For an active tag there will also be a battery.

A variety of RFID Tags


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There are two types of Tag: Active Passive In Active,having power supply on tag.and it continuously transmit the data. In Passive,doesnt having power supply and it transmit data when it is in readers range.eg metro station. In tag there is silicon chip and antenna.silicon chip contain unique ID no.And antenna transmit when transmission occur. 10.2.2 Reader or InterrogatorThe readersometimes called an interrogator or scanner sends and receives RF data to and from the tag via antennas. A reader may have multiple antennas that are responsible for sending and receiving radio waves. It is also known as Base station.

Basic Operations of RFID

10.3 GSM
The Global System for Mobile communication (GSM) is an ETSI (European Telecommunication Standard Institute) standard for 2G pan European digital cellular with
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international roaming. The main purpose of the group was to develop a 2G standard to resolve the roaming problem in the six existing different 1G analog systems in Europe. In 1986, the task force was formed, and in 1987 a memorandum of understanding (MoU) was signed. In 1989, ETSI included GSM in its domain. In 1991, the specification of the standard was completed, and in 1992, the first deployment started. By the year 1993, thirty two operators in 22 countries adopted the GSM standard, and by 2001, close to 150 countries had adopted GSM for cellular adaptation. 10.3.1 Frequency Bands This GSM system is a frequency and time division system. Each physical channel is characterized by a carrier frequency and a time slot number. GSM system frequencies include two bands at 900 MHZ and 1800 MHz commonly referred to as the GSM 900 and DCS 1800 systems. For the primary band in the GSM 900 system, 124 radio carriers have been defined and assigned in two sub-bands of 25 MHz each in the 890 915 MHz and 935-960 MHz ranges with channel width of 200 kHz (these sub-bands are always referred as downlink as well as uplink respectively, we will see this concept in detailed in channel concepts later in this module). Each carrier (a total channel width of 200 KHz) is divided into frames of 8 time slots. For DCS 1800, there are two sub bands of 75 MHz in the 1710 1785 MHz and 1805 1880 MHz ranges 10.3.3 GSM Services To study any system, it is very important to know the services, which the system supports or provides. Analog cellular systems were developed for a single application that is voice and in a manner similar to analog access to PSTN, other data services such as fax and voice-band modems were defined as overlay services on top of the analog voice service. GSM is an integrated voice-data service that provides a number of services beyond cellular telephone. These services are divided into three major categories. They are Teleservices, Bearer services and supplementary services. 10.3.4 Features of GSM 1. The GSM system provides a greater subscriber capacity than analogue systems. 2. GSM allows 25 kHz per user, that is, eight conversations per 200 kHz channel pair (a pair comprising one transmit channel and one receive channel).
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3.Digital channel coding and the modulation used makes the signal resistant to interference from cells where the same frequencies are re-used (co-channel interference); a Carrier to Interference Ratio (C/I) level of 12 dB is achieved, as opposed to the 18 dB typical with analogue cellular. 4. This allows increased geographic reuse by permitting a reduction in the number of cells in the reuse pattern.

10.4 Blutooth
Bluetooth is a proprietary open wireless technology standard for exchanging data over short distances (using short wavelength radio transmissions in the ISM band from 24002480 MHz) from fixed and mobile devices, creating personal area networks (PANs) with high levels of security. Created by telecoms vendor Ericsson in 1994. It was originally conceived as a wireless alternative to RS-232 data cables. It can connect several devices, overcoming problems of synchronization. Bluetooth is managed by the Bluetooth Special Interest Group, which has more than 15,000 member companies in the areas of telecommunication, computing, networking, and consumer electronics.[2] The SIG oversees the development of the specification, manages the qualification program, and protects the trademarks.[3] To be marketed as a Bluetooth device, it must be qualified to standards defined by the SIG. A network of patents is required to implement the technology and are only licensed to those qualifying devices; thus the protocol, whilst open, may be regarded as proprietary.

Bluetooth logo

10.5 Zigbee

ZigBee is a specification for a suite of high level communication protocols using small, lowpower digital radios based on an IEEE 802 standard for personal area networks. Applications
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include wireless light switches, electrical meters with in-home-displays, and other consumer and industrial equipment that requires short-range wireless transfer of data at relatively low rates. The technology defined by the ZigBee specification is intended to be simpler and less expensive than other WPANs, such as Bluetooth. ZigBee is targeted at radio-frequency (RF) applications that require a low data rate, long battery life, and secure networking. ZigBee has a defined rate of 250 kbps best suited for periodic or intermittent data or a single signal transmission from a sensor or input device.

zigbee Module

ZigBee protocols are intended for embedded applications requiring low data rates and low power consumption. The resulting network will use very small amounts of power individual devices must have a battery life of at least two years to pass ZigBee certification Typical application areas include:

Home Entertainment and Control Home automation, smart lighting, advanced temperature control, safety and security, movies and music Wireless Sensor Networks' Starting with individual sensors like Telosb/Tmote and Iris from Memsic.

Industrial control, Embedded sensing, Medical data collection, Smoke and intruder warning, Building automation.

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Major Project
AUTOMATIC TOLL PLAZA SYSTEM

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Aim
Electronic toll collection (ETC), an adaptation of military "identification friend or foe" technology, aims to eliminate the delay on toll roads by collecting tolls electronically. It is thus a technological implementation of a road pricing concept. It determines whether the cars passing are enrolled in the program, alerts enforcers for those that are not, and electronically debits the accounts of registered car owners without requiring them to stop.The major advantage of this is that users are able to drive through the toll plaza at highway speed without having to slow down to pay the toll.

Introduction
In 1959, Nobel Economics Prize winner William Vickrey was the first to propose a system of electronic tolling for the Washington metropolitan area. He proposed that each car would be equipped with a transponder. The transponders personalised signal would be picked up when the car passed through an intersection, and then relayed to a central computer which would calculate the charge according to the intersection and the time of day and add it to the cars bill. In the 1960s and 1970s, free flow tolling was tested with fixed transponders at the undersides of the vehicles and readers, which were located under the surface of the highway. Norway has been the world's pioneer in the widespread implementation of this technology. ETC was first introduced in Bergen, in 1986, operating together with traditional tollbooths. In 1991, Trondheim introduced the world's first use of completely unaided full-speed electronic tolling. Norway now has 25 toll roads operating with electronic fee collection (EFC), as the Norwegian technology is called (see AutoPASS). In 1995, Portugal became the first country to apply a single, universal system to all tolls in the country, the Via Verde, which can also be used in parking lots and gas stations. The United States is another country with widespread use of ETC in several states, though many U.S. toll roads maintain the option of manual

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collection.

On an open toll system, all vehicles stop at various locations along the highway to pay a toll. While this may save money from the lack of need to construct toll booths at every exit, it can cause traffic congestion while traffic queues at the mainline toll plazas (toll barriers). It is also possible for motorists to enter an 'open toll road' after one toll barrier and exit before the next one, thus travelling on the toll road toll-free. Most open toll roads have ramp tolls or partial access junctions to prevent this practice, known as "shunpiking". With a closed system, vehicles collect a ticket when entering the highway. In some cases, the ticket displays the toll to be paid on exit. Upon exit, the driver must pay the amount listed for the given exit. Should the ticket be lost, a driver must typically pay the maximum amount possible for travel on that highway. Short toll roads with no intermediate entries or exits may have only one toll plaza at one end, with motorists traveling in either direction paying a flat fee either when they enter or when they exit the toll road. In a variant of the closed toll system, mainline barriers are present at the two endpoints of the toll road, and each interchange has a ramp toll that is paid upon exit or entry. In this case, a motorist pays a flat fee at the ramp toll and another flat fee at the end of the toll road; no ticket is necessary. In addition, with most systems, motorists may only pay tolls with cash and/or change; debit and credit cards are not accepted. However, some toll roads may have travel plazas with ATMs so motorists can stop and withdraw cash for the tolls. Toll roads have been criticized as being inefficient in various ways:
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1. They require vehicles to stop or slow down, manual toll collection wastes time and raises vehicle operating costs. 2. Collection costs can absorb up to one-third of revenues, and revenue theft is considered to be comparatively easy. 3. Where the tolled roads are less congested than the parallel "free" roads, the traffic diversion resulting from the tolls increases congestion on the road system and reduces its usefulness. 4. By tracking the vehicle locations, their drivers are subject to an effectual restriction of their freedom of movem ent and freedom from excessive surveillance. Hence to overcome this i made project based on RFID.

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Block diagram:

This project consist of various units.


1. RFID Tag and reader 2. CPLD 3. Display Unit 4. Stepper Motor and driver 5. RS232 Protocol Descriptions RFID: A basic RFID system consists of three components:

An antenna or coil A transceiver (with decoder)

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The antenna emits radio signals to activate the tag and to read and write data to it. The reader emits radio waves in ranges of anywhere from one inch to 100 feet or more, depending upon its power output and the radio frequency used. When an RFID tag passes through the electromagnetic zone, it detects the reader's activation signal.

The reader decodes the data encoded in the tag's integrated circuit (silicon chip) and the data is passed to the host computer for processing.

RFID MODULE

The purpose of an RFID system is to enable data to be transmitted by a portable device, called a tag, which is read by an RFID reader and processed according to the needs of a particular application. The data transmitted by the tag may provide identification or location information, or specifics about the product tagged, such as price, color, date of purchase, etc. RFID technology has been used by thousands of companies for a decade or more. . RFID quickly gained attention because of its ability to track moving objects. As the technology is refined, more pervasive - and invasive - uses for RFID tags are in the works.

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A typical RFID tag consists of a microchip attached to a radio antenna mounted on a substrate.The chip can store as much as 2 kilobytes of data.

To retrieve the data stored on an RFID tag, you need a reader. A typical reader is a device that has one or more antennas that emit radio waves and receive signals back from the tag. The reader then passes the information in digital form to a computer system. READER

TAG: Tag has two types


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Active Passive

In active, having power supply on tag. It continuously transit data. In passive, not having power supply. It transmits data only when it is in reader range. In tag there is silicon chip and antenna. silicon chip contains unique ID no.

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TAG

Stepper Motor: This section of tutorial will explain you everything that you need to know about stepper motors. Stepper motors can be used in various areas of your microcontroller projects such as making robots, robotic arm, automatic door lock system etc. This tutorial will explain you construction of stepper motors (unipolar and bipolar stepper motors ), basic pricipal, different controlling types (Half step and Full step), Interfacing Techniques (using L293D or ULN2003) and programming your microcontroller in C and assembly to control stepper motor.

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Unipolar stepper motor

motor

The unipolar stepper motor has five or six wires and four coils (actually two coils divided by center connections on each coil). The center connections of the coils are tied together and used as the power connection. They are called unipolar steppers because power always comes Is on this one pole. :

Bipolar stepper motor

The bipolar stepper motor usually has four wires coming out of it. Unlike unipolar steppers, bipolar steppers have no common center connection. They have two independent sets of coils instead. You can distinguish them from unipolar steppers by measuring the resistance between the wires. You should find two pairs of wires with equal resistance. If you've got the leads of your meter connected to two wires that are not connected (i.e. not attached to the same coil), you should see infinite resistance (or no continuity).

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As already said, we will talk mostly on "Unipolar stepper motors" which is most common type of stepper motor available in the market.A simple example of 6 lead step motor is given below and in 5 lead step motor wire 5 and 6 are joined together to make 1 wire as common.

Working

Now lets discuss the operation pricipal of a stepper motor. When we energize a coil of stepper motor, The shaft of stepper motor (which is actually a permanent magnet) align itself according to poles of energized coil. So when motor coils are energized in a particular sequence, motor shaft tend to align itself according to pole of coils and hence rotates. A small

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example of energizing operation is

You can see in the example, when coil "A" is energized, A north-south polarity is generated at "A+A\" as shown in the figure above and magnetic shaft automatically align itself according to the poles generated. When the next coil is energized the shaft again align itself and take a step. Hence the working pricipal.

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Stepangle . . . . Step angle of the stepper motor is defined as the angle traversed by the motor in one step. To calculate step angle,simply divide 360 by number of steps a motor takes to complete one revolution. As we have seen that in half mode, the number of steps taken by the motor to complete one revolution gets doubled, so step angle reduces to half.

CPLD Section: The daughter card section is most important section of the board. This section has 44 pins for connecting CPLD card. 8 Mhz oscillator is provided to give clock to programmable device .The frequency of this section determines the time taken or any operation.

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PIN

OUT

DIAGRAM

OF

CPLD

(XC9572-15PC44)

VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin D0-D32=input pins

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RS232 Protocol: RS-232 (Recommended Standard 232) is a standard for serial binary data signals connecting between a DTE (Data terminal equipment) and a DCE (Data Circuit-terminating Equipment). VoltageLevels. The RS-232 standard defines the voltage levels that correspond to logical one and logical zero levels. Valid signals are plus or minus 3 to 25 volts. The range near zero volts is not a valid RS-232 level; logic one is defined as a negative voltage, the signal condition is called marking, and has the functional significance of OFF. Logic zero is positive, the signal condition is spacing, and has the function ON So a Logic Zero represented as +3V to +25V and Logic One represented as -3V to -25V. .

RS-232 Level Converters

Converters

Usually all the digial ICs works on TTL or CMOS voltage levels which cannot be used to communicate over RS-232 protocol. So a voltage or level converter is needed which can convert TTL to RS232 and RS232 to TTL voltage levels. .

The most commonly used RS-232 level converter is MAX232. This IC includes charge pump which can generate RS232 voltage levels (-10V and +10V) from 5V power supply. It also includes two receiver and two transmitters and is capable of full-duplex UART/USART communication
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MAX 232 PIN DIAGRAM

MAX232 Typical Connection Circuit

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Toll Plaza PCB Section

List of components:-

44 pin cpld ic base 8 pin IC base 44 pin cpld ic 10 pin box adder 8 mhz crystal oscillator IC-Max 32 IC-LM317 regulator
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DB9 male connector Leds Capacitors Resistors Power connector Db9 cross cable mab

Components Used for the Project:

COMPONENT LM317 Regulator 1k Resistance 330 Resistance 470 Resistance 10-pin box headers Power Jack Sliding Switch 10k Capacitor Red LEDs Max232IC MAX 232 IC base DB9 male connector

QUANTITY 1 3 1 1 5 1 1 1 2 1 1 1

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TECHNIQUE USED FOR CONNECTING COMPONENTS:


SOLDERING: Soldering is an alloying process between two metals or soldering is a method of making reliable joints. IRON SOLDERING: It is one of the most oldest and common methods of obtaining a solder joint. If the numbers of PCBs and components to be soldered are less, hand soldering process is used. The 1.Soldering iron 2.Solder 3. Soldering flux Tools Soldering Iron:It is reasonable priced electrical equipment. It supplies sufficient heat to melt solder by heat transfer, when the iron tip is applied to connection to be soldered. Soldering iron is available in different temperature ranges, for professional use and industrial grade these are available with at the output ratings of 6W, 8W, 12W, 25W, 35W, 65W, 100W and 150W. Selection of iron depends upon the type of use for which it is being put to temperature is selected and controlled according to the work performed. Solder:It is the oldest and most widely used alloy. It is a generic name representing a host of alloys of low melting metal like tin, cadmium, bismuth, indium, silver and many more.

Working Here what i have done is a prototype for an Automated Ticketless Toll Booth System, in which we dont require to pay "paper money" while passing through a toll booth. Rather you require showing an RFID Tag, which has a personal 10 Bytes Identifier [of which last 3 Bytes are used for identification] to an RFID Module. This database has stored charges for each user. These charge decrements while using the RFID Tag in the Toll Booth.

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In this, every car consists of tag having a unique no which is stored in processor unit means in data base. When card enter at toll booth, reader detect the code and compare with database. If data in data base match with the data in tag then there will be green display and stepper motor will rotate by 90 degree and also reverse wise, and barrier will be open. If the code will not match the red display will on and barrier will remain closed.

PROGRAMMING CODE:
entity rfidlcd is Port ( clk : in STD_LOGIC; sin : in bit; led : out STD_LOGIC_vector(1 downto 0); j : out STD_LOGIC_VECTOR (2 downto 0); z : out STD_LOGIC_VECTOR (3 downto 0)); end rfidlcd; architecture Behavioral of rfidlcd is signal clock:std_logic:='0'; begin process(clk) variable c:integer range 0 to 417:=0; begin if clk'event and clk= '1' then c:= c+1; if c=417 then clock<= not clock;
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c:=0; end if; end if; end process; process(clock) variable y:bit_vector(59 downto 40); variable t:integer range 0 to 62:=0; variable c:integer range 0 to 5:=5; variable t1:integer range 0 to 1600; variable t2:integer range 0 to 10; begin if clock='1' and clock'event then if (t=0 or t=10 or t=20 or t=30 ) then if sin='0' then t:=t+1; end if; elsif ((t>0 and t<9 )or (t>10 and t<19 ) or (t>20 and t<29 ) or (t>30 and t<39 ))then t:=t+1; elsif (t=40 or t=50) then if sin='0' then y(t):='0'; t:=t+1; end if;
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---checking the start bit and storing

elsif ((t>40 and t<49) or (t>50 and t<59) )then y(t):= sin; t:=t+1; elsif(t=9 or t=19 or t=29 or t=39)then if(sin='1')then t:=t+1; end if;

---storin 8 bit ascii code

elsif ( t=49) then--- checking stop bit and storing it if sin='1' then y(t):='1'; t:=t+1; end if; elsif t=59 then if sin='1' then y(59):='1'; if y="1010000110"&"1001101100" then---comparing card number t:=61; if(c>0)then c:=c-1; t2:=0; end if; elsif y="1010001000"&"1001101100" then---comparing card number t:=60;
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end if; else t:=0; end if; elsif t=61 then if (c>=0)then j<="011"; if(t2<4 )then led<="10"; t1:=t1+1; if (t1=400)then z<="1000";--8 elsif (t1=800)then z<="0010";---2 elsif (t1=1200)then z<="0100";--4 elsif (t1=1599)then z<="0001";--1 t2:=t2+1; t1:=0; end if; -elsif(t2>3 and t2<9)then
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---LCD display for" AUTHENTICATED"

led<="01"; t1:=t1+1; if (t1=400)then t2:=t2+1; z<="0001";--1 elsif (t1=800)then z<="0100";--4 elsif (t1=1200)then z<="0010"; elsif (t1=1599)then z<="1000"; t1:=0; end if; else t:=0; end if;end if; end process; end Behavioral;

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AUTOMATIC TOLL PLAZA SYSTEM

Conclusion
I hereby conclude that after attending the six moth industrial training in advance technology in VLSI technology. I gain a knowledge of circuit designing using VHDL .With the help of XILINX ISE software and vlsi universal board. modules such as serial communication ,gsm, rfid etc. I have become familiar with various

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Apart from above ,I have also made a project of Toll Plaza and done work with advance digital experimental board which is much advanced version of digital trainers board for doing digital experiments . By using this technique there is less wastage of time and money. Rfid is a secure technology. Where the tolled roads are less congested than the parallel free roads, the traffic diversion resulting from the tolls increases congestion on the road system and reduce its usefulness, this technology decrease the traffic jams.

Future Scope
In future, if this module is connecting with GSM, we can send sms to their own mobiles respectably. So they will come to know the detail and they can also made queries regarding their detail.eg how much entries will remain in card.

Bibliography
1. www.xilinx.com 2. www.wikipedia.com 3. www.google.com 4. BHASKER J., VHDL Primer 5. VOLEINI A. PEDRONI, Circuit Design with VHDL

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