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RISC, or Reduced Instruction Set Computer is a type of microprocessor architecture that

utilizes a small, highly-optimized set of instructions, rather than a more specialized set of
instructions often found in other types of architectures
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The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and early
80s The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a
similar philosophy which has become known as RISC
Examples of RISC processors:
O IBM RS6000, MC88100
O C`s Alpha 21064, 21164 and 21264 processors
eatures of RISC Processors:
The standard Ieatures oI RISC processors are listed below:
Certain design features have been characteristic of most RISC processors:
O one cycle execution time: RISC processors have a CPI (clock per instruction) of one
cycle
O pipelining: a techique that allows for simultaneous execution of parts, or stages, of
instructions to more efficiently process instructions;
O large number of registers: the RISC design philosophy generally incorporates a
larger number of registers to prevent in large amounts of interactions with memory
O RISC processors use a small and limited number oI instructions.
O To execute each instruction, there is separate electronic circuitry in the control unit,
which produces all the necessary signals
O It is also called hard-wired approach
O RISC machines mostly uses hardwired control unit.
O RISC processors uses simple addressing modes.
O RISC instruction is oI uniIorm Iixed length.
O Pardwlred conLroller lnsLrucLlons (as opposed Lo mlcrocoded lnsLrucLlons) 1hls ls where 8lSC
really shlnes as hardware lmplemenLaLlon of lnsLrucLlons ls much fasLer and uses less slllcon
real esLaLe Lhan a mlcrosLore area
O % lused or compound lnsLrucLlons whlch are heavlly opLlmlzed for Lhe mosL commonly used
funcLlons
O % lpellned lmplemenLaLlons wlLh goal of execuLlng one lnsLrucLlon (or more) per machlne
cycle
O # Large unlform reglsLer seL
O # no/mlnlmal supporL for mlsallgned accesses
AdvanLages
O RISC processors consume less power and are having high perIormance
O ach instruction is very simple and consistent.
O mlnlmal number of addresslng modes
O


O RISC
O !ronounced same as RISK, it is an acronym Ior Reduced Instruction Set Computer. It is a
type oI microprocessor that has been designed to carry out Iew instructions at the same
time. Till 1980`s hardware manuIacturers were trying to build C!&`s that could carry out
a large number oI instructions at the same instant. But the trend was reversed and
manuIacturers decided to build computers that were capable oI carrying out relatively
very Iew instructions. Instructions being simple and Iew, C!&`s could execute them
quickly. Another advantage oI RISC is the use oI Iewer transistors making them
inexpensive to produce.
O eatures of RISC
O emands less decoding
O &niIorm instruction set
O Identical general purpose registers used in any context
O Simple addressing modes
O Fewer data types in hardware

1yplcal currenL 8lSC chlps are P reclslon ArchlLecLure Sun
SA8C uLC Alpha l8M ower MoLorola/l8M owerC

Common 8lSC characLerlsLlcs

8lSC
Lmphasls on sofLware
Slngleclock
reduced lnsLrucLlon only
8eglsLer Lo reglsLer
LCAu and S1C8L
are lndependenL lnsLrucLlons
Low cycles per second
large code slzes
Spends more LranslsLors
on memory reglsLers