Memory New

Digital Integrated Circuits
A Design Perspective
Semiconductor Memories
Digital Integrated Circuits2nd Memories
Chapter Overview
Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
Semiconductor Memory Classification

Read-Write Memory Non-Volatile Read-Write Memory EPROM E2PROM FLASH Read-Only Memory
Random Access
Non-Random Access FIFO LIFO Shift Register CAM
Mask-Programmed Programmable (PROM)
SRAM DRAM
Digital Integrated Circuits2nd
Memories
Memory Architecture: Decoders

M bits S0 S1 S2 S0 A0 A1 M bits Word 0 Word 1 Word 2 Storage cell Word 0 Word 1 Word 2 Storage cell
SN 2 2 SN 2 1
A K2 1 Word N 2 2 Word N 2 1 K 5 log2N Input-Output (M bits)
Word N 2 2 Word N 2 1
Input-Output (M bits) Decoder reduces the number of select signals
Intuitive architecture for N x M memory Too many select signals: N words == N select signals
K = log2N
Memories
Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH
2L 2 K
Row Decoder
Bit line
Storage cell
AK A K1 1
Word line
AL2 1
M.2K Sense amplifiers / Drivers A0 A K2 1

Amplify swing to rail-to-rail amplitude
Column decoder
Selects appropriate word
Input-Output (M bits)
Memories
Hierarchical Memory Architecture

Block 0 Row address Column address Block address Block i Block P 2 1
Global data bus Control circuitry Block selector Global amplifier/driver I/O
Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings Digital Integrated Circuits2nd Memories
Read-Only Memory Cells

BL VDD WL BL WL BL
WL
BL WL WL
BL
BL WL
GND Diode ROM MOS ROM 1 MOS ROM 2
Memories
MOS OR ROM
BL[0] WL[0] V DD WL[1] BL[1] BL[2] BL[3]
WL[2] V DD WL[3]
V bias Pull-down loads
Memories
MOS NOR ROM

V DD Pull-up devices
WL[0]
GND WL [1] WL [2] GND WL [3]
BL [0]
BL [1]
BL [2]
BL [3]
Memories
MOS NOR ROM Layout

Cell (9.5 x 7)
Programmming using the Active Layer Only
Polysilicon Metal1 Diffusion Metal1 on Diffusion
Memories
MOS NOR ROM Layout

Cell (11 x 7)
Programmming using the Contact Layer Only
Polysilicon Metal1 Diffusion Metal1 on Diffusion
Memories
MOS NAND ROM

V DD Pull-up devices BL [0] WL [0] BL[1] BL[2] BL[3]
WL [1] WL [2]
WL [3]
All word lines high by default with exception of selected row

MOS NAND ROM Layout

Cell (8 x 7)
Programmming using the Metal-1 Layer Only

No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM
Polysilicon Diffusion Metal1 on Diffusion
Memories
NAND ROM Layout

Cell (5 x 6)
Programmming using Implants Only
Polysilicon Threshold-altering implant Metal1 on Diffusion Digital Integrated Circuits2nd Memories
Precharged MOS NOR ROM

f
pre
V DD Precharge devices
WL [0] GND WL [1]
WL [2] GND WL [3]
BL [0]
BL [1]
BL [2]
BL [3]
PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.
Non-Volatile Memories The Floating-gate transistor (FAMOS)

Floating gate Source tox tox n+ Substrate p n+_ S Gate Drain G
Device cross-section
Schematic symbol
Memories
Floating-Gate Transistor Programming

20 V 0V 5V
10 V S
5V
20 V
25V S
0V
2 2.5 V S
5V
Avalanche injection
Removing programming voltage leaves charge trapped
Programming results in higher V T .
Memories
FLOTOX EEPROM
Floating gate Source 2030 nm Gate Drain -10 V 10 V n1 Substrate p 10 nm n1 V GD I
FLOTOX transistor
Fowler-Nordheim I-V characteristic
Memories
EEPROM Cell
BL WL
Absolute threshold control is hard Unprogrammed transistor might be depletion 2 transistor cell
VDD
Memories
Flash EEPROM
Control gate
Floating gate erasure n 1 source Thin tunneling oxide
programming p-substrate
n 1 drain
Many other options

Characteristics of State-of-the-art NVM
Memories
Read-Write Memories (RAM)

STATIC (SRAM)
Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential
DYNAMIC (DRAM)
Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
6-transistor CMOS SRAM Cell

WL V DD M2 M5 Q M1 BL M4 Q M6
M3 BL
Memories
CMOS SRAM Analysis (Read)

WL
V DD
BL Q= 0 M5 V DD Cbit M4 Q= 1 V DD M6 V DD Cbit BL
M1
Memories
CMOS SRAM Analysis (Write)

WL V DD M4 M5 Q= 0 Q= 1 M1 BL = 1 V DD BL = 0 M6
Memories
CMOS SRAM Analysis (Write)
Memories
6T-SRAM Layout
VDD
M2 M4
Q
M1 M3
GND
M5 M6
WL
BL
BL
Memories
Resistance-load SRAM Cell

WL V DD RL M3 BL Q RL Q M4 BL
M1
M2
Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem
SRAM Characteristics
Memories
Pessimistic Design Hurts Performance

200
Number of dies
(150nm CMOS Measurements, 110C) nominal corner
150 100
worst-case corner
50 0
Normalized IOFF
Substantial variation in leakage across dies 4X variation between nominal and worst-case leakage Performance determined at nominal leakage Robustness determined at worst-case leakage
31
Memories: On-chip SRAMs

100%
% of chip area
Cache
80% 60% 40% 20% 0%
Cache Core Core
% of chip area taken by SRAM cache
Source: Intel 0.5 0.35
Technology (micron)
0.25
0.18
0.13
0.10
On-chip memory size is increasing with scaling Challenges: Leakage and Variability
32
Global and Local Variations

Random Dopant Fluctuation
Vt LOCAL
LOCAL
intra-die
Vt GLOBAL
GLOBAL
inter-die
Vt = Vt GLOBAL + Vt LOCAL
Parametric Failures: Read Failure

WL Voltage
33
VL WL VR=VREAD
VTRIPRD
AXL
+
PL PR
VR=0
VREAD
AXR
VL=1
-
NL NR
Time ->
-
BL
+
Voltage BR
VR WL VL
Time ->
PRF = P(VREAD > VTRIPRD )
Read failure => Flipping of Cell Data while Reading
34
Parametric Failures in SRAM

WL PL 1 NL BL High-Vt PR 0 NR Low-Vt BR AXR
AXL
Parametric failures
Read Failures Write Failures Access Failures Hold Failures
Test & Repair using Redundancy
Faulty chips
Working chips
Parametric failures can degrade SRAM yield
Process Variations in On-chip SRAM

350 300
35
Yield 33%
Chip Count
250 200 150 100 50 0 157 262 367 419 524
Fault statistics
Vt 30mv, using BPTM 45nm technology
Simulation of an 64KB Cache

A. Agarwal, et. al, JSSC, 05
577
210
315
472
629
682
105
734
52
839
944
996
Number of faulty cells (NFaulty-Cells)
Parametric failures Yield degradation
1049
786
890
36
Post-Silicon Repair: Proposed Approach
LOCAL LOCAL
intra-die intra-die
GLOBAL
inter-die
Apply correction to the global variation to reduce number of failures due to local variations
37
Inter-die Variation & Cell Failures

1
LowVt Corners
Read failure Hold failure
HighVt Corners
GLOBAL
Access failure Write failure
inter-die Vt shift (Vth-GLOBAL)
Inter-die Variation & Memory Failure

LVT Nom. Vt HVT
38
BPTM 70nm Devices
Memory failure probabilities are high when inter-die shift in process is high
Self-Repairing SRAM Array

LVT Region A LVT Corner Region A Nom. Vt Region B HVT Region C Region C HVT Corner
39
Read & Hold failures dominate
Access & Write failures dominate
Reduce RF & HF
Reduce AF & WF
Reduce the dominant failures at different inter-die corners to increase width of low failure region
Self-Repairing SRAM Array

LVT Region A Nom. Vt Region B HVT Region C
40
RBB ZBB
FBB
Reduce the dominant failures at different inter-die corners to increase width of low failure region
41
How to identify the inter-die Vt corner under a large intra-die variation ?

WL VDD
BL
GND
BR
Monitor circuit parameters, e.g. leakage current Effect of inter-die variation can be masked by intra-die variation
42
Array Leakage Monitoring
Y 1 X Y = X i => = Y i =1 N X
N
Adding a large number of random variables reduces the effect of intra-die variation
Leakage of entire SRAM array is a reliable indicator of the inter-die Vt corner
Self-Repair using Leakage Monitoring

V Bypass Switch DD V V
43
Calibrate Signal
On-chip Leakage Monitor
V out
REF1
REF2
VOUT SRAM ARRAY
Comparator SRAM Array Body bias
Body-Bias selection
FBB ZBB RBB
Entire array leakage is monitored to detect inter-die corner and proper body-bias is selected
Yield Enhancement using Self-Repair
44
Self-Repairing SRAM using body-bias can significantly improve design yield
45
Test-Chip of Self-Repairing SRAM

VCO
VCO Isolated cell 16 KB block
64 KB LVT Array
Sensor + Ref. gen. BB gen
Technology : IBM 0.13 m
128KB SRAM
Dual-Vt Triple-well tech. Number of Trans: ~ 7 million Die size: 16mm2 VLSI CKT Symp. 2006, ITC 2005
Simulation results for 1MB array designed in IBM 0.13m
Continuous vs Quantized Body Bias

Memory failure probability 1
Memory failure probability
46
V body (1 ) < V body ( 2 )

# of dies
Vt ~ 200 mV
-0.2 -0.1 0.1 0.2 0 Inter-die Vt shift [mV]
-0.2
0.1 -0.1 0.2 0 Inter-die Vt shift [mV]
Continuous body biasing scheme Pros: better yield, Cons: higher cost & design complexity Finite width of low PMEM region & sharp transition Large allowable range for body bias stability requirement for body bias is less critical
V Vt ~30 m
47
Continuous vs Quantized Body Bias
Quantized (3 Level: FBB, ZBB, RBB) body bias scheme is a cost effective solution with good yield enhancement possibility
Read Failure Measurement

80 70
140
# of failures (out of 1792)
f=400MHz VWL = 2.1V
60 50 40 30 20 10 0 2 1.7
HVT LVT
Low Vt Cell
120 100 80 60 40 20 0
1.5
f=400MHz VWL = 2.3V Vcell = 2.0V
-1
Cell Supply Voltage
NMOS Body Bias
Low Vt array shows more number of read failures Application of reverse body bias to NMOS (RBB) reduces number of read failures
Hold Failure Measurement

160
120
140
120 100 80 60 40 20 0 0.2
HVT LVT
Low Vt Cell
100 80 60 40 20 0 0 -1
Hold voltage = 0.08V
0.1
0.08
Hold Voltage [V]
NMOS Body Bias [V]
Low Vt array shows more number of hold failures Application of reverse body bias to NMOS (RBB) reduces number of hold failures
Process Tolerance: Register Files
Process Compensating Dynamic Circuit Technology

Conventional Static Keeper
clk LBL0 RS0 RS1 RS7 LBL1 N0
...
D0
D1
D7
Keeper upsizing degrades average performance
Process Compensating Dynamic Circuit Technology

3-bit programmable keeper
b[2:0] clk W s 2W s 4W s LBL0 RS0 RS1 RS7 LBL1 N0
...
D0
D1
D7
C. Kim et al. , VLSI Circuits Symp. 03
Opportunistic speedup via keeper downsizing
Robustness Squeeze
250 Number of dies 200 150 100 50 0 0.7 0.8 0.9 1.0 1.1 Normalized DC robustness 1.2
saved dies Noise floor
Conventional This work
5X reduction in robustness failing dies
Delay Squeeze
300 Number of dies 250 200 150 100 50 0 0.8 0.9 1.0 1.1 Normalized delay 1.2
Conventional This work
PCD = 0.90 Conv. = 1.00 : avg. delay
10% opportunistic speedup
Self-Contained Process Compensation

Fab Wafer test
Process detection
Leakage measurement On-die leakage sensor Program PCD using fuses
Customer
Package test
Burn in
Assembly
On-Die Leakage Sensor For Measuring Process Variation

current reference
73m
compa rators
VBIAS gen.
NMOS device
test interface
83m
C. Kim et al. , VLSI Circuits Symp. 04
High leakage sensing gain Compact analog design sharing bias generators
current mirrors
6-Channel Leakage Sensor Testchip

WP VBIAS IREF + 2WP 3WP 4WP 6WP 9WP WN WN WN WN WN WN V1 V2 V3 V1 V4 V5 V2 V4 V6 V1 V2 V3 V4 V5 V6 OUT[2]
VSEN1
VSEN2
VSEN3
VSEN4
VSEN5
VSEN6
VREF + + -
OUT[1]
+ -
+ -
+ -
+ -
Bubble rejection circuit
OUT[0]
Incremental mirroring ratio for multi-bit resolution leakage sensing Shared bias generators compact design Process-voltage insensitive IREF, VBIAS gen.
On-Die Leakage Sensor Test Chip

current reference VBIAS gen.
NMOS devices
current mirrors
compar ators
test interface
Technology VDD Resolution Power consumption Dimensions 90nm dual Vt CMOS 1.2V 7 levels 0.66 mW @80C 83 X 73 m2
Leakage Binning Results
001 010 011 100
101
110
111
Output codes from leakage sensor
3-Transistor DRAM Cell

BL 1 WWL RWL M3 M1 CS X M2 WWL RWL X BL 1 BL 2 V DD V DD 2 V T DV V DD 2 V T BL 2
No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = VWWL-VTn Digital Integrated Circuits2nd Memories
3T-DRAM Layout
BL2 BL1 GND
RWL
M3 M2
WWL
M1
Memories
1-Transistor DRAM Cell

BL WL WL M1 CS BL V DD /2 CBL V DD V /2 sensing DD X GND V DD 2 V T Write 1 Read 1
Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance
CS V = VBL V PRE = V BIT V PRE -----------C S + CBL
Voltage swing is small; typically around 250 mV.
Memories
DRAM Cell Observations

1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD
Sense Amp Operation

V BL
V(1) V PRE
DV(1)
V(0) Sense amp activated Word line activated t
Memories
1-T DRAM Cell

Capacitor M 1 word line Poly n+ Poly n+ Inversion layer induced by plate bias SiO2 Field Oxide Diffused bit line Polysilicon gate Polysilicon plate
Metal word line
Cross-section
Layout
Expensive in Area
Uses Polysilicon-Diffusion Capacitance
Memories
SEM of poly-diffusion capacitor 1T-DRAM
Memories
Advanced 1T DRAM Cells

Word line Insulating Layer Cell plate Capacitor dielectric layer
Cell Plate Si
Capacitor Insulator Storage Node Poly 2nd Field Oxide
Refilling Poly
Transfer gate
Isolation Storage electrode
Si Substrate
Trench Cell
Stacked-capacitor Cell
Memories
Static CAM Memory Cell

Bit Word CAM CAM Bit Bit Bit Bit M4 M8 M6

Bit M9 M7 M5
Word Word CAM CAM Match S M3 int S M2 M1
Wired-NOR Match Line
Memories
CAM in Cache Memory
CAM ARRAY
H i t L o g i c
SRAM ARRAY
Input Drivers
Sense Amps / Input Drivers
Address
Tag
Hit
R/W
Data
Memories
Periphery
Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry
Memories
Row Decoders
Collection of 2M complex logic gates Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
Memories
Hierarchical Decoders
Multi-stage implementation improves performance
WL 1
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1
A 2A 3 A 2A 3 A 2A 3 A 2A 3
NAND decoder using 2-input pre-decoders
A1 A0
A0
A1
A3 A2
A2
A3
Memories
Dynamic Decoders
Precharge devices GND GND
VDD WL3
WL 3 WL 2 WL 1
VDD
VDD
WL 2
V DD WL 0
WL 1
WL 0 VDD A0 A0 A1 A1
A0
A0
A1
A1
2-input NOR decoder
2-input NAND decoder
Memories
4-input pass-transistor based column decoder BL BL BL BL

0 1 2 3
A0
S0 S1 S2
A1
2 i n p u t N O R d e c o d e r
S3
Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count
Memories
4-to-1 tree based column decoder

BL 0 BL 1 BL 2 BL 3 A0 A0
A1
A1
D
Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches
Memories
Decoder for circular shift-register

V DD WL R V DD
0
V DD WL
1
V DD
V DD WL
2
V DD
V DD
f f
f f R
f f
f f R
f f
Memories
Sense Amplifiers
C V tp = ---------------Iav large make V as small as possible
small
Idea: Use Sense Amplifer small transition input s.a. output
Memories
Differential Sense Amplifier

V DD M3 M4 y bit M1 M2 bit Out
SE
M5
Directly applicable to SRAMs

Differential Sensing SRAM

V DD PC V DD BL EQ WL i x BL y M3 M1 SE M2 M5 V DD M4 2 x x SE V DD 2 y 2 x
SE SRAM cell i Diff. x Sense 2 x Amp V DD y Output
SE Output (a) SRAM sensing scheme (b) two stage differential amplifier
Memories
Latch-Based Sense Amplifier (DRAM)

EQ BL VDD SE BL
SE
Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.
Charge-Redistribution Amplifier
V ref VL M2 M3 VS C small Transient Response
2.5
M1 C large
Concept
V
2.0 1.5 1.0 0.5 0.0 0.0
V in VL
VS
V ref 5 3V 1.00 2.00 time (nsec) 3.00
Memories
Charge-Redistribution Amplifier V EPROM

DD
SE
M4 Out
Load
V casc
M3
Cout
Cascode device
Ccol WLC M2 BL WL
Column decoder
M1
CBL
EPROM array
Memories
Single-to-Differential Conversion
WL BL Cell x Diff. S.A. 2 x
1 2
V ref
Output
How to make a good Vref?

Open bitline architecture with dummy cells

EQ L L1 L0 SE
BLL V DD
R0
R1
BLR SE CS CS CS Dummy cell
CS
CS
CS
Dummy cell
Memories
DRAM Read Process with Dummy Cell

3 3 2 BL
V V
2 BL 1 BL
BL
1 t (ns)
1 t (ns)
reading 0
3 EQ 2
V
reading 1
WL
SE 1
1 t (ns)
control signals
Memories
Voltage Regulator
VDD Mdrive VDL
VREF Vbias
Equivalent Model
VREF
Mdrive
VDL
Charge Pump
V DD VB CLK A M1 B M2 V load Cload V load 0V V DD 2 V T 0V 2V DD 2 V T
Cpump
Memories
DRAM Timing
Memories
RDRAM Architecture
Bus Clocks Data bus k k3 l
n e t w o r k
memory array
Column Row
demux demux
packet dec. packet dec.
Memories
Address Transition Detection

V DD DELAY td DELAY td DELAY td
A0
ATD
ATD
A1
A N2 1
Memories
Reliability and Yield
Memories
Sensing Parameters in DRAM

1000
V smax (mv)
s m a x
C D(1F)
100
C S(1F)
Q S(1C)
10 V DD (V)
Q S 5 C S V DD / 2 V smax 5 Q S / (C S 1 C D )
4K
64K
1M 16M 256M 4G
/ chip)
64G
Memory Capacity (bits Digital Integrated Circuits2nd
From [Itoh01]
Memories
Noise Sources in 1T DRam

BL CWBL WL leakage CS electrode substrate Adjacent BL
a -particles
Ccross
Memories
Open Bit-line Architecture Cross Coupling
EQ
WL 1 BL C BL C
WL 0
WL C WBL D Sense Amplifier
C WBL
WL D
WL 0
WL 1 BL C BL
Memories
Folded-Bitline Architecture
WL 1 BL CBL C CBL CWBL C C C C C WL 1 WL 0 C
WBL
WL 0
WL D
WL D x Sense EQ Amplifier x y y
BL
Memories
Transposed-Bitline Architecture
Ccross BL 9 BL BL BL 99 (a) Straightforward bit-line routing Ccross BL 9 BL BL BL 99 (b) Transposed bit-line architecture
SA
SA
Alpha-particles (or Neutrons)

a -particle WL BL n1
1 1 1 2 2 1 1 2 2 2 2
V DD SiO 2
1 Particle ~ 1 Million Carriers

Yield
Yield curves at different stages of process maturity (from [Veendrick92])
Memories
Redundancy
Redundant rows Redundant columns Row Address : Memory Array
R o w D e c o d e r
Fuse Bank
Column Decoder
Column Address
Memories
Error-Correcting Codes
Example: Hamming Codes
e.g. B3 Wrong with 1 1 0 =3
Memories
Redundancy and Error Correction
Memories
Sources of Power Dissipation in Memories

V DD CHIP nC DE V INT f C PT V INT f I DCP selected I DD 5 SC iDV if1S I DCP m mi act
n m(n 2 1)i hld non-selected ARRAY mC DE V INT f COLUMN DEC V SS
ROW DEC PERIPHERY
From [Itoh00]
Memories
Data Retention in SRAM

1.30u 1.10u 0.13 mm CMOS 900n
Ileakage
700n 500n 300n 100n 0.00 .600 1.20 1.80
Factor 7
0.18 mm CMOS
VDD
SRAM leakage increases with technology scaling

Suppressing Leakage in SRAM

V DD low-threshold transistor sleep V DD,int SRAM cell SRAM cell SRAM cell sleep V DD,int SRAM cell SRAM cell SRAM cell V DD V DDL
sleep
V SS,int
Inserting Extra Resistance

Reducing the supply voltage

Memories
Data Retention in DRAM

10
1
100 10 Current (A)

21
I ACT I AC
102 2 102 3 10 10
24 25
I DC
Cycle time : 150 ns T 5 75 C,S 5 97 mV/dec.
102 6
15M
64M
255M
1G
4G
15G
64G
Capacity (bit) 3.3 2.5 2.0 1.5 1.2 1.0 0.8
Operating voltage (V) 0.53 0.40 0.32 0.24 0.19 0.16 0.13
Extrapolated threshold voltage at 25 C (V)
From [Itoh00]
Memories
Case Studies
Programmable Logic Array SRAM Flash Memory
Memories
PLA versus ROM

Programmable Logic Array
structured approach to random logic two level logic implementation NOR-NOR (product of sums) NAND-NAND (sum of products) IDENTICAL TO ROM!
Main difference
ROM: fully populated PLA: one element per minterm Note: Importance of PLAs has drastically reduced 1. slow 2. better software techniques (mutli-level logic synthesis)
But
Memories
Programmable Logic Array

Pseudo-NMOS PLA
GND GND GND GND V DD GND
GND
GND
V DD
X0
X0
X1
X1
X2
X2
f0
f1
AND-plane
OR-plane
Memories
Dynamic PLA
f AND GND V DD f
OR
f f AND V DD X0 X0 X1 X1 X2 X2 f0 f 1 GND
OR
AND-plane
OR-plane
Memories
Clock Signal Generation for self-timed dynamic PLA

f f f Dummy AND row
AND
AND
tpre teval f
OR
AND
Dummy AND row
OR
(a) Clock signals
(b) Timing generation circuitry
Memories
PLA Layout
VDD And-Plane Or-Plane GND
x0 x0 x1 x1 x2 x2 Pull-up devices
f0 f1 Pull-up devices
Memories
4 Mbit SRAM Hierarchical Word-line Architecture

Global word line Sub-global word line Local word line Block group select Block select
Local word line

Memory cell Block 0 Block 1 Block select Block 2...
Memories
Bit-line Circuitry
Bit-line load Block select ATD
BEQ Local WL Memory cell B /T CD CD I/O line I/O Sense amplifier B /T CD I/O
Memories
Sense Amplifier (and Waveforms)

Address
I /O SEQ BS I /O
ATD
Block select ATD
BEQ Vdd I/O Lines GND SEQ

SEQ
SA
BS
SA SEQ
SEQ
SEQ DATA Dei
Vdd SA, SA GND DATA
BS
Data-cut
Memories
1 Gbit Flash Memory

512Mb Memory Array BL0 BL1 BL16895
Word Line Driver
512Mb Memory Array

BL16996 BL16897 BL33791
Word Line Driver Word Line Driver
WL0 SGS Block0 Block1023 BLT0 BLT1
Block0 Block1023
Bit Line Control Circuit Sense Latches (10241 32) 3 8 Data Caches (10241 32) 3 8
Sense Latches (10241 32) 3 8 Data Caches (10241 32) 3 8
I/O
I/O
From [Nakamura02]
Word Line Driver
SGD WL31
Memories
Writing Flash Memory

Verify level 5 0.8 V Word-line level 5 4.5 V
Number of memory cells
108 106 104 102

R e a d l e v e l ( 4 . 5 V )
Result of 4 times program

N u m b e r o f c e l l s
100 0V
1V
2V
3V
4V
0V
1V 2V 3V 4V Vt of memory cells
Vt of memory cells
Evolution of thresholds
Final Distribution
From [Nakamura02]
Memories
125mm2 1Gbit NAND Flash Memory

2kB Page buffer & cache
Charge pump
32 word lines x 1024 blocks
10.7mm
16896 bit lines
11.7mm
From [Nakamura02]
Memories
125mm2 1Gbit NAND Flash Memory

Technology Technology 0.13m p-sub CMOS triple-well 0.13m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al 1poly, 1polycide, 1W, 2Al Cell size 0.077m2 Cell size 0.077m2 Chip size 125.2mm2 Chip size 125.2mm2 Organization 2112 x 8b x 64 page x 1k block Organization 2112 x 8b x 64 page x 1k block Power supply 2.7V-3.6V Power supply 2.7V-3.6V Cycle time 50ns Cycle time 50ns Read time 25s Read time 25s Program time 200s //page Program time 200s page Erase time 2ms //block Erase time 2ms block
From [Nakamura02]
Memories
Semiconductor Memory Trends (up to the 90s)
Memory Size as a function of time: x 4 every three years

Semiconductor Memory Trends (updated)
From [Itoh01]
Memories
Trends in Memory Cell Area
From [Itoh01]
Memories
Semiconductor Memory Trends
Technology feature size for different SRAM generations


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Digital Integrated Circuits

Semiconductor Memory Classification

Non-Random Access FIFO LIFO Shift Register CAM

Mask-Programmed Programmable (PROM)

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Memory Architecture: Decoders

A K2 1 Word N 2 2 Word N 2 1 K 5 log2N Input-Output (M bits)

Input-Output (M bits) Decoder reduces the number of select signals

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Array-Structured Memory Architecture

M.2K Sense amplifiers / Drivers A0 A K2 1

Selects appropriate word

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Hierarchical Memory Architecture

Read-Only Memory Cells

GND Diode ROM MOS ROM 1 MOS ROM 2

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V bias Pull-down loads

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MOS NOR ROM

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MOS NOR ROM Layout

Programmming using the Active Layer Only

Polysilicon Metal1 Diffusion Metal1 on Diffusion

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MOS NOR ROM Layout

Programmming using the Contact Layer Only

Polysilicon Metal1 Diffusion Metal1 on Diffusion

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MOS NAND ROM

All word lines high by default with exception of selected row

MOS NAND ROM Layout

Programmming using the Metal-1 Layer Only

Polysilicon Diffusion Metal1 on Diffusion

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NAND ROM Layout

Programmming using Implants Only

Polysilicon Threshold-altering implant Metal1 on Diffusion Digital Integrated Circuits2nd Memories

Precharged MOS NOR ROM

WL [0] GND WL [1]

WL [2] GND WL [3]

Non-Volatile Memories The Floating-gate transistor (FAMOS)

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Floating-Gate Transistor Programming

Removing programming voltage leaves charge trapped

Programming results in higher V T .

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Fowler-Nordheim I-V characteristic

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Many other options

Characteristics of State-of-the-art NVM

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Read-Write Memories (RAM)

6-transistor CMOS SRAM Cell

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CMOS SRAM Analysis (Read)

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CMOS SRAM Analysis (Write)

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CMOS SRAM Analysis (Write)

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