Exam 3 Study Questions

Chapters 15-18 of Nelsons Text, Cascadable Counters, LC-3, and UARTs

August 9, 2007 1. Consider the state graph shown below, consisting of four states and the signals V, W, X, Y, and Z. Answer the following questions regarding the state graph: a. b. c. d. Which signals are inputs? Which signals are outputs? For each output, identify if it is a Moore or Mealy output? For each state, identify if it is complete (show this algebraically). Is the overall graph complete? e. For each state identify if it is conflict free (show this algebraically). Is the overall graph conflict free?

XY S0 XY/W,Z V S3 XY XY S2 XY
2. Consider the state diagram below, with input X, output Z, and state bits A and B. Call the left state bit A and the right state bit B. Derive the minimized equations for NA, NB, and Z.

X+Y/Z X Y XY Y S1 Z

1/0 00 0/0 0/1 0/0 1/0 01

11 1/1

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3. The following graph has an unusual characteristic. Answer the following questions regarding the circuit: a. What is unusual about this graph? b. Can a circuit be built which represents this graph? If so, what would the circuit do, assuming it starts in state S0? c. Is the graph complete? Is it conflict free?

S0 Z Z

S1 Z

4. Consider the state machine shown below, with inputs X and S, outputs Y and Z, and state bits A and B. With A as the left state bit and B as the right state bit, assume the encoding {S0, S1, S2, S3} = {00, 11, 10, 01}. Design the state machine for the graph. This implies writing the transition table and deriving the minimized next-state logic (NA, NB) for both state bits as well as the outputs Y and Z. Assume that the S input takes precedence over X.

S X/Y Z S3 X X

Z S0

X X S1 X S2 X

5. Using the same state diagram as the previous problem, consider how you would design the circuit using T flip flops or JK flip flops. Expand the transition table to include columns for TA, TB and JAKA, JBKB. Derive the minimized equations for TA then JA and KA. Do the equations for outputs Y and Z change when using T flip flops or JK flip flops?

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6. Design a 0011 detector circuit. Start by drawing the state diagram. Then convert the state diagram to a transition table. Finally, derive the next-state and output logic. The circuit should have an input X and an output Z, which goes high concurrently with the last bit of the detected sequence. The detector should be capable of immediately detecting another occurrence of the sequence. Use a standard binary state encoding. 7. Consider the simplified transition table below, then do the following: a. Draw the state diagram for the transition table. b. Give the fully expanded (or unfolded) version of this simplified transition table. c. Now see if you can generate the simplified transition table from the state graph without looking at the example below. A 0 1 B 0 1 Q1 0 0 0 1 1 Q0 0 0 1 0 0 N1 0 0 1 1 0 N0 0 1 0 0 0 Y 0 0 1 0 0 Z 0 0 0 1 1

8. There are basically two ways to provide a finite state machine with a synchronous reset capability. What are they? 9. Consider the state machine shown below, with inputs X and S and outputs Y and Z. Design the state machine for the graph, using a one-hot encoding. This implies deriving the next state logic (N1, N0) for all state bits as well as for outputs Y and Z. Note that you should be able to do this by inspection of the state graph, without a transition table. Assume that the S input takes precedence over X.

S X/Y Z D X X

Z A

X X B X C X

10. Which generally has the simplest IFL and OFL, a one-hot encoding, a gray code encoding, or a standard binary encoding? WSF Page 3 of 5

11. What is an asynchronous input? 12. What are the two dangers of asynchronous inputs? In other words, what are the two problems discussed in class that asynchronous inputs can cause? 13. What is metastability? 14. What are the two reasons why asynchronous inputs can cause a state machine to make invalid state transitions? 15. What are the two solutions we discussed to deal with metastability? How effective are they? 16. What are the two solutions we discussed to deal with invalid state transitions caused by asynchronous inputs? 17. Which solution works for both metastability and the invalid state transition problem? 18. Sometimes we must generate signals that will be seen as asynchronous by another circuit. These signals must be free of any kind of glitches or false outputs. Describe at least two ways we can ensure that our state machine outputs will look like good asynchronous signals to other circuits. 19. What is a clock domain? How many clock domains does a globally synchronous design have? 20. What is the difference between a synchronous cascaded counter and an asynchronous cascaded counter? 21. Assume you have in your possession a 4-bit counter module. It has synchronous inputs inc and rst and output count[3:0]. Show how you would use it to design a mod-118 counter with a rollover output signal. 22. The fetch stage of the LC-3 processor can be divided into four specific steps. What are they, which control signals are needed for each, and which of the steps can share the same clock cycle? 23. Which control signals are actively used by the LC-3 control unit to execute the instruction 1010011001110101? Do not consider the fetch part of the instruction in your response. 24. How many bits wide is the system bus of LC-3 datapath? 25. Is the LC-3 data path capable of reading and writing memory on the same clock cycle? 26. Which of the LC-3 instructions cause the NZP flags to be updated? 27. What kind of adder is needed in the effective address block of the LC-3? In other words: how many numbers does it add? How many bits is each number? Is it an unsigned, twos complement, ones complement, or signed magnitude adder? Does it have any control signals? WSF Page 4 of 5

28. Assume you have an application where you must download images over a UART connection. The UART is configured to 115,200 baud, 8 data bits, 1 stop bit, no parity. Each image is exactly 900 KB. How many data bits per second (bps) will the UART actually be able to transfer? How many seconds will it take to download each image? Hint: Recall that a kilobyte (KB) is 1024 bytes. 29. What is the purpose of the parity bit? Under what circumstances will the parity bit fail to fulfill its purpose?

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