Clockgate Enable Path Timing

CTS / hold

Typically in ideal mode, the insertion delay to a clock gate is

equal to the insertion delay for the entire clock tree (derived from force timing latency -type network on the clock root) In computed mode, the actual insertion delay to a clockgate is always
less than that of the sinks in its fanout

Ideal timing mode thinks that clockgate enable paths have a

full cycle to meet timing, which is optimistic, causing underoptimization on critical clockgate paths, resulting in possible timing failures once in computed mode To prevent this optimism, we should make pre-clock tree synthesis optimizations aware of the actual insertion delay to the clockgate

November 22, 2006 - Magma Confidential - 87

Clockgate Latency Example

CTS / hold
1ns network latency on CLK Enable Path sees 1ns launch AT and 1ns capture AT Call run timing adjust latency -clockgates

forced latency ideal AT

Now enable path sees 1ns launch AT and 684ps capture AT 1ns 0ns -316ps +1ns = 684ps 1ns +316ps 1ns 1ns

CLK

1ns

AT at sinks does not change

Clockgate Enable Path

November 22, 2006 - Magma Confidential - 88

Early Clockgate Latency Modeling

CTS / hold

run timing adjust latency -clockgates Options:

-clockgates: Create network latencies for clockgates

based on actual insertion delay to clockgates -no_source: Supresses default behavior of adjusting network / source / I/O latencies on clock roots -file: Write results to a file so they can be sourced earlier in the flow

November 22, 2006 - Magma Confidential - 89

Early Clockgate Latency Modeling (contd)

CTS / hold

Estimated latencies are based on actual clock insertion

delays, so this command must be run post-clock tree synthesis Then, latencies can be applied pre-clock tree synthesis to allow
optimization to take advantage of proper timing

Ex: Clock arrives at $m/B1/A at 700ps.

that?
1n latency on clock2 pin name -----------clock:clock1 clock1 B2/A B2/Z D3/C AT ---0 0 1000 1000 1000 delay ----0 1000 0 0

How do we model

1n latency on clock1 -300p latency on B1/A 300p latency on B1/Z pin name -----------clock:clock1 clock1 B1/A B1/Z D1/C AT ---0 0 700 1000 1000 delay ----0 700 300 0

November 22, 2006 - Magma Confidential - 90

Clockgate Latency Modeling: Recommended Flows

CTS / hold

Multi-pass flow

Anytime netlist, constraints, or floorplan changes in a

Single-pass flow

major way, generate a file of latencies after fix clock using run timing adjust latency -clockgates On a subsequent run, source the file before fix-cell

After global placement in fix-cell, call run route clock Call run timing adjust latency -clockgates Then run unroute clock to remove the clock tree

November 22, 2006 - Magma Confidential - 91