NUST School of Electrical Engineering and Computer Science

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EE 241
Prerequisite: None

Digital Logic Design

Fall 2011
Email:nasir.gohar@seecs.edu.pk Tel: 051-9085-2250 Office Hours Fri: 15:00-16:50 Lab Instructor: Mr. Yasir Ateeq

Instructor: Dr. Nasir ud Din Gohar Office: Faculty Bloc k Room # A119 Time and Place: Tue: CR-10 09:00-09:50 & 15:00-15:30 Thu: CR-11 15:00-15:50 Lab: Wed: 09:00-11:50

Course Objective:
This course aims to provide the electronic engineering students their first exposure to design digital circuits using conventional as well as modern design techniques. Having gone thru the basic logic gates, they will learn how to implement any digital electronic circuit using these basic gates. Building on their skills in these basic gates, they will learn how to design combinational as well as sequential logic circuits. They will also be exposed to logic circuit two-level optimization/simplification using K-Maps/QM reduction techniques. [Moreover, side-by-side, they will learn how to design and simulate these logic circuits using CAD tools such as ModelSim while programming in Verilog HDL. Finally, if time permits, use of ROM as well as other PLDs to design simple logic circuits will be discussed leading to their first exposure to FPGA technology.]

Text Book:
1.

Digital Design, 4th Edition, by Morris Mano & Michael D. Ciletti, by Pearson Education, Inc. Prentice Hall, 2007. [ISBN 0 13 -198924-3]

Reference Books: (Although not limited to but to name a few)

1. 2. 3. Logic and Computer Design Fundamentals, 2nd Edition, by M. Mano and C. Kime, published by Prentice Hall, 2000. [ISBN 0-13-012468-0] Digital Systems: Principles and Applications, 7th Ed. by Tocci and Widmer, published by Prentice Hall, 1998. [ISBN 0-13-649492-7] Digital Fundamentals, 7th Ed. By T. L. Floyd, , published by Prentice Hall, Inc. 2000. [ISBN 0-13-085268-6]

Main Topics to be Covered:

1. 2. 3. Introduction Number Systems and Their Conversion Combinational Logic Circuits o Boolean Algebra o Logic Gates o K Map/QM Techniques 4. 5. 6. 7. Combinational Logic Design Sequential Logic Design Verilog HDL Representation and Design of Simple Digital Systems (Optional) Memory and Programmable Logic Devices (PLD) and their Applications (Optional)

Policy Matters:
1. 2. 3. 4. 5. 6. Assignments [02%]: Number of assignments will be issued and each will be due exactly one week after its issue date unless otherwise specified. No late submissions will be allowed. Quizzes [08%]: At least 6 Quizzes will be conducted in class in the first 15-20 minutes, and late comers will suffer. No make-up provisions. Labs/Mini-Project [20+5=25%]. Lab would be conducted on weekly basis. During the last leg of the course, Class Projects will be issued. Project Report will be due within 4 weeks from the issue date. No late submission allowed. Two One Hour Tests [12.5+12.5 =25%] during 6th week and 12th week. Dont ask for any postponement, which is impossible. Final Test [40%] in 18th week. It is mandatory to maintain at least 75% class attendance to be allowed to sit in Final Test. Please try to observe Instructor/TA Office Hours for any help.

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Digital Logic and Design-Lecture Breakdown

Week No 1. Lecture No 1. Topics Introduction: Digital Systems and motivation for study Number Systems: Binary, Octal, Decimal and Hexadecimal Numbers and Base Conversions. Complements: Subtraction of Unsigned Numbers using Complements. Signed Binary Numbers, Arithmetic Addition and Subtraction of Signed Binary Numbers. Binary Codes Binary storage and Registers: Binary Logic; Definition of Binary Logic and Logic Gates. Introduction: Boolean Algebra: Basic and Axiomatic Definition of Boolean Algebra; TwoValued Boolean Algebra. Basic Theorems and Properties of Boolean Algebra Boolean Functions. Canonical and Standard Forms. Other Logic Operations. Digital Logic Gates and Integrated Circuits. Introduction: The K-Map Method; Two, and Three Variable K-Maps. Sum-of-Products and Product-of-Sums simplification using FourVariable K-Maps; Essential and Non-essential Prime Implicants. Five-Variable K-Maps; Sumof-Products and Product-ofSums simplification using Five-Variable K-Maps. Text Book Reference 1-1 Other References Remarks

2.

1-2,1-3,&1-4

3.

1-5

2.

4*.

1-6

5*. 6.

1-7 1-8&1-9

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2-1&2-2

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2-3

3.

9. 10. 11.

2-4 2-5 2-6 2-7&2-8 3-1

4.

12. 13.

14.

3-2&3-4

5.

15.

3-3

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16. 17. 6. 7. 18. 19. 20.

Dont Care conditions. NAND and NOR implementations. Other Two-Level implementations. Exclusive-OR function: Parity Generation and Checking. Verilog Hardware Description Language (Verilog HDL): Design Entry using Source Code (Optional) Introduction: Combinational Circuits and their Analysis Procedure. Design Procedure with Code Conversion Example. Half and Full Adders: 4-BIT Adder Design using Full Adders. Design of 4-Bit Adder using Carry Look-ahead Generator. Binary Sub-tractor and Overflow Decimal Adder. Binary Multiplier. Magnitude Comparator. Decoders. Encoders. Multiplexers and Tri-State Gates. HDL for Combinational Circuits (Optional) HDL for Combinational Circuits (Optional) Introduction: Sequential Circuits and different types of Latches. Flip-Flops: Edge-Triggered D Flip-Flop. Other Flip-Flops. Analysis of ClockedSequential Circuits. Analysis with D Flip-Flops, JK Flip-Flops, and T FlipFlops.

3-5 3-6 3-7 3-8 3-9 1 OHT

st

8.

21.

4-1&4-2

22. 23.

4-3 4-4

9.

24. 25. 26.

4-4 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-11 5-1&5-2

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27. 28. 29.

11.

30. 31. 32.

12.

33. 34.

35. 13. 14. 36. 37.

5-3 5-3 5-4 2 OHT

nd

38.

5-4

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15.

39. 40.

Mealy and Moore Models. State Reduction and Assignment. Design ProcedureSynthesis using D Flip-Flops, JK Flip-Flops, and T FlipFlops. HDL for Sequential Circuits (Optional) HDL for Sequential Circuits (Optional) Introduction: Registers with Parallel Load. Shift Registers; 4-Bit Shift Register; Serial Transfer and Serial Addition. 4-Bit Universal Shift Registers. Ripple Counters; Binary and BCD Ripple Counters. Synchronous Counters: Binary and BCD Counters. Other Counters; Counter with unused States. Other Counters: Counters with unused states, Ring Counters and Johnson Counters. HDL for Sequential Circuits (Optional) HDL for Sequential Circuits (Optional) Revision -

5-4 5-6

41.

5-7

16.

42. 43. 44.

5-5 5-5 6-1 6-2

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45.

46. 47. 18. 48. 49. 50.

6-2 6-3 6-4 6-5 6-5

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51. 52. 53.

6-6 6-6

20.

Final Exam

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