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  • Detailed Lesson Plan: Cmos Technology

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    6maaliga
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    This document outlines the detailed lesson plan for a VLSI Design course taught over 3 years and 6 semesters. It covers 5 units of topics: 1. CMOS technology including transistor characteristics, layout design rules, and process enhancements. 2. Circuit characterization and simulation including delay estimation, power dissipation, device modeling, and interconnect simulation. 3. Combinational and sequential circuit design including logic families, flip-flops, latches, and static/dynamic circuits. 4. CMOS testing including test fixtures, logic verification, design for testability, and internal/external testing features. 5. Verilog modeling including identifiers, gate primitives, operators, procedural assignments,

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    vlsiece

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    This document outlines the detailed lesson plan for a VLSI Design course taught over 3 years and 6 semesters. It covers 5 units of topics: 1. CMOS technology including transistor characteristics, layout design rules, and process enhancements. 2. Circuit characterization and simulation including delay estimation, power dissipation, device modeling, and interconnect simulation. 3. Combinational and sequential circuit design including logic families, flip-flops, latches, and static/dynamic circuits. 4. CMOS testing including test fixtures, logic verification, design for testability, and internal/external testing features. 5. Verilog modeling including identifiers, gate primitives, operators, procedural assignments,

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    Attribution Non-Commercial (BY-NC)
    Скачайте в формате DOC, PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    21 просмотров3 страницы

    Detailed Lesson Plan: Cmos Technology

    Загружено:

    6maaliga
    This document outlines the detailed lesson plan for a VLSI Design course taught over 3 years and 6 semesters. It covers 5 units of topics: 1. CMOS technology including transistor characteristics, layout design rules, and process enhancements. 2. Circuit characterization and simulation including delay estimation, power dissipation, device modeling, and interconnect simulation. 3. Combinational and sequential circuit design including logic families, flip-flops, latches, and static/dynamic circuits. 4. CMOS testing including test fixtures, logic verification, design for testability, and internal/external testing features. 5. Verilog modeling including identifiers, gate primitives, operators, procedural assignments,

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате DOC, PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    из 3

    FORMAT PCF/TH/06 MADHA ENGINEERING COLLEGE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DETAILED LESSON PLAN Batch : 2009

    2013 Year / Semester : IIIYr. /VI Sem. B Subject Code Topics to be covered UNIT- I CMOS TECHNOLOGY 1. 2. 3. 4. 5. 6. 7 8 9 10 12.12.11 12.12.11 13.12.11 13.12.11 14.12.11 16.12.11 19.12.11 20.12.11 21.12.11 23.12.11 1 5 2 4 5 6 1,5 2,4 5 6 Introduction about VLSI DESIGN
    A brief History-MOS transistor Technology related CAD issues, Manufacturing issues Ideal I-V characteristics Non ideal IV effects, DC transfer characteristics CMOS technologies Layout design Rules C-V characteristics CMOS process enhancements. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 2005

    Subject :VLSI DESIGN Class No. Date Period

    : EC2354 Books to be Referred

    And
    D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 2003

    UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION 11 12 13. 14 15. 16 17 18. 26.12.11 27.12.11 28.12.11 30.01.12 02.01.12 03.01.12 04.01.12 06.01.12 1,5 2,4 5 6 1,5 2,4 5 6
    Class test,Delay estimation, Power dissipation, Interconnect, Design margin, Reliability Scaling- SPICE tutorial, Class test, Device models, Device characterization, Interconnect simulation Transistor sizing Circuit characterization

    . Weste and Harris: CMOS


    VLSI DESIGN (Third edition) Pearson Education, 2005

    19. 09.01.12 1,5 Class test, comparison of circuit families 20. 10.01.12 2,4 Logical effort and Transistor sizing, Circuit characterization 21. 11.01.12 5 Design margin 22. 13.01.12 6 UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN Class test ,Circuit families Low power logic 23. 16.01.12 1,5 design 24. 17.01.12 2,4 Sequencing static circuits 25. 18.01.12 5 circuit design of flipflop 26. 20.01.12 6 circuit design of latches 27. 23.01.12 1,5 Class test,Sequencing static circuits, 28. 24.01.12 2,4 Sequencing static circuits, 29. 25.01.12 5 circuit design of latches 30. 28.01.12 6 Static sequencing element methodology 31 30.01.12 2,4 sequencing dynamic circuits 32. 30.01.12 2,4 synchronizers 33. 31.01.12 1,5 Class test ,Circuit design of and flip flops

    Weste and Harris: CMOS VLSI DESIGN (Third

    34. 36 37 38 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

    01.02.12 3.02.12 6.02.12 6.02.12 07.02.12 07.02.12 08.02.12 10.02.12 10.02.12 10.02.12 13.02.12 14.02.12 15.02.12 17.02.12 20.02.12 21.02.12 22.02.12 24.02.12 27.02.12 28.02.12 29.02.12 2.03.12 5.03.12 6.03.12 7.03.12 09.03.12 12.03.12 13.03.12 14.03.12 16.03.12 19.03.12 20.03.12 21.03.12 23.03.12 26.03.12 27.03.12 28.03.12

    5 6 1,5 5 2,4 4 5 6 1,5 6 1,5 2,4 5 6 1,5 2,4 5 6 1,5 2,4 1 6 1,5 2,4 5 6 1,3 2,4 5 6 1,5 2,4 5 6 1,5 2,4 5

    Low power logic design Low power logic design UNIT IV CMOS TESTING Class Test Text fixtures and test programs Logic verification Silicon debug principles Design for testability Manufacturing test Class test,Manufacturing test Boundary scan Class test ,Boundary scan Testers Testers test programs Class test Internal test Internal test ,external test features UNIT V Basic concepts- identifiers- gate primitives gate delays, operators, timing controls procedural assignments conditional statements Class test Basic concepts- identifiers- gate primitives, gate delays, operators, timing controls procedural assignments conditional statements Data flow and RTL structural gate level, switch level modeling Test benches equality detector, comparator, priority encoder Structural gate level description of decoder Review of all the unit University model question paper discussion half adder, full adder, Ripple carry adder, D latch and D concepts- identifiers- gate primitives, Basic flip flop. gate delays, operators, timing controls Revision Revision Revision

    J.Bhasker: Verilog HDL primer, BS publication,2001

    Signature of Staff

    Signature of HOD

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