The 2010 International Power Electronics Conference

Dead-time effect and its compensation in common-mode voltage elimination of PWM inverter with auxiliary inverter
N. Aizawa*, M. Kikuchi*, H. Kubota*, I. Miki*, K. Matsuse*
* Graduate School of Science and Technology, Meiji University, 1-1-1 Higashimita, Tamaku, Kawaki, 214-8571, JAPAN Abstract--This paper discusses improvement of common-mode voltage elimination ability of a PWM inverter with an auxiliary inverter. The main inverter and the small capacity auxiliary inverter are connected at the neutral point of the LC filter. The auxiliary inverter compensates common-mode voltages of the main inverter. Additionally, because the auxiliary inverter does not output active power, the capacity of the inverter is small. Common-mode voltages results from rapid change of output voltage when the switching is done in inverter. The common-mode currents flow through parasitic capacitances. Theoretically, the auxiliary inverter is able to perfectly compensate the common-mode voltage generated by the main inverter. Actually, however, the common-mode voltage appeared by the dead-time effect. This paper presents the influence of the dead time to the common-mode voltage of the PWM inverter with the auxiliary inverter and its compensation. Index Terms Common-mode voltage elimination, Electromagnetic Interference (EMI), Pulse Width Modulation (PWM), Dead-time.

Fig. 1. The conventional PWM inverter drive with LC filter.

I. INTRODUCTION Nowadays, pulse-width modulation (PWM) inverters are widely used for many adjustable speed drive systems. Three leg PWM inverter generates common-mode voltages. The common-mode voltages results from rapid change of output voltage of the PWM inverter. The common-mode voltages produce electromagnetic interference (EMI). The common-mode currents flow through the parasitic capacitances in the motor. It causes the fault of the bearing of the motor. Therefore, the common-mode voltages should be removed. To remove the common-mode voltages, four-leg inverters and three-level inverters have been proposed [1] - [4]. This paper discusses improvement of common-mode voltage elimination ability of the PWM inverter with an auxiliary inverter. II. REDUCTION OF COMMON-MODE VOLTAGE OF PWM INVERTER WITH AUXILIARY INVERTER. This chapter describes the principle and the circuit of the proposed method to compensate the common-mode voltage. The PWM control is used to drive three-phase three-wire induction motors. The conventional inverter and

Fig.2. The proposed PWM inverter drive

point voltage of the LC filter is expressed by equation (1) for the conventional inverter.

the proposed inverter configurations are shown in Fig.1 and Fig.2, respectively. In Fig.2, INV1 is the main inverter, and INV2 is the auxiliary inverter. Capacity of the auxiliary inverter is one-tenth of the main inverter, because the auxiliary inverter only outputs reactive power. Two inverters are connected at the neutral point of the LC filter. The common-mode voltage Vcom and the neutral

Vcom = v n =

So, when the neutral voltage of the LC filter is adjusted to 0, the common-mode voltage is also adjusted to 0. To adjust the neutral point voltage of the LC filter to zero, the output voltage of the auxiliary inverter is adverse magnitude to sum of the all phase voltages of the main

1 (Vu + Vv + Vw ) 3

(1)

978-1-4244-5393-1/10/$26.00 2010 IEEE

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inverter.

Adding the voltage expressed by equation (2) to the neutral point of the LC filter, the common-mode voltage for the proposed circuit becomes equation (3). Vcom = Vu + Vv + Vw + Vu ' + Vv ' + Vw' = 0 (3) To realize equation (2), the auxiliary inverter is controlled by reversing the PWM pulses for the main inverter. III. DEAD-TIME EFFCT AND ITS COMPENSATION Fig. 3 shows a simulation circuit of the proposed inverter. It is supposed that the difference of the switching timing between the main inverter and the auxiliary inverter is caused by the dead-time effect. In this chapter, the dead-time effect is investigated by simulation and its compensation method is proposed. A leg in inverters consists of two switches and their antiparallel diodes. The two switches in each leg are switched in such a way that when one of them is in its off state, the other switch is on. Therefore, ideally the two switches are never off simultaneously. In practice, they are both off for a short time interval, known as dead time, to avoid short circuiting of the dc input.Fig.4 shows the waveforms of the gate signals and the output voltage of main inverter when the current polarity is positive. Fig.5 shows the waveforms of the gate signals and the output voltage of main inverter when the current polarity is negative. During the dead-time period, the inverter outputs lower level voltage when the inverter output current polarity is positive, and it outputs upper level when the current polarity is negative. Fig. 6 shows the waveforms of the output voltage and the output current of the auxiliary inverter. Fig.7 shows the waveforms of the gate signals and the output voltage of the auxiliary inverter. The output current of the auxiliary inverter is positive at the turning down timing of the auxiliary inverter output voltage, and it is negative at the turning up timing of the auxiliary inverter output voltage

Vu ' + Vv ' + Vw' = (Vu + Vv + Vw )

(2)

Fig.4. The gate signals and the output voltage when the current polarity is positive.

Fig.5. The gate signals and the output voltage when the current polarity is negative.

as shown in Fig. 6. The auxiliary inverter outputs lower level voltage when the turning up timing of the auxiliary inverter output voltage, and it outputs upper level voltage when the turning down timing of the auxiliary inverter output voltage as shown in Fig. 7. Fig.8 and Fig.9 show the waveforms of the u phase output voltages of the main inverter and the auxiliary inverter. The difference of the switching timing depends on the current polarity of the main inverter as shown in Fig.8 and Fig.9. The turning down timing of the auxiliary inverter output voltage is earlier than that of the main inverter when the current polarity is positive as shown in Fig.8. On the other hand, the turning up timing of the auxiliary inverter output voltage is earlier when the current polarity is negative as shown in Fig.9. To compensate the dead-time effect, gate signals of the auxiliary inverter is adjusted depending on the current polarity of the main inverter output.

Fig.3. A simulation circuit of the proposed inverter

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Fig. 6. The output voltage and the output current of the auxiliary inverter. Fig.9.The output voltages when the current polarity is negative.

Fig. 10 and Fig. 11 show the waveforms of the compensated gate signals of the auxiliary inverter when the current polarity is positive and negative, respectively. The turning down timing of auxiliary inverter gate signals is delayed when the current polarity is positive as shown in Fig. 10. And the turning up timing of the auxiliary inverter gate signals is delayed when the current polarity is negative as shown in Fig. 11.

Fig. 7. The gate signals and the output voltage of the auxiliary inverter.

Fig.10. The gate signals when the current polarity is positive. Fig.8. The output voltages when the current polarity is positive.

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Fig.13. The output voltages when the current polarity is negative. Fig.11. The gate signals when the current polarity is negative.

Fig.12 and Fig.13 show the waveforms of the output voltages of the inverters when the dead-time effect is compensated. The switching timing of both inverters agrees with each other. Fig.14 shows the waveforms of the common-mode voltage and the output voltages of each phase of the inverter without the dead-time compensation. Fig.15 shows the waveforms of those with the compensation. In Fig.14, the common-mode voltage appears during dead-time periods. In Fig.15, The common-mode voltage is eliminated by the compensation.

Fig.14. Without compensation

Fig.12. The output voltages when the current polarity is positive.

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50 s

Fig.16. The current polarity is positive without the compensation.

Fig.15. With compensation

IV. EXPERIMENTAL RESULT For the experiments, the three-phase power supply of 200V is used, and it is converted into direct current with the rectifier circuit. The modulation index of PWM inverters is set at 0.8, and the carrier frequency of the inverter is 15kHz. Parameters of the LC filter and the induction motor are shown in Table 1.
Table1 Parameter of the LC filter and the induction motor Parameters of LC Filter Inductance of LC Filter L 1.54[mH] Capacitance of LC Filter C 10[ F] Ratings of Induction Motor Rated Power 3.7[kW] Rated Voltage 200[V] Rated Current 15[A] Pole Number 4 Rated Speed 1420[min 1 ]

50 s

Fig.17. The current polarity is negative without the compensation.

The difference of the switching timing between the main inverter and the auxiliary inverter is caused by the dead-time and the gate signal delay. The gate signal of the auxiliary inverter is adjusted considering these influences. Fig.16 and Fig.17 show the waveforms of the common-mode voltage, u phase output voltages of the both inverters and the output current without the compensation.

50 s

Fig.18. The current polarity is positive with the compensation.

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50 s

Fig.19. The current polarity is negative with the compensation.

measured with respect to the negative bus potential of the dc link voltage. The common-mode voltage is almost eliminated by the compensation. V. CONCLUSION

Fig.18 and Fig.19 show the waveforms of the common-mode voltage, u phase output voltages of the both inverters and the output current with the compensation. The common-mode voltages include a dc voltage as high as 141v (= Edc ), because they are

Improvement of the common-mode voltage elimination ability of the inverter with an auxiliary inverter is discussed. Theoretically, the auxiliary inverter is able to perfectly compensate the common-mode voltage generated by the main inverter. Actually, however, the common-mode voltage appeared by the dead-time effect. This paper presents the influence of the dead-time to the common-mode voltage of the PWM inverter with the auxiliary inverter and its compensation.
[1] A. L. Julian, G. Oriti, and T. A. Lipo, Elimination of Common-Mode Voltage in Three-Phase Sinusoidal Power Convers, IEEE Trans. Power Electron., vol.14 no.5,pp.982 989,Sept.1999. [2] Hee-Jung Kim, Hyeoun-Dong Lee and Seung-Ki Sul, A new PWM strategy for common-mode voltage reduction in neutral-point-clamped inverter-fed AC motor drives, IEEE Trans. IA, vol.37, no.6, pp.1840 - 1845, Nov.-Dec.2001 [3] Yonggao Zhang, Yanli Gao, Ming Yao and Qiang Dong, Research on common mode noise evaluation method, IEEE Cnf. Cybernetics and Intelligent Systems, pp. 1270 1274, 21-24 Sept. 2008. [4] Masafumi Kikuchi, Naoyuki Aizawa, Hisao Kubota, Ichiro Miki, Kouki Matsuse, Investigation of Common-Mode Voltages of PWM Inverter with a Small Capacity Auxiliary Inverter International Conference on Electrical Machines and Systems, 2009.

REFERENCES

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