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JG-004-DTF

Design for Test (DFT) Flow Guidelines

Prepared by: Laxman Arram Reviewed by: Srinivasa Kakumanu Approved by: NG Raju

Version No: 1.0 Copy No:

Issue Date: 20-01-2009 Issued to:

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Document Amendments Ver. No 1.0 Date 20/01/2009 Sec No Amendments made Initial Version Prepared by Reviewe d by Laxman Srinivas Approv ed by NG Raju

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Table of Contents
1 2. 3. 4. 5. 6 Introduction............................................................. Error! Bookmark not defined. DFT Flow Charts 6 EDA Tools . 9 Test Requirements and goals . 10 Test Features and Limitations 10 DFT Planning & Implementation 11 6.1 Test Modes .. 11 6.2 JTAG/BSCAN. 11 6.2.1 JTAG Interface ...................................................................................... 11 6.2.2 JTAG Instructions .................................................................................. 11 6.2.3 JTAG ID Code....................................................................................... 11 6.2.4 Non-BSCAN pins .................................................................................. 11 6.2.5 Test Compliance pin values ................................................................... 12 6.2.6 Bond pins .............................................................................................. 12 6.2.7 Pad Order .............................................................................................. 12 6.2.8 Description of used BSCAN Cells ......................................................... 12 6.2.9 BSDL .................................................................................................... 12 6.2.10 Disabling Mechanism for JTAG/BSCAN ............................................... 12 6.2.11 Use of JTAG for Scan/Test Mode signal generation ............................... 12 6.2.12 Use of JTAG for MBIST Interface ......................................................... 13 6.3 MBIST .......................................................................................................... 13 6.3.1 Introduction ........................................................................................... 13 6.3.2 Algorithm selection................................................................................ 13 6.3.3 Memory Grouping ................................................................................. 13 6.3.4 Slow-Speed/At-speed MBIST ................................................................ 13 6.3.5 MBIST Interface .................................................................................... 14 6.3.6 MBIST SDC .......................................................................................... 14 6.4 MACROTEST............................................................................................... 14 6.4.1 Introduction ........................................................................................... 14 6.4.2 Scan & Clocking Information for Macrotest........................................... 14 6.4.3 Algorithm .............................................................................................. 14 6.5 SCAN ............................................................................................................ 14 6.5.1 Design Information ................................................................................ 14 6.5.2 Scan Mode design changes .................................................................... 15 6.5.3 Scan Configuration ................................................................................ 15 6.5.4 Scan DRC and fixes ............................................................................... 15 6.5.5 Scan Chain Information ......................................................................... 15 6.5.6 Scan SDC .............................................................................................. 16 6.6 ATPG ............................................................................................................ 16 6.6.1 Stuck-at Fault Test ................................................................................. 16 6.6.2 Transition Delay Fault (TDF) Test ......................................................... 16 6.6.3 Path Delay Fault (PDF) Test .................................................................. 17

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7. 8.

6.6.4 Bridge Fault Test ................................................................................... 17 6.6.5 IDDQ Test ............................................................................................. 17 6.6.6 Burn-In Test...177 DFT Verification18 DFT Pattern Handoff19

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1. Introduction
As always, the primary objective of DFT is to provide the capability to generate and apply a high quality test set in an efficient and cost effective manner. Understand design description from the test perspective 1. Components to be tested such as IOs, RAM/ROM, PLL/DLL, IPs, Analog blocks and the core logic. Mention the Full Chip block diagram highlighting test requirements. 2. List of Hard and soft IPs 3. Functional clock domains and maximum frequency of operation 4. Existing test structures 5. Physical partitioning information 6. Clocking and Flop count information for each physical block Understand test features recommended for the targeted process technology 1. stuck-at fault test 2. transition fault test 3. path delay test 4. bridging fault test

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1 DFT Flow Charts


Understand the Design and DFT requirements Prepare DFT Architecture Definition

Obtain the libraries for DFT

MBIST RTL Insertion

NO Formal Verification YES MBIST Verificaation

Boundary Scan RTL Insertion

NO

Formal Verification YES Boundary Scan Verification

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Internal Scan Insertion

EDT IP Creation and Integration

Formal Verification

NO

YES ATPG Setup for EDT and BYPASS modes and Design Hand-off for Physical Design

ATPG

Reached Targeted Coverage

NO

YES ATPG Simulations (Zero Delay)

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ATPG with Post-Layout Netlist

DFT Timing Simulations

DFT Pattern Hand-Off

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3 EDA TOOLS
We use industry standard sign off tools from Mentor, Synopsys and Cadence

Scan Insertion (DFT Advisor, DFT Compiler, RC Compiler,

LogicVision) )

Scan Compression (Test Kompress, DFTC-Max)

MBIST Insertion (MBIST Architect, LogicVision)

Boundary Scan Insertion (BSD Architect, BSD Compiler, LogicVision)

ATPG Pattern Generation ( FastScan, TestKompress, TetraMax, LogicVision)

DFT Simulations ( NC-Verilog, ModelSim, VCS)

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4 Test Requirements and Goals


Identify the test requirements 1. Testing of IOs 2. Testing of RAM/ROMs MBIST Diagnostic MBIST Repair At-speed MBIST MacroTest Testing of PLL/DLLs Testing of Hard IPs and its internal test features Testing of Analog Blocks Testing of Core Logic Scan Compression Partition Scan At-speed Scan/ATPG Path Delay Testing Bridging Fault Test IDDQ Test Set the test goals 1. Compliance to IEEE1149.1 Std 2. Scan Compression Ratio 3. 99% Stuck-at test coverage 4. 80% Transition test coverage 3. 4. 5. 6.

5 Tester Features/Limitations
Understand the following which helps in defining the DFT architecture for Scan. - Tester Memory configuration (memory per scan chain) - Maximum number of scan chains and IOs supported - Maximum frequency that ATE can support

6 DFT Planning & Implementation


Test Modes
This section describes the top level signals and their decoding table/logic for internal test mode signal generation.

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6.2 JTAG/BSCAN
This section describes the JTAG interface and its application in the full chip. It also describes how the already existing TAP controllers are configured. 6.2.1 JTAG Interface Describes 5 top levels pins and corresponding pads used. Mention whether required PU/PD pads are used for each pin Describe the JTAG pin sharing with the existing JTAG Controller and mention the values of the BSCAN Compliance pins. Describe the JTAG interface to the embedded TAP Controllers using diagrams JTAG Instructions Instructions and their opcodes Instruction executed when unused-opcode is selected? Is it Byapss? What is the default JTAG instruction up-on JTAG reset? JTAG ID Code This section describes the JTAG ID code value as mentioned by the client. Non-BSCAN pins Mentions the Non-BSCAN pins - Power and Ground pins - Test Compliance pins - Analog pins - Bonded pins.? Test Compliance pin values Mention the Test Compliance pins and their values which are generally used to generate JTAG/BSCAN mode control signals.

Bond pins

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Mention the list of BOND pins for each package to decide on BSCAN Chain. If the BOND pins are less, same BSCAN chains can be used with separate pattern generation in the BSDL flow. If BOND pins are more, we may need to go with separate BSCAN chain for each package with MUX logic. Pad Order Mentioned the pad pin order which has to be followed for BSCAN chain insertion Description of used BSCAN Cells This section describes the BSCAN cells used in the design with diagrams. This helps immensely while simulation debug. BSDL Mentioned the BSDL desicription. - Full package - Other packages Disabling Mechanism for JTAG/BSCAN Mention various mechanisms to disable the JTAG during functional mode of operation. It will give clear information if mentioned with diagrams and signal waveform sequence. Use of JTAG for Scan/Test Mode signal generation This section describes the JTAG sequence and operation for scan/test mode signal generation and state of JTAG FSM during that mode. Mention with signal waveform sequence. Use of JTAG for MBIST Interface This section describes the following mechanisms Description of the JTAG interface to MBIST with diagrams Enabling MBIST controllers through JTAG Memory Fail status capture and Shift-out MBIST Diagnostic support

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MBIST
6.3.1 Introduction
This section describes memory types and their clocking in the design to decide the MBIST algorithm, memory grouping, register pipe-lining, etc., Information has to be mentioned here why/why not memory diagnostic/repair is required. Information regarding Shadow-Logic testing can be mentioned here. Explain the pin description of each memory type with diagram which would be helpful in MBIST insertion (though the documentation is available in the memory datasheets)

6.3.2 Algorithm selection


This section mentions the algorithms selected and targeted memory faults for each algorithm. Need to mention the test time and algorithm selection criteria. It would give clear information if the algorithms are mentioned as sequence of steps here.

6.3.3 Memory Grouping


This section mentions the memory grouping criteria, list of MBIST Controllers, corresponding memory instances in a tabular format. Mention each MBIST Controller execution (serial/parallel/interleaved).

6.3.4

Slow-Speed/At-speed MBIST

This section mentions the test logic support for slow/at-speed MBIST such as clock muxing, register-pipelining, etc., with diagrams.

6.3.5 MBIST Interface


This section defines the MBIST interface to enable MBIST operation and to capture MBIST status.

6.3.6 MBIST SDC


Mention the MBIST port IO delays and case analysis constraints during MBIST mode.

6.4 MACROTEST
6.4.1 Introduction

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This section describes requirement of Macrotest for the listed macros.

6.4.2 Scan & Clocking Information for Macrotest


This section describes the Scan IOs and the Read/Write clock configuration for slow-speed/atspeed Macrotest. Mention the Read/Write operation (at-speed/slow-speed) of memory MacroTest with diagrams.

6.4.3 Algorithm
This section describes the source of pattern file which is going to be translated by fastscan to create Macrotest patterns. Mention the steps of the algorithm.

6.5 SCAN
6.5.1 Design Information
This section contain the following information for each physical block and full chip - Functional clocks (clock diagrams with clock generation logic) and their clock crossing information to help in addressing clock skew issues - Reset generation diagrams - Flip-flop count for each functional clock. Helpful in scan chain balancing and estimating the scan IO requirements. - Scan Information of the embedded Hard IP and their connectivity; scan chain length in the Hard IP generally decides the internal scan chain length for Scan Compression and hence the Compression Ratio. - Measures to avoid clock skew issues during Scan mode

6.5.2 Scan Mode design changes


This section defines the design modification to make the design scan testable. - Scan clock domains - Describe the OCC (On-Chip Clock Control) logic for at-speed capture pulse generation with diagram. This logic also supports the Stuck-at test mode scan/capture Clock - Describe the additional chains that may need to be added for functional clock divider/PLL programming and enabling the selected OCC block. - At-speed clocking and programming information of On-Chip PLL/generated functional clocks

6.5.3 Scan Configuration


This section describes the following

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Scan Methodology Scan Control Signals such as Scan Enable, Scan Clocks, Test Resets, Scan Mode Scan IO/Channels Lock-Up Latch and Terminal Lock-up Latch usage Test point insertion Scan Chain lengths and compression ratio Non-Scan modules/instances and mention how they will be tested. Mention EDT/Scan Compression interface to the internal chains with diagram and describe the pins

6.5.4 Scan DRC and fixes


This section describes the allowed Test DRC violations and expected fixes in ATPG

6.5.5 Scan Chain Information


This section gives a table giving the following information for each chain - chain number - scan in and scan out - scan clock - functional clocks - chain length

6.5.6 Scan SDC


This section mentions the scan mode SDC for each physical blocks and full chip. Case analysis has to be mentioned for each of the various scan test modes such as - EDT/Bypass stuck-at shift - EDT/Bypass stuck-at capture - EDT/Bypass TDF shift - EDT/Bypass TDF capture

6.6 ATPG
This section describes the ATPG flow for each of the targeted fault model.

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6.6.1 Stuck-at Fault Test


This section describes the following - List of allowed black-box modules - ATPG pin constraints - Scan Clocks and Test Resets - Test Setup sequence - Reported DRC violations and their solutions - List of masked flops - Test Coverage and pattern count statistics - Explain stuck-at fault test mechanisms with diagram

6.6.2 Transition Delay Fault (TDF) Test


Following information need to be mentioned in addition to what mentioned for stuck-at - Mention the at-speed capture method (Launch-off-Shift/Lunch-off-Capture) - List the free running PLL Reference clocks and their frequencies - Path timing exceptions - Synchronous functional clock domains and their clock waveform relation. - List of capture clocks - Explain transition delay test mechanism with diagram

6.6.3 Path Delay Fault (PDF) Test


Explain the need of PDF though TDF is implemented. 5-10% of timing critical paths are generally tested in PDF. The difference between transition and path-delay is, it can check user-defined paths operate correctly at-speed.

6.6.4 Bridge Fault Test


This section describes the following. - Generation of ATPG patterns that target particular net pairs within a design using the bridging fault model - Run LVS with Net pair identification macros and create SVDB database using Mentors Calibre - Identify the net pairs to be targeted for bridging fault pattern generation by querying the SVDB database using Calibre - Set the fault type as bridging fault in ATPG tool which will use the 4-way dominant Fault model for fault analysis

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Load the Net pairs as the targeted fault sites Add all the faults and create the patterns which targets bridging faults. This method is more accurate in targeting the net pairs that are likely to bridge because of their physical characteristics

6.6.5 IDDQ Test


This section describes the following: - This is a pseudo stuck-at test which relies on measuring the supply current (Idd) in the quiescent state (when the circuit is not switching and inputs are held at static values). The current consumed in the state is commonly called Iddq. It can catch faults that are not found by conventional stuck-at fault test vectors - For IDDQ testing, the following sequence is followed: o Shut down all analog cell ( all analog cell are disconnected ) o Shut down Pull-up / Pull-down o Stop the clock o Make a measurement of the supply current IDDQ test vectors require only controllability, and not observability. This is because the observability is through the shared power supply connection

6.6.6 Burn-In Test


This section describes the following: - Burn-in is an electrical stress test that employs voltage and temperature to accelerate the electrical failure of a device. Burn-in essentially simulates the operating life of a device, since the electrical excitation applied during burn-in may mirror the worst-case bias that the device will be subjected to in the course of its useable life. Burn-in may be used as a reliability monitor or as a production screen to weed out the potential infant mortalities from the lot - Burn-in is usually done at 125degree Celcius with electrical excitation applied to the samples. The Burn-in oven had certain constraints, they are y Maximum number of toggling inputs in burn-in patterns is a function of the tester. All other inputs must be held constant y No differential pins that cannot be driven rail-to-rail may be used for driving or receiving y Maximum number of clocks is a function of the tester y Frequency of operation is 5Mhz y Number of Monitor pins should be one. This pin should actively toggle during execution. BIST outputs must be XOR-ed with all scan chain outputs to meet this constraint y BIDIs must remain in the same mode(input or output) through out The Burn-in pattern generation follows the following sequence: y Identify a subset of pins (inputs and bidis) that can toggle, this must include scan input pins and clocks. Ensure the chosen pins are connected to IO cells that have a valid switching data under BURNIN condition

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y y

y y

For the input pins that are not permitted to toggle, constrain it to 0 or 1 For the bidi pins that are not permitted to toggle, constrain it to Z to avoid generating patterns with contention. For the bidis chosen to be in the group of toggling pins, ensure bidis are always in input mode. Define scan chains, groups, clocks etc to enable DRC and enter ATPG mode. Clocks should not exceed the number Compute the number of patterns that will fit vector memory based on that set the limit on the ATPG patterns o Generate the patterns and order the patterns so that the most coverage comes first. This will help in reaching the coverage requirement with memory limitation in place. Save the patterns in tester format

7 DFT Verification
This section documents the verification status of each of the test features implemented TEST NAME NO-DELAY (or) ZERO-DELAY Pass/Fail WORSTCASE(MAXDELAYS) Pass/Fail BEST-CASE(MINDELAYS) Pass/Fail

ATPG: Stuckat(Compression Bypassed) ATPG: Stuck-at (Compression Enable) ATPG: Transition(Compression Bypassed) ATPG: Transition(Compression Enabled) ATPG: Pathdelay(Compression Bypassed) ATPG:Pathdelay(Compression Enabled) ATPG: Iddq (Compression Bypassed) ATPG: Burn-in (Compression Bypassed) MBIST: Production

Pass/Fail Pass/Fail

Pass/Fail Pass/Fail

Pass/Fail Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

Pass/Fail

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mode MBIST:Diagnostic mode Boundary SCAN

Pass/Fail Pass/Fail

Pass/Fail Pass/Fail

Pass/Fail Pass/Fail

8 DFT Pattern Hand-off


This section documents the pattern format delivered to the client for each of the tests implemented and verified