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Operation of a DSTATCOM in Voltage Control Mode

Mahesh K. Mishra, Student Member, IEEE, Arindam Ghosh, Senior Member, IEEE, and Avinash Joshi
AbstractThe paper presents the operating principles of a distribution static compensator (DSTATCOM) that is used to maintain the voltage of a distribution bus. A three-phase, four-wire distribution system is assumed in this study. A three-phase bridge inverter circuit that is supplied by two neutral-clamped dc storage capacitors realizes the DSTATCOM. Three filter capacitors, one for each phase, are connected in parallel with the DSTATCOM to eliminate high-frequency switching components. The voltage across the filter capacitor is controlled by a dead-beat controller to maintain the ac bus voltage. The magnitude of the bus voltage is chosen as nominal value, i.e., 1.0 p.u., while its phase angle is obtained through a feedback loop that maintains the voltage across the dc storage capacitors. Through detailed simulation and experimental results, it has been shown that the DSTATCOM can maintain the voltage against any unbalance and distortion in either the load or supply side. Index TermsDeadbeat control and neutral clamped inverter, distribution static compensator (DSTATCOM), voltage regulation.

(a)

(b) Fig. 1. (a) Simple radial system and (b) its Thevenin equivalent at bus 3.

I. INTRODUCTION N THE last two decades, various schemes of load compensation have been proposed [1][3]. These schemes can cancel the effect of unbalance and distortion in currents and can also correct the power factor at the load bus. All of these schemes assume the source voltages to be balanced and sinusoidal. In practice, however, the upstream source voltages may be unbalanced and distorted. In such cases, sensitive loads must be protected by a compensator that can regulate the bus voltage to provide balanced sinusoidal voltage of prespecified magnitude. This paper proposes a method to operate a distribution static compensator (DSTATCOM) as a voltage regulator to maintain the voltage of a specified bus. The magnitude of the bus voltage is prespecified while its phase angle is generated from the dc capacitor control loop. A deadbeat controller [4][8] for inverter is used for voltage tracking using the DSTATCOM. The algorithm has been discussed in detail. The proposed structure is verified through detailed simulation and experimental results. II. DSTATCOM IN VOLTAGE CONTROL MODE In a distribution system, there may be several different compensating devices. However, in a radial distribution system, the voltage of a particular bus can be distorted or unbalanced if the loads in any part of the system are nonlinear or unbalanced. The customers connected to that bus would be supplied by a set of unbalanced and distorted voltages, even when their loads are not contributing to the bus voltage pollution. Therefore, a

Manuscript received September 26, 2001. The authors are with the Department of Electrical Engineering, Indian Institute of Technology, Kanpur 208016, India. Digital Object Identifier 10.1109/TPWRD.2002.807746

DSTATCOM can be used at this bus to reduce harmonics and balance the bus voltages. Consider the three-phase, four-wire radial system shown in Fig. 1(a). Let us assume that we would like to correct the voltage of bus 3. The single-phase Thevenin equivalent of the system is constitute the Thevenin shown in Fig. 1(b). Here, , , and equivalent looking toward the left into the network, while the equivalent load is the impedance looking toward the right into the network, at bus 3. Since the DSTATCOM is connected at this bus, it is called the point of common coupling (PCC). We now have to use the DSTATCOM in the voltage control mode at bus 3. However, since the Thevenin equivalents can change any time depending on the load, it is desirable that these parameters are not used in the voltage controller design. Below, we present a voltage control technique that only requires the timing inforfor synchronization. mation from the source The single-phase equivalent circuit of the DSTATCOM that is connected to the PCC is shown in Fig. 2(a). The DSTATCOM is realized by a two-level neutral-clamped voltage source converter (VSC) [9], as shown in Fig. 2(b). A filter capacitor is used in parallel with the VSC circuit to provide a path for the high-frequency components. Note that the PCC is referred to as the terminal in this paper and its voltage is denoted by . In Fig. 2(a), is the switching variable that can take on values 1 corresponding to the states of one inverter phase, as shown and are assumed in Fig. 2(b). The capacitor voltages in the equivalent circuit. To derive a control to be equal to law, we assume for the time being that is equal to a continous signal . Then, the state space equation for the system shown in Fig. 2(a) is given as (1)

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Let be the reference (nominal) voltage to be maintained at the terminal bus. We now choose the cost function (5) and minimize it as

(6) From (4) and (6), the control input

(a)

is given by

(7) This control action is termed as a deadbeat action. The derivais discussed next. tion of from III. SWITCHING CONTROL As mentioned earlier, the switching variable is constrained to be 1. One leg of the neutral clamped inverter chosen to realize DSTATCOM is shown in Fig. 2(b). Here, there are two and . The voltage across dc storage capacitors, namely, . In Fig. 2(b), is the status each capacitor is maintained at of the top switch, bottom switch being complementary. This , the top switch is closed (open), while means for the bottom switch is open (closed) connecting the output of the . Therefore, through switching the inverter leg to . This is represented as inverter supplies a voltage in Fig. 2(a). The variable controls the status of the inverter switches through gate drive circuits. The switching variable is obtained from the continuous by a hysteresis action around zero, i.e. signal if else if The state vector and the output vector are given as then then

(b) Fig. 2. DSTATCOM. (a) Equivalent circuit. (b) Corresponding inverter circuit.

where

and

(8)

where is a prespecified hysteresis band. The value of the parameter determines the switching frequency. IV. REFERENCE VOLTAGE GENERATION (2) When two dc storage capacitors are supplying the DSTATCOM, the average of real power entering the PCC (terminal) from source must equal the sum of average load power and the losses in the DSTATCOM. Otherwise, the capacitors will continuously either charge or discharge. The magnitude of the terminal voltage can be arbitrarily chosen is decided by the up to a certain limit. The lower limit of with respect maximum permissible value of its angle to the source voltage, while its upper limit set by the voltage rating of the inverter and the dc capacitors. The phase angle must be adjusted in a closed loop for power balance. In this paper the nominal value of the terminal voltage is chosen to be 1.0 p.u. and the phase angle is controlled by a two-loop feedback control shown in Fig. 3. , the Assuming that the voltage across each capacitor is . The deviation of this total voltage across the dc link is

Writing the continuous state (1) into discrete form

where is the th sampling instant. The state transition matrix and the input matrix , given by and where is the sampling period. For the system of (1), let us define the elements of these matrices as and We can then write from (2) (4) (3)

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TABLE I SYSTEM PARAMETERS

Fig. 3.

Block diagram of closed loop voltage control.

total voltage from its reference value is a good indication of losses in the inverter. Therefore, we add the two capacitor voltages and compare the total with the reference value. It is to be noted that the dc capacitor voltage usually contains the switching frequency components. Therefore, comparing its instantaneous value with that of the reference will result in a large error in control. Instead, the average value of the dc capacitors can be regulated around the reference value. Alternatively, the value of the total voltage across the capacitors at the end of a cycle can be regulated around a reference value. This is done . The output through a proportional controller with a gain of , which is the amount of power that of this controller is must be drawn from the compensator in order to maintain the dc capacitor voltage. Thus

when bus to be controlled is remotely located. The reference voltages for the PCC bus are given as (12) is the desired magnitude of the terminal voltage and where is the fundamental frequency of the system. V. SIMULATION RESULTS In this section, detailed simulation results will be presented. It is demonstrated that the DSTATCOM in the voltage regulator mode is able to maintain the terminal bus voltage at the nominal value irrespective of the load changes and the upstream voltage fluctuations. For this, we assume a simplified distribution system in which a three-phase load is supplied by a source through a radial feeder. The objective is to supply a balanced voltage to the load. The simulation parameters are given in Table I. The three-phase load consists of , , ; 1) 2) three-phase diode bridges rectifier drawing a current of 5 A. For the source voltage of 360 V peak, the uncompensated terminal voltages are shown in Fig. 4(a). It can be seen that the terminal voltages contain the spikes due to diode rectifier load and feeder inductance. In Fig. 4(b), the compensated terminal voltages are shown. These are sinusoidal and balanced with a peak of 360 V. A. Performance in Case of Voltage Swell and Sag Voltage swell and sag are special (transient) cases of over voltage and under voltage, respectively. The short duration (a few cycles) transient over voltage is called a swell while an undervoltage is called a sag. The voltage swell and sag in source voltage is shown in Fig. 5(a). The different segments of the source voltage are as follows. For the first ten cycles, the source voltage has the nominal value of 360 V (peak). This is followed by a balanced 20% swell in the source voltage for eight cycles. After attaining the nominal value for the next ten cycles, the source voltage undergoes an eight-cycle, 20% balanced sag. Following this, the source voltage again attains the nominal

(9) where is the summation of voltage across the two capacitors (see Fig. 3). Since the loop maintains the capacitor voltage, we call it the outer voltage loop. The power angle (which is the phase angle between the terminal and the source voltages in their respective phases) is computed in such a way that it ensures that the shunt link draws that is equal to . To achieve an amount of power this, a PI controller is used, the output of which is power angle . This is given as

(10) and are the PI controller gains. These gains must where be carefully chosen, as high gain may cause unnecessary oscillations and may even cause instability. is computed as The instantaneous power in shunt link follows: (11) corresponds to It is to be noted that a positive value of a direction of power flow from the compensator into the bus, which reduces the dc capacitor voltage. In the steady state, the is negative due to the inverter losses. The average value of obtained from (11) is averaged over instantaneous value of and is used to ima cycle. This average value is denoted by plement the inner power loop to compute , as shown in Fig. 3. The angle is defined with the source voltage as reference. Thus, we require the zero crossing of the phase voltage of the source. This information can be obtained through telemetry

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(a)

(b) Fig. 4. Terminal voltages. (a) Before compensation. (b) After compensation.

is seen that terminal is regulated to nominal value, i.e., 360 V (peak), against the transient changes in the source voltage. The three-phase terminal voltage on a magnified scale is shown in Fig. 5(c). This figure indicates that the terminal voltages are balanced and sinusoidal. Fig. 5(d) shows the power angle. The total dc capacitor voltage is shown in Fig. 5(e). It can be seen from Fig. 5(d) that initially, when the compensator is switched on with the nominal value of source voltage, the power angle settles at 0.092 rad (5.3 ). During the voltage rises as the increased power swell, the dc capacitor voltage coming from the source starts charging the capacitors. To offset this, the power angle decreases. Exactly the opposite phenomenon can be seen during the voltage sag. During this period, the capacitors momentarily supply real power to the load and as a consequence, the load angle rises to draw more power from the source. It is to be noted that the duration of either swell or sag is rather small. Therefore, the controller does not have sufficient time to settle. However, when the source supplies the nominal voltage, the load angle settles to the steady state value of 0.092 rad. The increase in the shunt power during the voltage swell and the decrease during the voltage sag can be seen from Fig. 5(f), and its refwhich depicts the instantaneous shunt power . erence value B. Performance in Case of Unbalanced and Distorted Source Voltage The DSTATCOM in voltage control mode must be able to clean up any supply side disturbances. To investigate this, a source voltage is chosen that is both unbalanced and distorted, while the load remains the same as given before. To verify this, the source voltages are assumed to be unbalanced and contaminated by third harmonics. The voltages are given by: 1) phase a: 360 V (peak) and 15% third harmonic; 2) phase b: 432 V (peak) and 16% third harmonic; 3) phase c: 288 V (peak) and 8% third harmonic. The source voltages are shown in Fig. 6(a), while the terminal voltages are shown in Fig. 6(b). The compensator is connected at the end of the first cycle (0.02 s). It can be seen from Fig. 6(b) that the terminal voltages become balanced sinusoidal as soon as the compensator is connected. The power angle settles around 0.1 rad, i.e., 5.7 . The harmonic spectrums of phase a the source voltage and the terminal voltage are shown in Fig. 7(a) and (b), respectively. The total harmonic distortion (THD) in phase a of the source voltage is 15%, while in phase a of the compensated terminal voltage it is 0.95%. The THD in terminal voltage of the other two phases is also around 1%. C. Performance Under Change in Feeder Impedance It was mentioned previously that the source side impedance is, at best, the Thevenin impedance looking toward the source from the bus controlled by the DSTATCOM. Therefore, the DSTATCOM should be able to regulate the bus voltage even when the feeder impedance is changed. To test this, the feeder impedance is halved at the end of ten cycles (0.2 s) when the DSTATCOM is operating in the steady state. The system response is shown in Fig. 8, in which the bus voltage, total voltage

Fig. 5. (a) Swell and sag in source voltage. (b) Terminal voltage. (c) Terminal voltage on magnified scale. (d) Variation of  (e). (e) Total dc capacitor voltage. (f) Reference shunt power and instantaneous shunt actual power.

value. When the DSTATCOM is operated in the voltage control mode, the terminal voltage of phase a is shown in Fig. 5(b). It

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(a)

Fig. 8. System response to change in feeder impedance.

(b) Fig. 6. (a) Unbalanced source voltages with harmonics and (b) terminal voltages before and after regulation.

Fig. 9. System response to change in load.

(a)

siently, the power drawn from the source is larger than the power required by the load. As a result, the sum of the capacitor voltages increases. Then, the control loop (see Fig. 3) takes over and adjusts the power angle to bring back the sum of the capacitor voltages to the desired reference value in about ten cycles. D. Performance Under Load Change To investigate the effect of abrupt changes in load on the performance of DSTATCOM, the load pattern is divided into three regions. The phase a of the load current is shown in Fig. 9 where the regions are demarcated. For region 1, the load is normal and the power angle settles to around 0.09 rad (5.1 ). The is maintained at the reference total dc capacitor voltage value of 1200 V. In region 2, the unbalanced R-L load is removed from all three phases and only the diode rectifier load is present. Since this is smaller than the normal load current, reduces to a smaller value. Since the power requirement at the load is suddenly reduced, the sum of the capacitor voltages rises transiently but is then gradually brought back toward the steady state value of 1200 V by the control action. The load is in-

(b) Fig. 7. Harmonic spectrum in (a) source voltage and (b) compensated terminal voltage.

across the dc capacitors, and the load angle are shown. It can be seen that the ripples in the bus voltage die out within two cycles. Due to the sudden reduction in the feeder impedance, tran-

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TABLE II EXPERIMENTAL PARAMETERS

Fig. 11.

Variations in (a)  and (b) P

for unbalanced load.

Fig. 10.

Source and uncompensated terminal voltage in phase a.

creased in region 3. The effect of this load increase on the load angle and the capacitor voltage is just the reverse of region 2. However, power angle gradually settles around 0.16 rad, while settles around 1200 V. It is to be noted that the sum of the capacitor voltages in region 2 tries to recover to the reference value, but the load is changed before it can reach the steady state. Throughout the change in load, the terminal voltage is regulated and its waveform is similar to those shown in Fig. 8. It is also mentioned that for the parameters considered in simulation, the switching frequency of the inverter is approximately 3 kHz. VI. EXPERIMENTAL RESULTS The experimental system parameters are given in Table II. The load and the feeder impedance are the same as those given in the simulation studies. Three-phase terminal voltages [ in Fig. 2(a)] are measured using three Hall-effect voltage transducers across the filter capacitors. In addition, six Hall-effect current transducers are employed for the measurement of filter and shunt link currents . These capacitor currents quantities are given to an IBM compatible PC (P-II, 350 MHz) through a data acquisition card (NuDAQ 9118DG). A. When Load is Both Unbalanced and Nonlinear and uncompensated The phase a of the source voltage are shown in Fig. 10. It can be seen that terminal voltage the terminal voltage is distorted due to the rectifier load and the feeder impedance. To start the compensator, the load angle is initially set to zero and the dc capacitors are supplied by independent dc , the DSTATCOM is sources. Then, at an instant (see Fig. 3) is set to zero. connected to the ac bus and Since the inner control loop is active during this time, rises to a small value to supply the load power. Then, at a later instant , the outer control loop is activated and, at the same time, the independent sources are turned off. The steady state then settles to 0.17 rad (10 ). The entire transient is shown in

Fig. 12.

Source and compensated terminal voltage in phase a.

Fig. 13. Load current and terminal bus voltage during load change.

Fig. 11, which also shows the variation of average shunt power . The phase a of the compensated voltage in steady state is shown in Fig. 12 along with the phase a source voltage. The steady state can also be seen in this figure. B. Transient Performance The phase a of the load is changed suddenly by switching off the passive load and retaining only rectifier load. After approximately one and one-half cycle, the load is switched back to normal. The load current and terminal voltage in phase a are shown in Fig. 13. It is seen from the voltage waveform that the terminal voltage is not affected by change in the load. Thus, the voltage regulator is able to regulate the voltage at the bus under load transient. This experiment verifies the findings of Section V-D. C. Unbalanced Source Voltages For this test, the source voltage in phases a and c are set to 32 V (peak), while the source voltage in phase b is set to 40 V (peak). These are shown in Fig. 14. Once the compensator is connected, the terminal voltages become balanced with the desired magnitude of V (peak) in each phase. In the steady state,

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Fig. 14.

Unbalanced sources voltages.

[2] A. Ghosh and A. Joshi, A new approach to load balancing and power factor correction in power distribution system, IEEE Trans. Power Delivery, vol. 15, pp. 417422, Jan. 2000. [3] F. Z. Peng and J. S. Lai, Generalized instantaneous reactive power theory for three-phase power systems, IEEE Trans. Instum. Meas., vol. 45, pp. 293297, Feb. 1996. [4] A. Ghosh and G. Ledwich, Structures and control of a dynamic voltage regulator (DVR), in Proc. IEEE-PES Winter Meeting, Columbus, OH, 2001. [5] V. KuCera, A dead beat servo problem, Int. J. Control, vol. 32, no. 1, pp. 107113, 1980. [6] S. Wang and B. Chen, Simultaneous deadbeat tracking controller synthesis, Int. J. Control, vol. 44, no. 6, pp. 15791586, 1986. [7] L. Jetto, Ripple-free tracking problem, Int. J. Control, vol. 50, no. 1, pp. 349359, 1989. , Deadbeat controllers with ripple-free requirement for SISO dis[8] crete systems, Proc. Inst. Elect. Eng., pt. D, vol. 137, pp. 323328, Sept. 1990. [9] M. K. Mishra, A. Ghosh, and A. Joshi, A new STATCOM topology to compensate loads containing AC and DC components, in IEEE-PES Winter Meeting 2000, Singapore, 2000.

Fig. 15.

Compensated balanced terminal voltages. Mahesh K. Mishra (S00) received the B.Tech. degree from College of Technology, Pantnagar, India, and the M.E. degree from University of Roorkee, India. Currently, he is a research scholar at the Indian Institute of Technology, Kanpur. His interests are in the areas of power electronics and controls.

settles at 0.14 rad. The compensated terminal voltages are shown in Fig. 15. These are similar to those shown in Fig. 6. VII. CONCLUSIONS In this paper, a deadbeat control algorithm is applied to operate a DSTATCOM to regulate the voltage of the terminal bus at a nominal value. A closed loop control scheme, consisting of an outer dc capacitor voltage loop and an inner load angle control loop, is proposed. The control scheme maintains the power balance at the PCC to regulate the dc capacitor voltages. It has been shown that the DSTATCOM is able to regulate the PCC voltage against disturbances either in the load or in the source side. REFERENCES
[1] H. Akagi, Y. Kanazawa, and A. Nabae, Instantaneous reactive power compensators comprising switching devices without energy storage components, IEEE Trans. Ind. Applicat., vol. IA-20, pp. 625630, May/June 1984.

Arindam Ghosh (S80M83SM93) received the Ph.D. degree in electrical engineering from the University of Calgary, Calgary, AB, Canada. Currently, he is a Professor of electrical engineering at the Indian Institute of Technology, Kanpur. He has held visiting positions at Nanyang Technological University, Singapore, the University of Queensland, and Queensland University of Technology, Australia. His areas of interest are power systems, and power electronics and controls.

Avinash Joshi received the Ph.D. degree in electrical engineering from the University of Toronto, Toronto, ON, Canada. Currently, he is a Professor of electrical engineering at the Indian Institute of Technology, Kanpur. He has also been with the G.E.C. of India, Ltd. His interests involve power electronics circuits, digital electronics, and microprocessor systems.