ABSTRACT ON

A FPGA IMPLEMENTATION OF IEEE-754-2008 DECIMAL64 FLOATING-POINT ALU

Submitted to the FACULTY OF ENGINEERING of JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY, KAKINADA in partial fulfillment of the requirements for the award of the Degree of MASTER OF TECHNOLOGY In EMBEDDED SYSTEMS (E.S)
by

G.PREETHISUDHA (10481D5505)
Under the Guidance of

Sri B.K.N.Srinivasa Rao

Associate professor

Department of Electronics and Communication Engineering GUDLAVALLERU ENGINEERING COLLEGE SESHADRI RAO KNOWLEDGE VILLAGE GUDLAVALLERU-521356 ANDHRA PRADESH OCTOBER 2011

ABSTRACT
.

There is a significant demand for decimal arithmetic, especially in commercial and financial applications. To support decimal floating point arithmetic, several software packages have been developed. However performance of Software packages may not be sufficiently fast, especially for DFP intense applications. Hence hardware implementation for DFP is done to improve the performance of commercial and financial applications. Hardware manufacturers such as IBM are prompting to add decimal floating-point arithmetic support to their microprocessors. This project presents the design and FPGA implementation of a decimal floating point ALU. The design performs addition, subtraction multiplication and division on 64-bit operands that use IEEE 754-2008 decimal encoding of DFP numbers and is based on fully pipelined circuit. The design proposed is made up of independent stages stages: IEEE-754 coder/decoder, adder, subtractor, multiplier, divider and rounding. The DFP ALU is based on previously designed decimal64 floating point adder/subtractor proposed by carlos and martin. The decimal multiplication is based on a previously designed BCD multiplier. Verilog is used to implement the design. Speed, Area and power consumption of the design is going to be analyzed and verified with previously designed architectures. This is the first hardware FPGA design that performs addition, subtraction, multiplication and division using IEEE 754-2008 decimal 64 encoding.

References

1. Carlos Minchola, Martin Vazquez and Gustavo Sutter,A FPGA IEEE-754-2008 Decimal64 floating point adder/subtractor.IEEE(2011) 2. IEEE standard for floating-point arithmetic(IEEE STD 754-2008),revision of IEEE std 754-1985.august (2008). 3. Mark A .Erle,Brian J.Hickmann,Michael J,Schulte,Decimal Floating point multiplication.IEEE(2009). 4. T.Lang and A.Nannarelli: A Radix-10 combinational multiplier.(oct 2006) 5. M.F.Cowlishaw: Decimal floating-point algorithm for computers, (june 2003). 6. E.M.Schwarz,J.SKapernick and M.F.Cowlishaw:decimal floating-point support on the IBM system z10 processor,(2009),IBM journal of research and development.

PLAN OF ACTION Literature Survey Design and Verilog implementation of (a) adder/subtractor (b) multiplier (c) divider (d) Top level module verification of results Documentation Total 6 weeks 6 weeks 6 weeks 6 weeks 5 weeks 5 weeks 40 weeks 6 weeks

Sri.B.K.N.Srinivasa Rao (Internal Guide) Prof M.Kamaraju (Head of the Department)

G.Preethisudha (10481D5505)