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Processing and Layout

David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu)

University of Toronto

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D.A. Johns, K. Martin, 1997

Silicon Wafer
Create 8 diameter cylinder (1m long) of single-crystaline silicon with light doping (usually p-) Ingot cut into wafers about 1mm thick Photolithography Portions of silicon wafer are masked out so processing can be applied to remaining areas First create glass mask with dark areas using e-beam (cost of mask set often >$50k) Thermally grow SiO2 on wafer, apply negative photoresist, align glass mask and expose to UV light Photoresist hardens (after baking) where exposed to light, remaining region removed (including SiO2) Negative since SiO2 removed where mask is light
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D.A. Johns, K. Martin, 1997

Photolithography
Ultraviolet light

Opaque region

Translucent region Glass mask

p substrate

Hardened photoresist, PR1

SiO2

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D.A. Johns, K. Martin, 1997

Diffusion
Gas containing phosphorus

2PH3 + 4O2

n well

SiO2

p substrate

Introduce dopants where well will be located Phosphorus gas used in furnace (1000 C)

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D.A. Johns, K. Martin, 1997

Ion Implantation
Vertical and horizontal deflection plates

Ion
Separating slit Focusing lens Focusing lens Acceleration plates beam Target

Ion source

More control as can set concentration and thickness Acceleration sets depth, current and time set dosage However, lattice damage and narrow doping profile requires annealing
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D.A. Johns, K. Martin, 1997

Annealing
Ion dopant
concentration Before annealing

After annealing

Depth into silicon wafer

Heat to 1000 C then cool slowly


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D.A. Johns, K. Martin, 1997

Field-implants
Si3N4 PR3 PR2 Boron ions PR2

n well Field-implants SiO2 p substrate

Ensures silicon under field-oxide will not invert (will remain p-) although conductors above

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D.A. Johns, K. Martin, 1997

Field-oxide
Si3N4 SiO2 Field-oxide

n well p+ field-implants

p substrate

Thick SiO2 where no transistors Wet process (H2O) fast but more defects Dry process (O2) slower but denser and higher quality (high temp so called thermal oxide)
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D.A. Johns, K. Martin, 1997

Thin gate-oxide and threshold-adjust


Thin gate SiO2 Field-oxide

n well p+ field-implants p substrate Gate thresholdvoltage-adjust implant

Thin oxide grown using dry process (0.01 m ) If n-well more heavily doped then single boron implant will adjust Vtn from -0.1V to 0.8V and Vtp from -1.6V to -0.8V
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D.A. Johns, K. Martin, 1997

Polysilicon Gates
PR4 SiO2 Polysilicon gate

n well p+ p substrate

Apply gate but only heat to 650 C polysilicon (rather than single crystal) 10 to 30 and thickness of 0.25 m

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D.A. Johns, K. Martin, 1997

P+ Junctions
PR5 PR4 Polysilicon Polysilicon PR5 PR4

p+ n well p
+

p+ p+ p substrate

p+ p+ p+

Substrate connection

Gates and drains formed for p-channel Use ion implantation Self-aligned as gate determines edges Substrate connection also shown

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D.A. Johns, K. Martin, 1997

N+ Junctions
PR6 Polysilicon gates PR6

n+

p+

p+

n+ p+

p+ p+

n+

n+ p+

n
p-channel junctions Well tie p substrate

Substrate tie

n-channel junctions

p+ regions protected and n+ implanted Requires annealing after since ion implantation used Would melt gate if it were metal

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Final Cross Section


Overglass Metal 2 Metal 1 Polysilicon gate CVD SiO2 Via

n+ n

p+

p+

n+ p+ Well tie

p+ p+ Substrate tie p substrate

n+

n+ p+ Field-oxide

p+ field-implant p-channel transistor

n-channel transistor

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D.A. Johns, K. Martin, 1997

Bipolar Cross Section


p+ poly Base Al Emitter n+ poly Base Collector n+ poly

n+ p+ n+

n p+

p substrate p+ p

n+

SiO2

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D.A. Johns, K. Martin, 1997

Transistor Layout

W L Active region
Field-oxide region Polysilicon mask

Active-region mask W 2

Contact mask

4 2

2 2 L

Effective gate region

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D.A. Johns, K. Martin, 1997

Mask misalignment
Gate poly Source junction Drain junction Noncatastrophic misalignment

Source-to-gate short circuit

Source-to-drain short circuit

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Series Transistor Layout


J1 J3 Q1 Q2 J2
2 2 J3 2

Less capacitance at node J3 since less area AND not beside field implants

J1

Q1 Q
1

10

Q2 Q
2

J2

2 2
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2
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CMOS Inverter
n+ well tie p+ junction n well

Q2 Vin

VDD

VDD Q2 p-channel transistor

Vout
Poly interconnect

Q1

Gnd

Active region Metal interconnect Vout

Vin

Q1

n-channel transistor Gnd

n+ junctions

p+ substrate tie

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Single Large Transistor (4 in parallel)


Node 1 Metal interconnect

Active region

J1 Q1

J2 Q2

J3 Q3

J4 Q4

J5

Gates Node 2 VG

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Schematic of Large Transistor


Node 1 J1 Q1 J2 J3 Q2 Q3 Q4 J4 J5

Node 2

VG

Node 1

Q 1 J2 VG J1

Q 2 J2 J3

Q3 J4 J3

Q 4 J4 J5 Node 2

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Actual sizes different from Masks


SiO2 protection SiO2 protection Polysilicon gate

Well Overetching Lateral diffusion under SiO2 mask

Polysilicon gate

Transistor channel

p+ field implants

Channel width narrowing

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Common Centroid Layout for Diff Pair


DM1 SM1,M2

GM2

M2

M2

M1

M1

M2

M2

M1

M1

GM1

DM2

M2
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D.A. Johns, K. Martin, 1997

M1

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Capacitor Errors due to Overetching


x1 x 1 2e y 1 2e e e
True capacitor size Ideal capacitor size

y1

Use unit sized capacitors as much as possible If not unit sized, keep the same perimeter-to-area ratio to minimize errors
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Capacitor Layout
10 m 10 m 10 m 19.6 m 6.72 m 4 units 2.314 units 10 m

Want to maintain ratio of 4 to 2.314 Rectangular capacitor of size 1.314 units used has same perimeter-to-area ratio as square also has same number of corners

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Capacitor Layout Equation


Assume K is non-unit sized and between 1 and 2 otherwise use another unit sized capacitor C2 A2 x2 y2 K ----- = ----- = --------2 C1 A1 x1 Can show that y2 = x1 ( K K 2 K ) (+/- simply changes orientation of rectangle and sqrt is positive since K>1) Also Kx 1 x 2 = -------y2
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(1)

(2)

(3)

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Example Capacitor Layout


Well contacts

C1

C2

Polysilicon bottom plate

Polysilicon top plates

C2

C1

Polysilicon edge matching

Well region

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Typical Resistor Layout


0.14

10

2.11

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More Accurate Resistor Layout

Dummy resistor

Dummy resistor

R1

R2

R1

R2

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Separate Analog and Digital Power Supplies


I/O pad
Analog power-supply net Digital power-supply net

Connect analog and digital supplies together as close to supply as possible


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D.A. Johns, K. Martin, 1997

Guard Ring to Sheild Analog


VDD

Analog region

p+ psubstrate

n+ n well

p+

Digital region

Depletion region acts as bypass capacitor

Depth of well causes higher impedance since doping usually higher near surface of p- substrate (perhaps 10 times higher resistance!)
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Sheilding Signals
Ground line used for shielding Analog interconnect Digital interconnect

n+ n well

n+

n+

p substrate

Shields keep noise from being capacitively coupled into or out of substrate

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Example Analog Floorplan


V DD
Opamp 1 Opamp 2 Opamp 3 Opamps

V SS
Gnd

Contact to substrate

n well under capacitor region

Capacitors

Region for n-channel switches Switches n well under p-channel switch region
V DD Gnd 1 1 2 2

n well shield and bypass capacitor

Clock lines

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Latch-Up
Vin VDD VDD

p+

n+

Q1

n+

p+ n well

Q2

p+ n+ Rn

Rp

p substrate

Occurs when large substrate or well currents Creates an SCR that might turn on and not off until harm done (or power turned off)

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Latch-Up
VDD = 5 V Rn Q2 0V Vinv Rp 5V Q1 Rp Q1 Q2 VDD = 0.9 V Rn

Capacitive coupling due to junction depletion caps of MOS drains Have many substrate contacts and guard rings
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D.A. Johns, K. Martin, 1997