Parsers are deterministic PDAs and cannot handle context-sensitive features of programming languages; e.g.

, Variables are declared before use Types match on both sides of assignments Parameter types and number match in declaration and use Semantic consistency that cannot be handled at the parsing stage is handled here Type checking of various programming language constructs is one of the most important task.Abstract AGs permit both inherited and synthesized attributes, whereas YACC-style grammars permit only synthesized attribute While generating machine code directly from source code is possible, it entails two problems With m languages and n target machines, we need to write m * n compilers The code optimizer which is one of the largest and very-difcult-to-write components of any compiler cannot be reused By converting source code to an intermediate code, a machine-independent code optimizer may be written Intermediate code must be easy to produce and easy to translate to machine code A sort of universal assembly language Should not contain any machine-specic parameters(registers, addresses, etc.) Usually produced during a traversal of the semantically validated syntax tre Quadruples, triples, indirect triples, abstract syntax trees are the classical forms used for machine-independent optimizations and machine code generatio Intermediate code generation process introduces many inefciencies Extra copies of variables, using variables instead of constants, repeated evaluation of expressions, etc.Code optimization removes such inefciencies andimproves code Improvement may be time, space, or power consumption It changes the structure of programs, sometimes of beyond recognition Inlines functions, unrolls loops, eliminates some programmer-dened variable Common sub-expression elimination Copy propagation Loop invariant code motion Partial redundancy eliminationInduction variable elimination and strength reductionCode opimization needs information about the programwhich expressions are being recomputed in a function?which denitions reach a point? All such information is gathered through data-ow analysi Converts intermediate code to machine code Each intermediate code instruction may result in many machine instructions or vice-cersaMust handle all aspects of machine architectureRegisters, pipelining, cache, multiple function units, etc.Generating efcient code is an NP-complete problemTree pattern matching-based strategies are among the bestNeeds tree intermediate codeStorage allocation decisions are made hereRegister allocation and assignment are the most importantproblemPeephole optimizationsAnalyze sequence of instructions in a small window(peephole) and using preset patterns, replace them with amore efcient sequenceRedundant instruction eliminatione.g., replace the sequence [LD A,R1][ST R1,A] by [LDA,R1]Eliminate jump to jump instructionsUse machine idioms (use INC instead of LD and ADD)Instruction scheduling (reordering) to eliminate pipelineinterlocks and to increase parallelismTrace scheduling to increase the

size of basic blocks andincrease parallelismSoftware pipelining to increase parallelism in loopThere are different kinds of memory in a computer system Some remember by the state an electrical circuit is in Others remember by the amount of electrical charge stored in a capacitor Yet others remember by magnetic or optical properties They can vary substantially in their speed and capacity e.g., DRAM Memorye.g., SRAMe.g., Hard disk drive/Mag Tape, VCD/DVD 2 kinds of registers in a CPU 1. Special purpose registers 2. General purpose registers Program Counter (PC): used to remember the location in memory of the instruction currently being executed n Instruction Register (IR): used to remember that instruction n Processor Status Register: used to remembers status information about current state of processor, e.g., whether an arithmetic overflow has occurre.CISC Complex Instruction Set Computer A single instruction performs a complex operation involving several actions 2. RISC Reduced Instruction Set Computer Each instruction performs only a simple operation.Arithmetic/logical instructions 2. Data transfer instructions 3. Control transfer instructions q jump, conditional branch, function call, return What must be done on a function call? q Pass parameters on stack q Transfer control to start of function q Remember return address n Where? q Save register values q Allocate space for local variables on stack What must be done on a function return? q Pass return value (through stack) q Restore register values q Clean up stack q Transfer control back to return address Implementing a Stack in Memory n Use one register as Stack Pointer, say R29 q It could point at either n The current top of stack value, or n The memory location for the next push onto the stack n Decide whether stack grows up or down in memory

q up: grows into higher memory addresses q down: grows into lower memory addresses 4 Implementing a Stack in Memory Stack Allocated Variables n Space allocated on function call, reclaimed on return n Addresses calculated and used by compiler, relative to the top of stack, or some other base register associated with the stack n Growth of stack area is thus managed by the program, as generated by the compiler Heap Allocated Variables n Managed by a memory allocation library n Functions like malloc, realloc ,free n Get `linked (joined) to your program if they are called n Executed just like other program functions n What about growth of the heap are Fetch instruction from Main Memory to CPU q Get instruction whose address is in PC from memory into IR q Increment PC 2. Decode the instruction q Understand instruction, addressing modes, etc q Calculate memory addresses and fetch operands 3. Execute the required operation q Do the required operation 4. Write the result of the instructiona? q Managed by the library function n Fetch instruction from memory to processor IR = Memory[PC]; Increment PC n Decode instruction and get its operands Decode; Operands from registers/memory to ALU n Execute the operation Trigger appropriate functional hardware If load/store, send access request to memory n Write back the result To destination register/memory Problem: There could be many programs running on a machine concurrently n Sharing the resources of the computer q Processor time q Main memory n They must be protected from each other q One program should not be able to access the variables of another q This is typically done through Address Translation. Each program is

compiled to use addresses in the range 0 .. MaxAddress (e.g., 0 .. 2 32 - 1) n These addresses are not real, but only Virtual Addresses n They have to be translated into actual main memory addresses n The translation can be done to ensure that one program can not access variables of another program n Many programs in execution can then safely share main memor. Shell: A command interpreter, through which you interact with the computer syste.Page: fixed size unit of memory (contiguous memory locations) for which a single piece of translation information is maintained.Page Fault n Situation where virtual address generated by processor is not available in main memory n Detected on attempt to translate address q Page Table entry is invalid n Must be `handled by operating system 1. Identify slot in main memory to be used 2. Get page contents from disk 3. Update page table entry n Data can then be provided to the processor.Identify slot in main memory to be used 2. Get page contents from disk 3. Update page table entry n It must keep track of the available, unused physical pages, maybe in a free list n What if the free list is empty? q i.e., all main memory physical pages are already mapped to virtual pages q The page fault handler must then identify a page to be replaced (evicted) from main memor.How does the page fault handler decide which main memory page to replace when there is a page fault? q How important is this decision? q In the worst case, the policy could always replace the page that is going to be accessed by the processor next n Each of these would require copying the virtual page from hard disk to main memory. Hard disk q Remembers things by the state of magnetic material q Disk is a mechanical device: motors rotating a firm plate coated with magnetic material q Aside: Computer noises

q Reading a page from hard disk could take -msecs (milli:10 -3 ) if not longer q i.e., 10 4 times slower than main memory For a program that displays good locality of reference what would be a good page replacement policy? now A page fault occurs on reference to page Px Which page should be replaced from memory to make space for page Px Candidates: P1 , P2 , P3 ,Pn, all the pages in main memory P5 P1 Pick from them the page that was referenced least recently.LRU page: at the bottom of the stack q Stack must be updated on every memory access.Unlike LRU, FIFO does not guarantee that the number of page faults will decrease if you increase the size of main memory. To translate a virtual memory address, the MMU has to read the relevant page table entry out of memory q Hardware must provide page table entries faster than that (most of the time.If the required page table entry is present in the TLB, then the MMU can do the translation fast n Otherwise: TLB miss n Must be handled, possibly like the OS handles a page fault.pageUnit of memory management q Translation: There is one translation table entry per page q Data movement: A page of data is copied together between main memory and dis.A tradeoff is involved here: the larger the page size n the smaller the page table, but n more potentially unused memory space within a page (internal fragmentation) n The unit of transfer to hard disks is typically 512B (disk sector) n A typical page size: 4KB.We can view a process as an OS created abstraction n Like virtual memory, it does not really (physically) exist

n It is just an OS interface for program execution n It is the unit of resource management by OS q There is a separate page table for each process q Unit of sharing of CPU time. Can 2 processes be running at the same time? n Answer: Not if there is only one PC, one IR, one set of general purpose registers q i.e., not if there is only one CPU of the kind that we have been talking about n So, if there are 100 processes on a computer system and process P1 is running, what state are the other 99 processes in.OS do when a process does something that will involve a long time? q e.g., Anything that involves a hard disk access (file read/write operation, page fault, ) n If it does nothing, the processor will be idle for billions of cycles q The processor could have executed billions of instructions instead during that time.OS should try to maximize processor utilization q utilization: fraction of time that the processor is busy n OS could change status of that process to `Waiting and make another process `Running n Question: Which other process? q Determined by the process scheduler.The part of the OS that manages the sharing of CPU time among processes n Possible considerations that the scheduler could use in making scheduling decisions q Minimize average program execution time q Fairness to all the programs in execution.Idea 1: Let the currently Running process continue to do so until it does something that involves a long time q Then switch to one of the Ready processes q But what if the currently Running process is executing an infinite loop while (1) ; /* a simple infinite loop */ q No other process would ever get to run if the OS uses Idea 1 q This is an example of a Non-preemptive policy q It does not seem to be very fair to other processes.When the OS changes which process is currently running on the CPU

n The switch takes some time, as it involves replacing the hardware state of the previously running process with that of the newly scheduled process q Saving HW state of previously running process q Restoring HW state of newly scheduled process n Amount of time would help in deciding what a reasonable CPU timeslice value would be.Process Lifetime: Time between fork() that created the process and exit() that causes its termination.Running Process Preempted? n OS preemption code must run on the CPU q How does OS get control of CPU from running process to run its preemption code? n Hardware timer interrupt q Hardware generated periodic event q When it occurs, hardware automatically transfers control to OS code (timer interrupt handler) q An interrupt is an example of a more general phenomenon called an exception. Exceptions n Certain exceptional events that occur during program execution, handled by the processor HW n There are two kinds of exceptions 1. Traps Synchronous, software generated n Page fault, Divide by zero, System call 2. Interrupts n Timer, keyboard, disk : : Asynchronous, hardware generate Hardware Saves processor state Transfers control to corresponding piece of OS code, called the exception handler 2. Software (exception handler) Takes care of the situation as appropriate Ends with return from exception instruction 3. Hardware (execution of RFE instruction) Restores the saved processor state Transfers control back to the saved PC valu.Processes can communicate using files q Example: Communication between parent process and child process q Parent process creates 2 files before forking child process q Child inherits file descriptors from parent, and they share the file pointers q Can use one for parent to write and child to read,

other for child to write and parent to read.OS supports something called a pipe q corresponds to 2 file descriptors (int fd[2]) q Read from fd[0] accesses data written to fd[1] in FIFO (First In First Out) order and vice versa. Processes could communicate through variables that are shared between them q Shared variables, shared memory; other variables are private to a process q Special OS support for program to specify objects that are to be in shared regions of address spac. Address translation is used to protect one process from anothe.how can 2 processes share a variable?. Processes could communicate by sending and receiving messages to each othe.Sometimes processes dont need to communicate explicit values to cooperate q They might just have to synchronize their activities q Example: Process 1 reads 2 matrices, Process 2 multiplies them, Process 3 writes the result matrix q Process 2 should not start work until Process 1 finishes reading, etc. q Called process synchronization q Synchronization primitives n Examples: mutex lock, semaphore, barrier Must synchronize processes so that they access shared variable one at a time in critical section; called Mutual Exclusion n Mutex Lock: a synchronization primitive q AcquireLock(L) n Done before critical section of code n Returns when safe for process to enter critical section q ReleaseLock(L) n Done after critical section n Allows another process to acquire loc.Thread q Thread of control in a process q `Light weight process n Weight related to q Time for creation q Time for context switch q Size of context n Recall: Process as a Data Structure.Thread context q Thread id q Stack q Stack pointer, PC, GPR values n So, thread context switching can be much faster

than process context switch n Many threads in the same process share parts of that process context q Virtual address space (other than stack) n So, threads in the same process share variables that are not stack allocated. Which is more important? q execution time of a single instruction q throughput of instruction execution i.e., number of instructions executed per unit time n Cycles Per Instruction (CPI) n Current ideas: CPI between 3 and 5 n Pipelining q Why keep Fetch hardware idle while instruction is being decode. A pipeline with p stages could give a speedup of p (compared to a non-pipelined processor that takes p cycles for each instruction) n i.e., A program would run p times faster on the pipelined processor (than on the nonpipelined processor) q if on every clock cycle, an instruction completes executio This hazard can be overcome by designing main memory so that it can handle 2 memory requests at the same time q Double ported memory n Or, since we are assuming that memory delays are hidden by cache memories q include a separate instruction cache (for use by the IF pipeline stage) and data cache (for use by the MEM stage) n Identify the possible structural hazards and design so as to eliminate them Instruction Scheduling q Reorder the instructions of the program so that dependent instructions are far enough apart q This could be done either n by the compiler, before the program runs: Static Instruction Scheduling n by the hardware, when the program is running: Dynamic Instruction Schedulin. n Reorder the instructions of the program to eliminate data hazards q or in general to reduce the execution time of the progra control hazarSince the branch is resolved only in the EX stage, there must be 2 stall cycles after every conditional branch instruction memory latency will be hidden so that it appears to operate at processor speed n Cache Memory: HW that makes this happen q Design principle: Locality of Reference

q Temporal locality: least recently used objects are least likely to be referenced in the near future q Spatial locality: neighbours of recently referenced locations are likely to be referenced in the near future15 Cache Memory Exploits Th. For a small program, everything would index into the same place in the hash table (collisions) Using the Most Significant address bits for hashing is not a good ide.A and its neighbours typically differ only in their least significant bits.A and its neighbours possibly differ only in these bits; but they should be treated as one unit, not hashing into different hash table entries Using the Least Significant address bits for hashing is not a good idea.Block: Serves the same purposes in cache memory as the Page does in virtual memory The Cache Directory contains one entry for each cache block, just like the Page Table contains one entry for each virtual page.Reduce translation table size 2. Exploit spatial locality of reference.A cache is organized in terms of blocks, memory locations that share the same address bits other than lsbs n Main memory is also organized in terms of blocks.Where can a memory block be placed in the cache? (Block Placement) q Direct mapped, Set Associative 2. How is a block identified in the cache? q Tag, valid bit, tag checking hardware 3. What is the replacement policy used? q LRU, FIFO, Random 4. What happens on writes to the cache? q Cache Hit: When is main memory updated? q Cache Miss: What happens on a write miss? Main memory block M is uniquely mapped to cache block M mod N n Consider a program which accesses two memory locations alternately q A, B, A, B, A, B, A, B n Where both A and B map to the same cache block q Example: N = 8, A is in memory block 6 and B is in memory block 14 n Every access will result in a cache miss.Under direct mapped placement q No choice is possible: unique placement n Under set associative placement q One of the blocks within the unique set must be selected for replacement q First-In-First-Out (FIFO)

q Least Recently Used (LRU) q Random Hardware must keep track of LRU information q Within the cache directory Recall that LRU replacement was not considered feasible for Virtual Memor.When is Main Memory Updated on Write Hit? n Write through: Writes are performed both in cache and in Main Memory + Cache and memory copies are kept consistent -- Multiple writes to the same location/block cause higher memory traffic -- Writes must wait for longer time (memory write) Solution: Use a Write Buffer to hold these write requests and allow processor to proceed immediately Write back: writes are performed only on cache q Modified blocks are written back to memory only on replacement from the cache o Need for dirty bit for each cache block + Writes will happen faster than with write through + Reduced traffic to memory -- Cache & main memory copies are not always the sam.What happens on a Write Miss? q Write-Allocate: allocate a block in the cache and load the block from memory to cache q Write-No-Allocate: write directly to main memory n Write allocate/no-allocate is orthogonal to write-through/write-back policy q Write-allocate with write-back q Write-no-allocate with write-through: ideal if mostly-reads-few-writes on data.Cold start miss: we assume that the cache is initially empty. Also called a Compulsory Miss Hit ratio of our loop is 75% -- there are 1536 hits out of 2048 memory accesses This is entirely due to spatial locality of reference. If the loop was preceded by a loop that accessed all array elements, the hit ratio of our loop would be 100%, 25% due to temporal locality and 75% due to spatial locality.Conflict miss: a miss due to

conflicts in cache block requirements from memory accesses of the same program Hit ratio for our program: 0% Source of the problem: the elements of arrays A and B accessed in order have the same cache index Hit ratio would be better if the base address of B is such that these cache indices differ.Row major order q Example: for a 2-dimensional array, the elements of the first row of the array are followed by those of the 2 nd row of the array, the 3 rd row, and so on q This is what is used in C n Column major order q A 2-dimensional array is stored column by column in memory q Used in FORTRAN.Physical addressed cache q Hit time higher (cache access after translation) n Virtual addressed cache q Data/instruction of different processes with same virtual address in cache at the same time n Flush cache on context switch, or n Include Process id as part of each cache directory entry q Synonyms n Virtual addresses that translate to same physical address n More than one copy of a block in cache Lifetime = Execution time of program 2. Lifetime = Time between explicit creation of data & explicit deletion of data 3. Lifetime = During execution of a function (i.e., time between function call and return) 4. Lifetime = Beyond the execution time of the program - even if the power fails while the program is running.Storage for data that continues to exist beyond the lifetime of program q Persistent data q This will be possible only through the use of nonvolatile, persistent secondary storage devices q like hard disk

2. A named sequence of data on a persistent storage device.How long does it take to read/write a disk sector? q Seek latency: Time for actuator/disk arms to move to the correct cylinder q Rotational latency: Time for correct sector to rotate to under the read/write head q Transfer time: Time for the data to be transferred from the disk to the main memory q Disk may currently be in a low power consumption mode (not spinning) 5-10 msecs 2-3 msecs for a 15,000 rpm disk at 30MB/sec 100s of msecs.Our view of disk: linear address space of fixed size sectors/blocks numbered from 0 up.Sequential access: bytes of file are read in order from start to finish q Reading a file from start to end q e.g., cat program.c n Random access: bytes of file are read in some (random) order q e.g., Query to a database file.Disk management: efficient use of disk space 2. Name management: how users select files for use 3. Protection: of files from users. Question: How does the OS keep track of which disk blocks are associated with a given file? n Consider a file that is 10 disk blocks in size n File Descriptor: OS structure that describes which blocks on disk represent a file n Issues: 1. Take common file access patterns into account 2. It must be possible for files to change in siz. File is stored in contiguous blocks on disk q File descriptor: first block address, file siz linked list Each file block contains the disk address of the next file block q File descriptor: first disk block addres File Index is an array containing addresses of 1 st ,2 nd , etc block of file q File descriptor: index Disk Block Caching The system maintains in main memory copies of

recently used disk blocks Called the disk block buffer cache They can be accessed from this buffer the next time they are required Could be managed using an LRU like policy Problem: If the system crashes, file data in the buffer cache will be lost The OS periodically flushes the contents of the cache to disk (say once every 30 secs.Disk Block Caching The system maintains in main memory copies of recently used disk blocks Called the disk block buffer cache They can be accessed from this buffer the next time they are required Could be managed using an LRU like policy Problem: If the system crashes, file data in the buffer cache will be lost The OS periodically flushes the contents of the cache to disk (say once every 30 secs.Disk Block Caching The system maintains in main memory copies of recently used disk blocks Called the disk block buffer cache They can be accessed from this buffer the next time they are required Could be managed using an LRU like policy Problem: If the system crashes, file data in the buffer cache will be lost The OS periodically flushes the contents of the cache to disk (say once every 30 secs.Disk Block Pre-fetching Prefetching: Reading something into a cache or buffer before it is actually required Idea: If a file is being read sequentially, a few blocks can be read ahead from the disk.Memory Mapped Files Idea: Map file into the virtual address space of the process that is accessing it. Memory Mapped Files n Traditional open, /lseek/read/write, close are inefficient due to system calls, data copying n Alternative: map file into process virtual address space n Access file contents using memory addresses (variables, pointers) n Could result in a page fault if that part of the file is not currently in memory n System call: mmap(addr,len,prot,flags,fd,off) n Some OSs: cat, cp use mmap for file acces. Asynchronous I/O Idea: In ordinary file I/O operations (e.g., read), the process has to wait (block) for the disk operations to complete before proceeding to use the file data

 But the I/O could be made non-blockin. Objective: allow programmer to write his/her program to perform I/O without blocking n eg: SunOS aioread, aiowrite library calls q aioread(fd, buff, numbytes, offset, whence, result) n Reads numbytes bytes of data from the file descriptor fd into the buffer buff, without blocking the process n The buffer should not be referenced until after the operation is completed; until then it is in use by the OS n Mechanisms are provided for the process to be notified of the actual completion of the I/O operatio. Question: Is a network of computers a parallel computer? q Yes, but the time involved in interaction (communication) might be high, as the system is designed assuming that the machines are more or less independent q Special parallel machines would be designed to make this interaction overhead les. Question: Why use parallel computers? 1. With two processors, twice as many instructions can be executed in a given amount of time n i.e., improved performance, reduced program execution time 2. The computer can continue to operate even if one of the processors fails n i.e., fault toleranc o one can see that is a free semigroup with as its identity. A CFL L is said to be inherently ambiguous if all the grammars generating it are ambiguous or in other words, there is no unambiguous grammar generating i.m It is undecidable to determine whether a given CFG /cfl is ambiguous or not. X is useful because it appears in at least one derivation from S to a word in L(G). Otherwise X is useles.In simplication of context-free grammars another important step is to make the given context-free grammar unit rule free i.e., to eliminate unit rules. This is essential for the application in compilers. As the compiler spends time on each rule used in parsing by generating semantic routines, having unnecessary unit rules will increase compiler time. Let L be accepted by a NFSA with moves. Then L can be accepted by a NFSA without -moves. If a language L is accepted by a nite

nondeterministic automaton, then L can be accepted by a right linear grammar and conversel.the equivalence of FAs (regular language) and type-3 or regular grammars, and the equivalence of PDAs and CFGS. We now show the equivalence of unrestricted grammars and TMs, and context-sensitive grammars and LBAs.LBA's accept exactly the CSLs except for the fact that an LBA can accept while a CSG cannot generate ,If L is a context-sensitive language, then L is accpeted by one LBA M.Every CSL is recursive. There is a recursive language that is not context-sensitive.There are algorithms to test emptiness of a CFL.Given a CFL L and a string x, the membership, problem is to determine whether xEl ?Decision algorithm for testing finiteness of a CFL :Equivalence of DFA & NFA proves that non determination does not add power in case of FA s. But it is not true in case of PDA s, i.e., it can be shown that nondeterministic PDA s are more powerful than DPDA s. In fact, DCFL s is a class of languages that lies properly between the class of regular languages and CFL . If L is a regular language, then there is some DPDA M such that l=l(m).First, prove the fact that DCFL s are closed under complement.

But, it is fact that CFL 's are not closed under complement. Hence, there must exist a CFL that is not s DCFL.We now show that class of languages accepted by DPDA s is properly included in the CFLS . First, note that, every DCFL is a CFL since every DPDA is a special case of a PDANPDA that the two methods of acceptance (by empty stack and final state) are equivalent. That is, a language L has an NPDA that accepts by final state if and only if some NPDA accepts it by empty stack. But this is not true for DPDAs. The language recognizing capability of DPDA s that accept by empty stack is much less than that of the other. This is proved in the following lemma. Lemma1 : If a language L is accepted by a DPDA by empty stack, then L has the prefix properly. Before giving the proof of the above lemma we first define the prefix properly of a language. Lemma1 : If a language L is accepted by a DPDA by empty stack, then Lhas the prefix properly.every language that has the prefix property and is accepted by a DPDA with final state is also accepted by some DPDA that accepts by empty stock.anguage accepted by a DPDA must have an unambiguous gramma.CFGs to model the syntax of arithmetic expressions, block structures in programming languages.Since PDAs and CFGs are found to be equivalent.nondeterministic nature of PDAs they are still not of immediate practical use in parsing. The parsing process may involve back tracking because of the nondeterministic steps and hence would lead to inefficiency. On the other hand, a parser rooted in the idea of a DPDA does not involve

backtrack----ing and hence expected to work efficiently. Even though the capability of DPDAs are limited in the sense that they accept DCFLs which is a proper subset of CFLs, it turns out that the syntax of most programming languages can be modeled by means of DCFLs. One of the main motivations for studying DCFLs lies in the fact that- they can describe the syntax of programming languages and they can be parsed efficiently using DPDAs. To produce a compiler for a given programming language the syntax is required to be described by some CFGin restricted form that generate only DCFLs. There are different kinds of such CFGs in restricted forms. The LL- and LR-grammars are two important classes in this category.FA have limited capability. (in the sense that the class of languages accepted or characterized by them is small). This is due to the "finite memory" (number of states) and "no external memory" involved with them. A PDA is simply an NFA augmented with an "external stack memory". The addition of a stack provides the PDA with a last-in, first-out memory management cpapability. This "Stack" or "pushdown store" can be used to record a potentially unbounded information. It is due to this memory management capability with the help of the stack that a PDA can overcome the memory limitations that prevents a FA to accept many interesting languages.a PDA can store an unbounded amount of information on the stack, its access to the information on the stack is limited. It can push an element onto the top of the stack and pop off an element from the top of the stack. To read down into the stack the top elements must be popped off and are lost. Due to this limited access to the information on the stack, a PDA still has some limitations and cannot accept some other interesting languages.pushdown automata and context-free grammars are equivalent in expressive power, that is, the language accepted by PDAs are exactly the context-free languages.CFG G there exists some PDA M that accepts exactly the same language generated by G. ii) Given any arbitrary PDA M there exists a CFG G that generates exactly the same language accpeted by M.- transitions do not increase the power of an NFA . That is, any - NFA ( NFA with E transition), we can always construct an equivalent NFA without -transitions.DFA is a special type of NFA and hence the class of languages accepted by DFA s is a subset of the class of languages accepted by NFA s. Surprisingly, these two classes are in fact equal. NFA s appeared to have more power than DFA s because of generality enjoyed in terms of -transition and multiple next states. But they are no more powerful than DFA s in terms of the languages they accept. Converting DFA to NFA Theorem: Every DFA has as equivalent NFA .equivalent DFA will have 2n states.f the number of states in the NFA is n , then there are 2n states in the DFA . That is, each state in the DFA is a subset of state of the NFA . But, it is important to note that most of these 2n states are inaccessible from the start state and hence can be removed from the DFA without

changing the accepted language. Thus, in fact, the number of states in the equivalent DFA would be much less than 2n To verify that a finite group is abelian, a table (matrix) - known as a Cayley table - can be constructed in a similar fashion to a multiplication table. If the group is G = {g1 = e, g2, ..., gn} under the operation , the (i, j)'th entry of this table contains the product gi gj. The group is abelian if and only if this table is symmetric about the main diagonal. This is true since if the group is abelian, then gi gj = gj gi. This implies that the (i, j)'th entry of the table equals the (j, i)'th entry, thus the table is symmetric about the main diago.intermediate language typically differs from that of a practical machine language in three fundamental ways: Each instruction represents exactly one fundamental operation; e.g. "shiftadd" addressing modes common in microprocessors are not present. Control flow information may not be included in the instruction set. The number of registers available may be large, even limitless. A popular format for intermediate languages is three address code.FIFO is cheap and intuitive, it performs poorly in practical application. Thus, it is rarely used in its unmodified form. The page replaced may be an initialization module that was used a long time ago and is no longer needed. On the other hand, it could contain a heavily used variable that was initialized early and is in constant use. nondeterministic Turing machines are equivalent with deterministic Turing machines BNF (Backus Normal Form or BackusNaur Form) is a notation technique for context-free grammars, often used to describe the syntax of languages wo objectives for any disk scheduling algorithm: 1. Maximize the throughput - the average number of requests satisfied per time unit. 2. Minimize the response time - the average time that a request must wait before it is satisfied. Some of the disk scheduling algorithms are explained below. FCFS (First Come, First Served) perform operations in order requested no reordering of work queue no starvation: every request is serviced poor performance SSTF (Shortest Seek Time First) after a request, go to the closest request in the work queue, regardless of direction reduces total seek time compared to FCFS Disadvantages starvation is possible; stay in one area of the disk if very busy switching directions slows things down SCAN

go from the outside to the inside servicing requests and then back from the outside to the inside servicing requests. repeats this over and over. reduces variance compared to SSTF. LOOK like SCAN but stops moving inwards (or outwards) when no more requests in that direction exist. C-SCAN (circular scan) moves inwards servicing requests until it reaches the innermost cylinder; then jumps to the outside cylinder of the disk without servicing any requests. repeats this over and over. variant: service requests from inside to outside, and then skip back to the innermost cylinder. C-LOOK moves inwards servicing requests until there are no more requests in that direction, then it jumps to the outermost outstanding requests. repeast this over and over. variant: service requests from inside to outside, then skip back to the innermost request ponse Time for FCFS, SSF, and CSCAN. SSF has signicantly worse maximum response time than FCFS, but CSCAN has roughly the same, or lower, maximum response time than FCFS. In some instances, CSCAN is able to have lower response time than FCFS because its average response time is lower. Implementing system calls requires a control transfer which involves some sort of architecture-specific feature. A typical way to implement this is to use a software interrupt or trap. Interrupts transfer control to the operating system kernel so software simply needs to set up some register with the system call number needed, and execute the software interrupt. System calls can be roughly grouped into five major categories: Process Control. load execute create process terminate process get/set process attributes wait for time, wait event, signal event allocate, free memory File management. create file, delete file open, close read, write, reposition

get/set file attributes Device Management. request device, release device read, write, reposition get/set device attributes logically attach or detach devices Information Maintenance. get/set time or date get/set system data get/set process, file, or device attributes Communication. create, delete communication connection send, receive messages transfer status information attach or detach remote devices.compiers.Preprocessing - handling include files, macros, and manifest constants Scanning - breaking the input file into tokens and managing the symbol table Parsing - verify that the input tokens form valid syntax Semantics - derive meaning from the structure of the input tokens Optimizations - find ways to accomplish the same task, quicker Code Generation - generate assembly language code for a specific computer Assembly - assemble the assembly language code to an object module ld - load one or more object modules with libraries to form an executable. Top Down Parsing The top down parsing method, also called a predictive parse or LL parse, requires that we reorganize the grammar so that the first symbol of each rule defining a given Non-Terminal will indicate which rule to choose for the NonTerminal. This transformation can be done to any grammar, but is sometimes awkward. There are also some cases that cannot be parsed correctly with Top Down Parsing methods. Bottom UP Parsing The bottom up parse, also called an LR parse is the most powerful parseing method. It also has the most complicated set of algorithms for building the parse tables. There are a set of algorithms for building LR parse tables. The same algorithm is used for all of the LR parse tables. LR(0) The first of the LR parse generation algorithms is called LR(0) and it generates tables that are somewhat large. The LR(0) parse algorithm do not parse grammars with certain types of ambiguities.

LR(1) The second algorithm, which handles all of the grammars correctly is LR(1). The LR(1) algorithm generates correct parse tables for grammars with all of the ambiguities that are found in most useful langauges. The biggest strike against LR(1) parse tables is the fact that the tables generated are much larger then the LR(0). SLR The third algoritm attempts to handle some of the amiguities that LR(0) fails at and keeps the size of the parse tables the same as those generated by LR(0). It is called Simple LR. LALR The last algorithm, Look Ahead LR, generates parse tables that are the same size of LR(0), but handles all of the ambiguities that are handled by LR(1). Stable sorting algorithms maintain the relative order of records with equal keys. If all keys are different then this distinction is not necessary. But if there are equal keys, then a sorting algorithm is stable if whenever there are two records (let's say R and S) with the same key, and R appears before S in the original list, then R will always appear before S in the sorted list. When equal elements are indistinguishable, such as with integers, or more generally, any data where the entire element is the key, stability is not an issue.r features, which are typically found in RISC architectures are: Uniform instruction format, using a single word with the opcode in the same bit positions in every instruction, demanding less decoding; Identical general purpose registers, allowing any register to be used in any context, simplifying compiler design (although normally there are separate floating point registers); Simple addressing modes, with complex addressing performed via sequences of arithmetic and/or load-store operations; Few data types in hardware, some CISCs have byte string instructions, or support complex numbers; this is so far unlikely to be found on a RISC.One good thing about the bisection method, that we dont have with Newtons method, is that we always know that the actual solution x is inside the current interval [a, b], since f(a) and f(b) have dierent signs. This allows us to be sure about what the maximum error can be. Precisely, the error is always less than half of the length of the current interval [a, b], i.e. {Absolute Error} = |x x | < (b a)/2, where x is the center point between the current a and b.

A multigraph is Eulerian if it has a closed trail containing all its edges. A multigraph is called even if all of its vertices have even degree. Theorem. Let G be a connected multigraph. Then G is Eulerian iff G is even. If every vertex of a multigraph G has degree at least 2, then G contains a cycle.A connected graph with exactly 2k vertices of odd degree decomposes into max(k; 1) trails If G is an n-vertex graph with at most n 2 edges then G is disconnected. If G is an n-vertex graph with at least n edges then G contains a cycle. Every loopless multigraph G has a bipartite subgraph with at least e(G)/2 edges. Every edge of a tree is a cut-edge. (ii) Adding one edge to a tree forms exactly one cycle. (iii) Every connected graph contains a spanning tree When page fault occurs following steps occur a. A trap is generated to the hardware b. The system stores the present state of registers and program counter c. It checks if the requested page is in valid space of process or not d. Looks for a free frame e. If no free frame is available, use some page replacement scheme and choose a victim frame f. The requested page is brought into system When modified bit is set to 0 and the page is to be replaced, we dont write back the contents of the page as 0 indicates that the page was not modified. Reference bit is used for page replacement policy A page fault occurs when the present bit is 0 Round Robin Scheduling There will be non-linear improvement due to reduced overhead of context switching. a) If the time quantum will be increased then the I/O utilization on a Round-Robin scheduler will decrease. The rationale behind this is that since I/O-bound processes have shorter CPU burst, thus by increasing the time -quantum, CPU bound processes which have larger burst will occupy the CPU for more time, thus it will decrease the I/O utilization. b) Yes, the CPU bond jobs will take longer to finish when the time-slice decreases. When the time-slice length decreases, programs with larger CPU burst will have to wait for quite sometime before its again scheduled. Thus the CPU bound jobs will suffer for greater waiting time in case of smaller time slice as compared to large-time slice, where the same jobs could have been finished in fewer quantum's and thus less wait. Increasing or Decreasing? Let f be continuous on an interval I and differentiable on the interior of I. If f(x)0 for all xI, then f is increasing on I. If f(x)0 for all xI, then f is decreasing on I.

Relative Maxima and Minima By the First Derivative Test, relative extrema occur where f(x) changes sign. Absolute Maxima and Minima If f has an extreme value on a closed interval, then the extreme value occurs either at a a critical point or at an endpoint. every regular language is context-free. The converse is not true: for example the language consisting of all strings having the same number of a's as b's is context-free but not regular. subset within the class of regular languages is the finite languages those containing only a finite number of words.A regular expression is not unique for a language. That is, a regular language, in general, corresponds to more than one regular expressions.Regular expressions are equal if and only if they correspond to the same language.The union of infinitely many regular languages is not necessarily regular.A finite language is regular. The halting problem is undecidable. a problem is NP-hard if every problem in class NP can be polynomial time reducible to it. A problem is NP-complete if it is in class NP and NP-hard. When a string is not accepted by a Turing machine, that is when a Turing machine does not halt on a string, one of the following three things happens: (1) The Turing machine goes into an infinite loop, (2) no transition is specified for the current configuration and (3) the head is at the left end and it is instructed to move left. In cases (2) and (3), the operation of the Turing machine is aborted. A Turing machine thus may accept a string and halt, reject a string and halt, or loop.It can be proven that any language accepted by an n-tape Turing machine can be accepted by a one tape Turing machine and that any function computed by an ntape Turing machine can be computed by a one tape Turing machine. Since the converses are obviously true, one can say that one tape Turing machines are as powerful as n-tape Turing machines. This is a kind of Turing machines that have one finite control and one tape which extends infinitely in both directions. It turns out that this type of Turing machines are only as powerful as one tape Turing machines whose tape has a left end. nondeterministic Turing machine is only as powerful as a deterministic Turing machine. Any language accepted by a nondeterministic Turing machine is also accepted by some deterministic Turing machine. deterministic Turing machine might take much more time than a nondeterministic Turing machine to accept a string. PDA and Context-Free Language There is a procedure to construct a PDA that accepts the language generated by a given context-free grammar and conversely. That means that a language is context-free if and only if there is a PDA that accepts it.Contect-free grammars are powerful grammars. They can describe much of programming languages and basic structures of natural languages. Thus they are widely used for compilers for high level programming languages and natural language processing systems.

The parsing for context-free languages and regular languages have been extensively studied .E-transitions are a convenience, but do not increase the power of FA' . From a given position in the tree, it takes O(1) time to walk to either the left or right child, to walk to the parent, or to rotate a node and its parent. (Rotation is a simple tree operation in which a node x takes the place of its parent y, with y becoming a child of x. The two subtrees of x and the other subtree of y are redistributed such that the structure of the binary search tree is preserved.)