Subject: VLSI DESIGN Staff In-Charge: Ms.Ramapriya 2 Marks UNIT-I MOS TECHNOLOGY 1. What is meant Photolithography? 2. What is photoresist?

3. Describe the process of ion implantation. 4. What is defect density? 5. What is annealing? 6. What are the two categories in the region of chip? 7. What are the different integration levels? 8. Define yield. 9. What is SSI and MSI? 10. What is LSI and GSI? 11. What is VLSI and ULSI? 12. What are the pattern layers needed for nFET masking sequence? 13. What are the pattern layers needed for pFET masking sequence? 14. Where we introduce length metric lambda? 15. Define design rule check(DRC). 16. What are the sequences we used to create the pattern? 17. Describe the term reticle. 18. What is the use of passivation mask? 19. State Moores law. 20. What are the classifications of design rules? 21. What is minimum feature and minimum spacing? 22. What is surround rule and exact size? 23. What are process specific rules? 24. Define design rules (DRs). 25. What is meant by Reactive Ion Etching? 26. Give the advantages of IC? 27. Give the variety of Integrated Circuits? 28. Give the basic process for IC fabrication. UNIT-II MOSFET TRANSISTOR 1. What are the materials we use to built the MOSFET? 2. Define surface charge, Qs. 3. What are the three different regions of operation using in square law model?

4. Define body bias voltage. 5. How to express the device transconductance and process transconductance. 6. Define mobility ratio. 7. How to measure the effective channel length? 8. Write the current equation for cut off, triode and saturation region. 9. Define MOSFET capacitors. 10. How to express the MOS capacitors in terms of gate capacitance? 11. Write the capacitance equation for three regions? 12. How we find the threshold voltage variation in transistor? 13. What is the possible modification to change the saturation current? 14. What is the total capacitance for n-type source /drain? 15. What are the different regions we can define in MOSFET depend upon voltages? 16. Define threshold voltage V(t). 17. What is body effect? 18. What are the parameters in threshold voltage? 19. What is Enhancement mode transistor and Depletion mode Device? 20. When the channel is said to be pinched off? 21. What are the advantages of CMOS process? 22. Why NMOS technology is preferred more than PMOS technology? 23. What are the different MOS layers? 24. Define Threshold voltage in CMOS? 25. What is Latch up? 26. What is Stick Diagram? 27. What are the uses of Stick diagram? UNIT-III CMOS LOGIC GATES DESIGN AND LAYOUT 1. Draw the circuit and layout diagram for series connected nFETs. 2. Draw the circuit and layout diagram for parallel connected nFETs. 3. What is Elmore time constant? 4. Draw the logic circuit diagram for NOR gate. 5. Draw the logic circuit diagram for NAND gate. 6. Define rise time and fall time. 7. Define time start and time pulse. 8. Write a short note about complex logic gates. 9. What is tri-state circuits? 10. Draw the circuit and symbol for transmission gate. 11. Draw the transmission gate based XOR circuit.

12. When there is a necessary to design transistors with large channel width? 13. What is the operation of transmission gate? 14. What are the different cell levels in cell hierarchy? 15. Define custom design. 16. What is cell library? 17. Define layer-to-layer crosstalk. 18. Define Full custom design. 19. What are the characteristics of cell library? 20. Design 2:1 MUX using transmission gate.

UNIT-IV STORAGE ELEMENTS AND DYNAMIC LOGIC CIRCUITS 1. What is the operation of SR latch? 2. Draw the NOR based SR and D latches. 3. How to design the simple register using transmission gate. 4. What is bistable circuit ? 5. What is meant by ring oscillator? 6. What is meant by positive edge triggered D-type flip flop? 7. How charge leakage exists in CMOS circuits? 8. Explain about master slave D- type flip flop when clock signal=0 and 1. 9. What is dynamic DFF? 10. What is retention time? 11. Write a short note about static RAM cell. 12. When the static RAM cell is in hold state. 13. What is meant by dynamic logic gate 14. What is precharge ? 15. What is evaluate? 16. Write a short note about domino logic. 17. What is meant by self resetting logic gate? 18. Write a short note about dynamic memories. 19. How to estimate the leakage current using I-V relationship. 20. Write the equation for hold time. UNIT-V VHDL Write the acronym for VHDL? What are the different types of modeling VHDL? What is packages and what is the use of these packages What is variable class ,give example for variable Name two subprograms and give the difference between these two.

1. 2. 3. 4. 5.

6. What is subprogram Overloading 7. write the VHDL coding for a sequential statement (d-flipflop ) 8. What are the different kinds of The test bench? 9. What is Moore FSM 10. Write the testbench for and gate 11. Give the different arithmetic operators? 12. Give the different bitwise operators. 13. Differentiate a signal and variable? 14. Explain case statement in VHDL with an Example. 15. Explain BLOCK statement in VHDL with an Example. 16. Explain Process statement in VHDL with an Example. 17. Explain Generate statement in VHDL with an Example. 18. What is Test Bench? 19. Give the behavioral model for JK flipflop. 20. Give the behavioral model for T flipflop. 21. Give the data flow model for half adder and half subtractor. 22. Give the dataflow model for full adder. 23. Give the dataflow model for full subtractor. 24. What is component instantiation? 25. Differentiate sequential from concurrent signal assignment statements. 16 Marks UNIT 1 MOS TECHNOLOGY 1. 2. 3. 4. 5. 6. Explain the chip design hierarchies Discuss the steps involved in CMOS fabrication process. Explain the layers of Integrated Circuits. Explain Photolithography and Pattern Transfer. Explain the CMOS design Rule set. List out the layout design rule. And draw the physical layout for one basic gate and two universal gates. 7. (a) What do you mean by layout of a component. (b) Draw neat layout diagrams for NMOS and PMOS transistor. UNIT 2 MOSFET TRANSISTOR 1. Derive the CMOS inverter DC characteristics and obtain the relationship for output voltage at different region in the transfer characteristics. 2. Discuss the origin of latch up problems in CMOS circuits with necessary diagrams. Explain the remedial measures.

3. 4. 5. 6.

Explain the operation of PMOS Enhancement transistor. Explain the operation of NMOS Enhancement transistor. Explain the concept of MOSFET as switches. Explain the square law model of MOSFET with its analytical description. UNIT 3 CMOS LOGIC GATES DESIGN AND LAYOUT

1. Explain with neat diagrams the Multiplexer and latches using transmission Gate. 2. Explain the tristate inverter and pass transistor logic briefly. 3. Design a layout diagram for two input n-MOS NAND and NOR gates. 4. Explain various cell hierarchies. 5. Explain the cell Libraries. UNIT 4 STORAGE ELEMENTS AND DYNAMIC LOGIC CIRCUITS 1. 2. 3. 4. 5. Explain SR latch and Bit level register. Explain DFF and Dynamic DFF. Write a note on Static RAM cell. Explain: i) Dynamic logic, ii) Domino logic, iii) SR logic. Write a short note on Dynamic Memories. UNIT 5 VHDL 1. Explain in detail any five operators used in VHDL. 2. Write the VHDL code for 4 bit ripple carry full adder. 2. Give the structural description for priority encoder using VHDL. 3. Develop the project using VHDL to realize the function of a ripple carry adder and draw its RTL. 4. Write a VHDL description to design Flip Flops( RS, JK, D, T) and write its test bench. 6. Write a VHDL description to design 8:1 MUX using two 4:1 MUX. 7. Write a VHDL description to design 8:1 MUX and DEMUX. 8. Write a VHDL description to design a undown counter and write its test bench. 5. Write short notes on Variables, Signals and Constants in VHDL program structure. 6. Write a VHDL description to design any Sequential circuit.

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