8/12/03 Transistor Review

1
CMOS Transistors and Inverters
Dr. Jerry L. Hudgins
Department of Electrical Engineering
University of South Carolina
8/12/03 Transistor Review
2
Complimentary-MOS Logic (CMOS)
PMOS (P-channel enhancement-mode Metal Oxide Semiconductor transistor)
NMOS (N-channel enhancement-mode Metal Oxide Semiconductor transistor)
G
G
G G
G
G
D
D D
D
D D
S
S
S S
S
S
B
B
8/12/03 Transistor Review
3
Definition of Symbols
1 to 5 V/m Saturation Electric Field Value E
sat
0.1 to 0.5 m Effective Channel Length L
0.2 to 3 m Effective Channel Width W
3 to 10 fF/m
2
Oxide Capacitance per Unit Area C
ox
150 cm
2
/Vs Surface Hole Mobility
p
400 cm
2
/Vs Surface Electron Mobility
n
-0.8 to 0.8 V MOS Threshold Voltage V
T
-3 to 3 V Gate-Source Voltage V
GS
-3 to 3 V Drain-Source Voltage V
DS
1 A to 100 mA Drain Current I
D
Typical Values and Units Description Symbol
8/12/03 Transistor Review
4
Definitions of Some Derived Symbols
k

n
=
n
C
ox
=
n

ox
/t
ox
Process Transconductance Parameters (A/V
2
)
k

p
=
p
C
ox
=
p

ox
/t
ox
Gain Factors (A/V
2
)
k
n
= k

n
(W
n
/L
n
)
k
p
= k

p
(W
p
/L
p
)
8/12/03 Transistor Review
5
Metal Oxide Semiconductor
Field-Effect Transistor Behavior
In the resistive region of operation for NMOS:
) (
2
) (
2
) (
1
2 2
DS
DS
DS T GS ox n
DS
DS T GS
sat
DS
ox n
D
V
V
V V V
L
W
C
V
V V V
L
W
L E
V
C
I

|
.
|

\
|
=
(

|
.
|

\
|
+
=
L E
V
V
sat
DS
DS
+
=
1
1
) (
For long channels or small drain-source voltages, approaches 1 and the expression
for the drain current reduces to the traditionally used equation describing a MOSFET
in its resistive region of operation. V
DS
/L is approximately the average electric field
in the channel.
8/12/03 Transistor Review
6
Metal Oxide Semiconductor
Field-Effect Transistor Behavior
In the saturation region of operation for NMOS:
When the electric field in the channel reaches the saturation value, then all carriers
at the drain reach the saturation drift velocity (v
sat
= 10
5
cm/s) and the drain current
remains constant (to first order at I
Dsat
) with respect to increases in drain-source
voltage.
) ( ) (
2
) (
2
DSsat T GS ox sat DSsat
DSsat
DSsat T GS ox n Dsat
V V V W C v V
V
V V V
L
W
C I =
(

|
.
|

\
|
=
L E
V V
V V
V
sat
T GS
T GS
DSsat

+

=
1
8/12/03 Transistor Review
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PMOS Equations
In the saturation region of operation for PMOS:
) ( ) (
2
) (
2
DSsat T GS ox sat DSsat
DSsat
DSsat T GS ox p Dsat
V V V W C v V
V
V V V
L
W
C I =
(

|
.
|

\
|
=
L E
V V
V V
V
sat
T GS
T GS
DSsat

+

=
1
In the resistive region of operation for PMOS:
) (
2
) (
2
) (
1
2 2
DS
DS
DS T GS ox p
DS
DS T GS
sat
DS
ox p
D
V
V
V V V
L
W
C
V
V V V
L
W
L E
V
C
I

|
.
|

\
|
=
(

|
.
|

\
|
+

=
L E
V
V
sat
DS
DS
+
=
1
1
) (
8/12/03 Transistor Review
8
CMOS Buffer/Inverter Static
Operation
VDD
Vin
Vout
CL
V
in
= 0 V V
GSp
< 0 V, V
GSn
= 0 V PMOS On, NMOS Off V
out
V
DD
V
in
= V
DD
V
GSp
= 0 V, V
GSn
> 0 V PMOS Off, NMOS On V
out
0 V
No dc current path from source to ground so ideally no power dissipation!
dc Transfer Curve
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5
Vin
V
o
u
t
8/12/03 Transistor Review
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Transfer Curve Information
Gate threshold voltage, V
TH
Noise Margins
Small-signal gain of gate at its threshold
voltage
dc Transfer Curve
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5
Vin
V
o
u
t
8/12/03 Transistor Review
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Threshold Voltage
VDD
Vin
Vout
CL
Gate Threshold Voltage is defined as
V
TH
V
in
that gives the same value of V
out
It is the boundary between logic states.
dc Transfer Curve with Gate Threshold
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5
Vin
V
o
u
t
V
TH
= 1.43 V for this example
NMOS off
PMOS res
NMOS sat
PMOS res
NMOS res
PMOS sat
NMOS sat
PMOS sat
NMOS off
PMOS res
8/12/03 Transistor Review
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r
V
V V r
V
V
V
DSsatp
Tp DD
DSsatn
Tn
TH
+
|
|
.
|

\
|
+ + +
|
.
|

\
|
+
=
1
2 2
n satn
p satp
DSsatn
n
n
n
DSsatp
p
p
p
DSsatn n
DSsatp p
W v
W v
V
L
W
V
L
W
V k
V k
r =
|
|
.
|

\
|
|
|
.
|

\
|
= =

Threshold Voltage
Assumes identical oxide thicknesses for NMOS and
PMOS, and ignores channel length modulation
effects.
8/12/03 Transistor Review
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Noise Margins
VDD
Vin
Vout
CL
Noise Margins are defined as:
NM
L
V
IL
-V
OL
=Max. input for logic 0 Nominal value of logic 0
NM
H
V
OH
-V
IH
= Nominal value of logic 1 Min. value for logic 1
dc Transfer Curve
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5
Vin
V
o
u
t
The points corresponding
to V
IL
and V
IH
are defined
where the gain is 1.
i.e. dV
out
/dV
in
= -1
Slope is -1
V
OH
V
IL
V
IH
V
OL
Noise margins are the difference in what the
nominal output voltage is at a given logic level and
what the input of a similar gate must see to
interpret the level correctly.
8/12/03 Transistor Review
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Small-signal Gain
VDD
Vin
Vout
CL
Must have voltage gain > 1
otherwise signals will fall below V
TH
after passing through several gates.
Minimum allowable value for
absolute value of voltage gain of a
digital gate is about . Typical
gains are from 2 to 50.
For this example:
2
26
26
1
1
= = = =
TH
V
in
out
v
dV
dV
A g
dc Transfer Curve
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5
Vin
V
o
u
t
Slope of curve
around
threshold
voltage
8/12/03 Transistor Review
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Calculation of Noise Margins
VDD
Vin
Vout
CL
dc Transfer Curve
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5
Vin
V
o
u
t
Linearize the transfer curve as shown with
the slope between the transitions equal to the
gain, g, at V
TH
.
V
OH
V
IL
V
IH
V
OL
8/12/03 Transistor Review
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Calculation of Noise Margins
dc Transfer Curve
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5
Vin
V
o
u
t
V
OH
V
IL
V
IH
V
OL
From the definition of gain and the nominal values of the gate:
From the equation of the slanted line:
Therefore combining the top two equations:
IL IH
DD
IH IL
OL OH
V V
V
V V
V V
g

=
0
g
V
V V
TH
TH IH
=
g
V V
V V
TH DD
TH IL

+ =
for large gain
TH DD TH OH
TH
TH DD IH OH H
V V V V
g
V
V V V V NM + = =
TH OL TH
TH DD
TH IL OL IL L
V V V
g
V V
V V V V NM

+ = = =
for large gain
8/12/03 Transistor Review
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Calculation of Gain at V
TH
Write a nodal equation with the drain currents of each
transistor equal to each other and V
GSn
= V
in
, V
DSn
= V
out
,
V
GSp
= V
in
V
DD
, and V
DSp
= V
out
V
DD
.
Next, differentiate V
out
with respect to V
in
and solve for
dV
out
/dV
in
) (
2
1
2 2
) 1 ( ) 1 (
p n
DSsatn
Tn TH
DSsatp
Tp DD TH DSsatp p p
DSsatn
Tn TH DSsatn n n
DD p TH p DSsatp p TH n DSsatn n
V
V V
r
V
V V V V k
V
V V V k
V V V k V V k
g

|
.
|

\
|

+

|
|
.
|

\
|
+
|
.
|

\
|

+ + +
=
Channel-length modulation factors, , CANNOT be ignored for
this analysis (depletion region at drain-end encroaches on
channel and reduces its effective length thus causing drain
current to increase).
8/12/03 Transistor Review
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Channel-Length Modulation Factor
) 1 (
DS Dsat D
V I I + =
)
`

+
(

+
=
E
DSsat DS
a DS
E
DSsat DS
a
V
V V
l L V
V
V V
l
1 ln
1 ln

3 / 1 2 / 1 6 / 1
) 22 . 0 (
ox j a
t d cm l =
d
j
is the drain junction depth V
E
is determined empirically and is < 1 V
Y.A. El-Mansy and A.R. Boothroyd, A simple two-dimensional model for IGFET operation in the
saturation region, IEEE Trans. ED, vol. 24, pp. 254-262, 1977.
P.K. Po, Approaches to scaling, pp. 1-37, Advanced MOS Device Physics, N.G. Einspruch and G.
Gildenblat, eds., VLSI Electronics, vol. 18, Academic Press, New York, 1989.
N.D. Arora, MOSFET Models for VLSI Circuit Simulation-Theory and Practice, Computational
Microelectronics Series, S. Selberherr, ed., Springer-Verlag, New York, 1993.
H.C. de Graaff and F.M. Klaassen, Compact Transistor Modeling for Circuit Design, Springer-Verlag, New
York, 1990.
8/12/03 Transistor Review
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Parasitic Capacitances Influencing
CMOS Inverter Pair
VDD
Vin
Vout
Cw
VDD
Vout2
M4
M1
M2
M3
C
g4
C
g3
C
gd12
C
db2
C
db1
8/12/03 Transistor Review
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Miller Capacitances
VDD
Vin
Vout
Cw
VDD
Vout2
M4
M1
M2
M3
C
g4
C
g3
C
gd12
C
db2
C
db1
Cgd1
Vin
Vout
M1
'
V
'
V
2Cgd1
Vin
Vout
M1
'
V
'
V
Can replace gate-drain capacitances (Miller caps) with
equivalent at output wrt ground because of V change
at each capacitance terminal.

n dn oxn n GDOn gd
W x C W C C 2 2
1
= =
p dp oxp p GDOp gd
W x C W C C 2 2
2
= =
C
GDO
is the overlap
capacitance per unit
width, x
d
is the extension
of the drain implantation
under the gate oxide.
8/12/03 Transistor Review
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Fan-out Gate Capacitances
VDD
Vin
Vout
Cw
VDD
Vout2
M4
M1
M2
M3
C
g4
C
g3
C
gd12
C
db2
C
db1
) 2 ( ) 2 (
) ( ) (
4 3
p p p oxp n n n oxn
p p oxp p GDOp p GSOp n n oxn n GDOn n GSOn g g out fan
L x W C L x W C
L W C W C W C L W C W C W C C C C
+ + + =
+ + + + + = + =

Each gate capacitance is made of the oxide capacitance along

the channel plus the overlap capacitance between gate oxide
and source, plus the overlap capacitance between the drain and
gate oxide.
8/12/03 Transistor Review
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Wiring Capacitance
VDD
Vin
Vout
Cw
VDD
Vout2
M4
M1
M2
M3
C
g4
C
g3
C
gd12
C
db2
C
db1
The wiring capacitance, C
w
, depends upon the length
and width of the connecting traces and is a function of
the distance between load gates and driving gates, as
well as the number of load gates.
8/12/03 Transistor Review
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Diffusion Capacitances
between Drain and Body
VDD
Vin
Vout
Cw
VDD
Vout2
M4
M1
M2
M3
C
g4
C
g3
C
gd12
C
db2
C
db1
C
db
is due to the reverse biased pn-junction between the drain and body
AND is the capacitance that is non-linear and voltage dependent.
m
bi
D
j
j db
V
V
C
C C
|
|
.
|

\
|

= =
1
0
|
|
.
|

\
|
+
=
D A
D A
bi
si
j
N N
N N
V
q
C
2
0

C
j0
is the zero-biased junction capacitance per unit area.
V
D
is the applied body voltage with respect to the drain.
V
bi
is the built-in potential of the junction (typically about
0.64 V).
m is the grading factor (1/2 for abrupt junctions and 1/3 for
linear junctions).
N
A
and N
D
are the acceptor and donor impurity
concentrations, respectively.
8/12/03 Transistor Review
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Approximate Diffusion Capacitance
between Drain and Body
|
|
.
|

\
|
+
=
D A
D A
bi
si
j
N N
N N
V
q
C
2
0

Using an approximation for the large-signal swing in
capacitance and in terms of the grading factor gives:
0
) ( ) (
j eq
low high
low j high j
D
j
eq
C K
V V
V Q V Q
V
Q
C =

=
] ) ( ) [(
) 1 )( (
1 1 m
low bi
m
high bi
low high
m
bi
eq
V V V V
m V V
V
K

=
8/12/03 Transistor Review
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Example
VDD
Vin
Vout
Cw
VDD
Vout2
M4
M1
M2
M3
C
g4
C
g3
C
gd12
C
db2
C
db1
The propagation delay is defined by the time between the
50% transitions of the input and output. For a CMOS inverter
this is the time instance where V
out
reaches 1.25 V as the
output voltage swing from rail-to-rail is 2.5 V (V
DD
= 2.5 V).
The drain-body capacitance is linearized over the voltage
intervals of 2.5 V to 1.25 V for high-to-low and 0 V to 1.25 V
for low-to-high transitions of the NMOS (M1). A similar
computation is performed for the PMOS.
8/12/03 Transistor Review
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Example (page 2)
VDD
Vin
Vout
Cw
VDD
Vout2
M4
M1
M2
M3
C
g4
C
g3
C
gd12
C
db2
C
db1
For the NMOS:
V
high
= -2.5 V
V
low
= -1.25 V
During the high-to-low transition of the output:
For the PMOS:
V
high
= -2.5 V
V
low
= -1.25 V
During the low-to-high transition of the output:
For the NMOS:
V
high
= -1.25 V
V
low
= 0 V
For the PMOS:
V
high
= -1.25 V
V
low
= 0 V
8/12/03 Transistor Review
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Example (page 3)
VDD
Vin
Vout
Cw
VDD
Vout2
M4
M1
M2
M3
C
g4
C
g3
C
gd12
C
db2
C
db1
For the NMOS:
Bottom plate: m=0.5, V
bi
=0.9 V
Side Wall: m=0.44, V
bi
=0.9 V
During both transitions of the output:
For the PMOS:
Bottom plate: m=0.48, V
bi
=0.9 V
Side Wall: m=0.32, V
bi
=0.9 V
8/12/03 Transistor Review
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Example (page 4)
0.86
PMOS
Sidewall
(H-L)
0.79
PMOS
Bottom Plate
(H-L)
0.61
NMOS
Sidewall
(H-L)
0.57
NMOS
Bottom Plate
(H-L)
0.7
PMOS
Sidewall
(L-H)
0.59
PMOS
Bottom Plate
(L-H)
0.81
NMOS
Sidewall
(L-H)
0.79
NMOS
Bottom Plate
(L-H)
K
eq
2.375 0.7 2.375 0.7 1.125/0.25 PMOS
1.875 0.3 1.875 0.3 0.375/0.25 NMOS
P
s
(m) A
s
(m
2
) P
D
(m)
A
D
(m
2
) W/L
6.05 6.16 C
L
(total)
0.12 0.12 *C
w
2.28 2.28 C
g4
0.76 0.76 C
g3
1.15 1.5 C
db2
0.90 0.66 C
db1
0.61 0.61 C
gd2
0.23 0.23 C
gd1
Value (fF)
Low to High
Value (fF)
High to Low
Capacitor
8/12/03 Transistor Review
28
Propagation Delay
During the high-to-low transition, the PMOS is turning off
and the NMOS is on. Represent the NMOS by its average
equivalent resistance during the load capacitance discharge.
Use similar expressions for the low-to-high transition.

|
.
|

\
|

+
=
DD
DD
V
V
DD
Dsat
DD
Dsat DD
eq
V
I
V
dV
V I
V
V
R
2 /
9
7
1
4
3
) 1 ( 2 /
1

=
2
) (
2
'
DSsat
DSsat t DD Dsat
V
V V V
L
W
k I
HL L eqn pHL
C R t

= 69 . 0
LH L eqp pLH
C R t

= 69 . 0
Propagation Delay of Inverter is average of the
two values:
) ( 345 . 0 ) ( 345 . 0
2
eqn eqp Lavg HL L eqn LH L eqp
pLH pHL
p
R R C C R C R
t t
t + + =
+
=

8/12/03 Transistor Review
29
Metastability
Two inverters cascaded, with a gain in the transition
region >1, has two stable operating points, A and B, and
one metastable operating point, C.
NOTE: Gain near A and B is << 1.
8/12/03 Transistor Review
30
Metastability
In figure (a) if initial
operating point is C,
any noise will cause
transition to a stable
operating point such
as A.
In figure (b) if initial
operating point is
away from C, any
noise will cause
transition back to a
stable operating point
such as A.
8/12/03 Transistor Review
31
SPICE Models
Level 1:
Shichman-Hodges model based on square-
law, long-channel expressions between
current and voltage.
DOES NOT HANDLE SHORT CHANNEL
EFFECTS!
Level 2
Geometry based model that incorporates
velocity saturation, mobility dependencies,
and drain-induced barrier lowering.
8/12/03 Transistor Review
32
SPICE Models (cont.)
Level 3:
Semiempirical model combining analytical and
empirical expressions. Uses measured data for model
parameters.
Works well for channel lengths down to about 1 m.
Berkeley Short-channel IGFET Model (BSIM)
Analytically simple with a small number of
parameters derived from empirical data.
BSIM3v3 model (Level 49) has over 200 parameters,
most related to modeling 2
nd
order effects.
Manufacturer provides a set of models valid over a
limited parameter space of L and W (delineated by
LMIN, LMAX, WMIN, and WMAX, called a bin).
http://bwrc.eecs.berkeley.edu/IcBook/
for BSIM and Matlab models
8/12/03 Transistor Review
33
SPICE Models-Example File
A CMOS Inverter using Level 3 Model for 0.8 um Process
*
.MODEL nch NMOS
+ LEVEL=3 PHI=0.70 TOX=1.0E-08 XJ=0.20U TPG=1
+ VTO=0.8 DELTA=2.5E-01 LD=4.0E-08 KP=1.88E-04
+ UO=545 THETA=2.5E-01 RSH=2.1E+01 GAMMA=0.62
+ NSUB=1.4E+17 NFS=7.1E+11 VMAX=1.9E+05 ETA=2.2E-02
+ KAPPA=9.7E-02 CGDO=3.7E-10 CGSO=3.7E-10 CGBO=4.0E-10
+ CJ=5.4E-04 MJ=0.6 CJSW=1.5E-10 MJSW=0.3 PB=0.99
*
.MODEL pch PMOS
+ LEVEL=3 PHI=0.70 TOX=1.0E-08 XJ=0.20U TPG=-1
+ VTO=-0.9 DELTA=2.5E-01 LD=6.7E-08 KP=4.45E-05
+ UO=130 THETA=1.8E-01 RSH=3.4E+00 GAMMA=0.52
+ NSUB=9.8E+16 NFS=6.5E+11 VMAX=3.1E+05 ETA=1.8E-02
+ KAPPA=6.3E+00 CGDO=3.7E-10 CGSO=3.7E-10 CGBO=4.3E-10
+ CJ=9.3E-04 MJ=0.5 CJSW=1.5E-10 MJSW=0.3 PB=0.95
*
M1 3 2 0 0 nch W=5u L=0.8u AS=7.2p PS=7.6u AD=7.2p PD=7.6u
M2 3 2 1 1 pch W=5u L=0.8u AS=9.9p PS=9.1u AD=9.9p PD=9.1u
CL 3 0 0.05pF
*
VDD 1 0 3.3V
VIN 2 0 PULSE(0 3.3 0 100p 100p 5n 10n)
*
.TRAN 0.05n 10n
*
.DC VIN 0V 3.3V 0.01V
*
.PROBE
*
.END
8/12/03 Transistor Review
34
References for CMOS Transistors
Operation and Modeling of the MOS
Transistor, 2
nd
ed., Y. Tsividis, McGraw-
Hill, Boston, 1999.
ISBN 0-07-065523-5
Digital Integrated Circuits A Design
Perspective, 2
nd
ed., J.M. Rabaey, A.
Chandrakasan, and B. Nikolic, Prentice
Hall Electronics and VLSI Series, C.G.
Sodini, ed., Upper Saddle, NJ, 2003.
ISBN 0-13-597444-5