SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCLS147B DECEMBER 1982 REVISED MAY 1997

D D D

High-Current 3-State Outputs Drive Bus Lines Directly or up to 15 LSTTL Loads Bus-Structured Pinout Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

SN54HC573A . . . J OR W PACKAGE SN74HC573A . . . DW OR N PACKAGE (TOP VIEW)

description
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE 1D 2D 3D 4D 5D 6D 7D 8D GND

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE

SN54HC573A . . . FK PACKAGE (TOP VIEW)

3D 4D 5D 6D 7D

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

OE VCC 1Q 2Q 3Q 4Q 5Q 6Q

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54HC573A is characterized for operation over the full military temperature range of 55C to 125C. The SN74HC573A is characterized for operation from 40C to 85C.
FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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8D GND LE 8Q 7Q

2D 1D

SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCLS147B DECEMBER 1982 REVISED MAY 1997

logic symbol
OE LE 1D 2D 3D 4D 5D 6D 7D 8D 1 11 2 3 4 5 6 7 8 9 EN C1 1D 19 18 17 16 15 14 13 12 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

OE LE 1 11

C1 1D 2 1D

19

1Q

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA Package thermal impedance, JA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero.

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SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCLS147B DECEMBER 1982 REVISED MAY 1997

recommended operating conditions

SN54HC573A MIN VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO tt TA Low-level input voltage Input voltage Output voltage Input transition (rise and fall) time Operating free-air temperature VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 4.5 V VCC = 6 V 2 1.5 3.15 4.2 0 0 0 0 0 0 0 0 55 0.5 1.35 1.8 VCC VCC 1000 500 400 125 NOM 5 MAX 6 SN74HC573A MIN 2 1.5 3.15 4.2 0 0 0 0 0 0 0 0 40 0.5 1.35 1.8 VCC VCC 1000 500 400 85 C ns V V V V NOM 5 MAX 6 UNIT V

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 2V IOH = 20 A VOH VI = VIH or VIL IOH = 6 mA IOH = 7.8 mA IOL = 20 A VOL VI = VIH or VIL IOL = 6 mA IOL = 7.8 mA II IOZ ICC Ci VI = VCC or 0 VO = VCC or 0 VI = VCC or 0, IO = 0 4.5 V 6V 4.5 V 6V 2V 4.5 V 6V 4.5 V 6V 6V 6V 6V 2 V to 6 V 3 MIN 1.9 4.4 5.9 3.98 5.48 TA = 25C TYP MAX 1.998 4.499 5.999 4.3 5.8 0.002 0.001 0.001 0.17 0.15 0.1 0.01 0.1 0.1 0.1 0.26 0.26 100 0.5 8 10 SN54HC573A MIN 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1000 10 160 10 MAX SN74HC573A MIN 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1000 5 80 10 nA A A pF V V MAX UNIT

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SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCLS147B DECEMBER 1982 REVISED MAY 1997

timing requirements over recommended operating free-air temperature range (unless otherwise noted)
VCC 2V tw Pulse duration, LE high 4.5 V 6V 2V tsu Setup time, data before LE 4.5 V 6V 2V th Hold time, data after LE 4.5 V 6V TA = 25C MIN MAX 80 16 14 50 10 9 20 5 5 SN54HC573A MIN 120 24 20 75 15 13 24 5 5 MAX SN74HC573A MIN 100 20 17 63 13 11 24 5 5 ns ns ns MAX UNIT

switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V D tpd d LE Any Q Q 4.5 V 6V 2V 4.5 V 6V 2V ten OE Any Q 4.5 V 6V 2V tdis OE Any Q 4.5 V 6V 2V tt Any Q 4.5 V 6V TA = 25C MIN TYP MAX 77 26 23 87 27 23 68 24 21 47 23 21 28 8 6 175 35 30 175 35 30 150 30 26 150 30 26 60 12 10 SN54HC573A MIN MAX 265 53 45 265 53 45 225 45 38 225 45 38 90 18 15 SN74HC573A MIN MAX 220 44 38 220 44 38 190 38 32 190 38 32 75 15 13 ns ns ns ns UNIT

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SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCLS147B DECEMBER 1982 REVISED MAY 1997

switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC 2V D tpd d LE Any Q Q 4.5 V 6V 2V 4.5 V 6V 2V ten OE Any Q 4.5 V 6V 2V tt Any Q 4.5 V 6V MIN TA = 25C TYP MAX 95 33 21 103 33 29 85 29 26 60 17 14 200 40 34 225 45 38 200 40 34 210 42 36 SN54HC573A MIN MAX 300 60 51 335 67 57 300 60 51 315 63 53 SN74HC573A MIN MAX 250 50 43 285 57 48 250 50 43 265 53 45 ns ns ns UNIT

operating characteristics, TA = 25C

PARAMETER Cpd Power dissipation capacitance per latch TEST CONDITIONS No load TYP 50 UNIT pF

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SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SCLS147B DECEMBER 1982 REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION

VCC S1 RL PARAMETER ten tPZH tPZL tPHZ tPLZ 50 pF or 150 pF 1 k RL 1 k CL 50 pF or 150 pF 50 pF S1 Open Closed Open Closed Open S2 Closed Open Closed Open Open

From Output Under Test CL (see Note A)

Test Point

S2

tdis

tpd or tt LOAD CIRCUIT

High-Level Pulse

VCC 50% tw 50% 0V VCC 50% 50% 0V VOLTAGE WAVEFORMS PULSE DURATIONS

Reference Input tsu Data Input 50% 10% 90% tr

50% th 90%

VCC 0V VCC 50% 10% 0 V tf

Low-Level Pulse

VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES

VCC Input 50% tPLH In-Phase Output 50% 10% tPHL Out-ofPhase Output 90% 50% 10% tf 90% tr tPLH 50% 10% 90% tr VOH VOL 50% 0V tPHL 90% VOH 50% 10% V OL tf

Output Control (Low-Level Enabling) tPZL Output Waveform 1 (See Note B) tPZH Output Waveform 2 (See Note B)

VCC 50% 50% 0V tPLZ VCC 50% 10% VCC VOL VOH 0V tPHZ

50%

90%

VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

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