Drawing CMOS Layout For IC Design (Crestopher Saint)

CMOS 1 Drawing CMOS Layout for IC Design Beginning Level
DTT6530
CMOS 1 Drawing CMOS Layout for IC Design Beginning Level
January 1996
Technical Publications and Training Design Technology
Published by Technical Publications and Training, Intel Corporation Copyright Intel Corporation 1996
Document requests:
http://ats.intel.com/Docs/
Technical information: Document comments:
Phil Sandoval, 356-6348, FM5-43, psandova@pcocd2 Mary Sullivan, 765-5576, RN4-43, msulliv@scdt
CMOS 1
Table of Contents
Chapter 1: Introduction to the Course

Introduction to the Course.................................................................................. 1-2
Chapter 2: Introduction to CMOS 1 Drawing CMOS Layout for IC Design Beginning Level
Chapter Overview .............................................................................................. 2-2 What is an IC?.................................................................................................... 2-3 How Is an IC Designed? .................................................................................... 2-4 Basic Layout Design Tasks................................................................................ 2-5 What Are the Design Data Representations? .................................................... 2-6
Chapter 3: How to Interpret Logic-level Schematics

Chapter Overview .............................................................................................. 3-2
Lesson 3-1: How to Identify the Parts of a Logic-level Schematic

Lesson Overview................................................................................................ 3-4 What Is a Logic-level Schematic? ...................................................................... 3-5 Lab 3-1.a: Identify the Nodes of the Logic-level Schematic ............................... 3-6 Logic Symbols of the Basic Logic Functions ...................................................... 3-8 Lab 3-1.b: Identify the Logic Symbols of the Logic-level Schematic .................. 3-9 Logic-level Schematic Drawing Conventions ................................................... 3-10 Lab 3-1.c: Identify the Parts of the Logic-level Schematic ............................... 3-12
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Lesson 3-2: How to Describe the Function of a Logic Symbol

Lesson Overview.............................................................................................. 3-14 What Are the Standard Logic Functions? ........................................................ 3-15 Practice 3-2.a: Evaluate Boolean Algebra Equations ...................................... 3-18 What Are Truth Tables? ................................................................................... 3-19 How Is the Number of Rows for a Truth Table Determined? ........................... 3-20 Practice 3-2.b: Determine the Number of Columns and Rows for a Truth Table..................................................................................... 3-21 How Are Input Values for a Truth Table Filled In? ........................................... 3-23 Practice 3-2.c: Fill in the Input Values for a Truth Table .................................. 3-26 Output Values of the Truth Tables ................................................................... 3-27 Practice 3-2.d: Describe Logic Functions with Truth Tables ............................ 3-29 Chapter Summary ............................................................................................ 3-36
Chapter 4: How to Convert a Logic-level Schematic to a Transistor-level Schematic

Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic

Lesson Overview................................................................................................ 4-4 What Is a Transistor-level Schematic?............................................................... 4-5 What Is a Transistor? ......................................................................................... 4-6 Nodes of a Transistor-level Schematic .............................................................. 4-9 Transistor Representations of the Logic-level Schematics .............................. 4-10 Lab 4-1: Identify the Parts of Transistor-level Schematics ............................... 4-12
Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol

Lesson Overview.............................................................................................. 4-17 Values that Turn a Transistor On or Off ........................................................... 4-18 How Are Truth Table Values Verified? ............................................................. 4-19 Practice 4-2: Verify the Transistor-level Function of the Logic Symbols .......... 4-22
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Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic

Lesson Overview.............................................................................................. 4-28 Logic Functions Defined with Transistors ........................................................ 4-29 How Is a Logic-level Schematic Converted to a Transistor-level Schematic? . 4-30 Practice 4-3: Convert a Logic-level Schematic to a Transistor-level Schematic ........................................................................................................ 4-32 What is Complex Logic? .................................................................................. 4-33 Order of the Series Transistors ........................................................................ 4-34 How Is a Complex Logic-level Schematic Converted to N-Type Transistors? . 4-35 Lab 4-3.a: Convert Complex Logic-level Schematics to N-Type Transistors ... 4-38 How Is a Complex Logic-level Schematic Converted to P-Type Transistors? . 4-40 Lab 4-3.b: Convert Complex Logic-level Schematics to P-Type Transistors ... 4-43 Lab 4-3.c: Convert Complex Logic-level Schematics to Transistor-level Schematics....................................................................................................... 4-44 Chapter Summary ............................................................................................ 4-45
Chapter 5: How to Create a Layout Drawing from a Transistor-level Schematic

Lesson 5-1: How to Identify a Transistor on the IC Cross Section

Lesson Overview................................................................................................ 5-4 What Is a Cross Section?................................................................................... 5-5 Layers of the Transistor Cross Section .............................................................. 5-6 Layers of the Die Cross Section......................................................................... 5-7 What Is a Diode?................................................................................................ 5-8 How Is a Transistor Turned On or Off? ............................................................ 5-10
Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section
Lesson Overview.............................................................................................. 5-14 What Is a Design Rule? ................................................................................... 5-15 Basic Process Design Rules ............................................................................ 5-16 How Are Process Design Rules Identified on the Transistor Cross Section? .. 5-17
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Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram

Lesson Overview.............................................................................................. 5-20 What Is a Stick Diagram?................................................................................. 5-21 Legend for a Stick Diagram.............................................................................. 5-22 Series and Parallel Transistors in a Stick Diagram .......................................... 5-23 How Is a Stick Diagram Created? .................................................................... 5-24 Lab 5-3.a: Create a Stick Diagram ................................................................... 5-26 How Is the Width of a Layout Drawing Estimated from a Stick Diagram? ....... 5-29 Lab 5-3.b: Estimate the Width of a Layout Drawing from a Stick Diagram ...... 5-31
Lesson 5-4: How to Get Better Layout Density with Node Sharing
Lesson Overview.............................................................................................. 5-34 What Is Node Sharing? .................................................................................... 5-35 How Is Node Sharing Achieved? ..................................................................... 5-36 Lab 5-4: Use Node Sharing to Increase Density .............................................. 5-38
Lesson 5-5: How to Estimate Area

Lesson Overview.............................................................................................. 5-40 Area Calculation............................................................................................... 5-41 Lab 5-5.a: Calculate Area ................................................................................ 5-42 Units of Measure Conversion ........................................................................... 5-43 Lab 5-5.b: Convert Units of Measure ............................................................... 5-44 Average Area per Transistor Calculation ......................................................... 5-46 Lab 5-5.c: Calculate the Average Area per Transistor ..................................... 5-47
Lesson 5-6: How to Calculate Resistance

Lesson Overview.............................................................................................. 5-50 What Is Resistance? ........................................................................................ 5-51 Lab 5-6.a: Calculate Resistance Values .......................................................... 5-53 How Is Sheet Resistance Calculated? ............................................................. 5-56 Lab 5-6.b: Calculate Sheet Resistance............................................................ 5-58
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Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing

Lesson Overview.............................................................................................. 5-60 What Is a Layout Drawing? .............................................................................. 5-61 What Is Transistor Size? .................................................................................. 5-62 How Is a Stick Diagram Converted to a Layout Drawing? ............................... 5-63 Lab 5-7.a: Convert a Stick Diagram to a Layout .............................................. 5-64 Visually Verifying a Layout Drawing ................................................................. 5-65 Lab 5-7.b: Visually Verify a Layout Drawing .................................................... 5-66
Lesson 5-8: How to Draw Layout with a Standard Cell Template

Lesson Overview.............................................................................................. 5-68 What Is a Standard Cell Template? ................................................................. 5-69 How Is a Layout Drawing Drawn with a Standard Cell Template?................... 5-70 Lab 5-8: Draw a Layout Drawing with a Standard Cell Template .................... 5-71
Lesson 5-9: How to Draw Layout to Meet Layout Restrictions

Lesson Overview.............................................................................................. 5-74 How Is a Transistor Drawn with Multiple Legs? ............................................... 5-75 How Is a Transistor Drawn with a Bent Gate? ................................................. 5-77 Lab 5-9: Draw Layout to Meet Layout Restrictions .......................................... 5-79 Chapter Summary ............................................................................................ 5-80
Appendix A: Glossary
Terms .................................................................................................................A-2
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Introduction to the Course

Introduction The goal of this course is to provide the information and practice needed to create layout drawings with CMOS technology. This course is structured around the three main tasks of the basic layout design process. A chapter is devoted to each task as follows:
G G G
Structure
Interpret Logic-Level Schematics Convert Logic-Level Schematics to Transistor-Level Schematics Create Layout Drawings from Transistor-Level Schematics
Chapters are divided into lessons, the number of lessons depending on the complexity and scope of the topic being taught. Each lesson has a practice or lab, which gives hands-on experience. Objectives Every chapter and lesson has a clearly stated objective so that you will know exactly what you are expected to learn. The course material is presented in a mapped-page format.
G
Format
Information is categorized as follows. Concept: Provides denitions and examples Process: Explains how something works Procedure (practice/lab): Tells how to perform a task Guidelines: Provide suggestions for performing a task or tackling a problem
Margin labels (labels on the left side of the page) provide visual cues to help increase information access and retrieval time. The labels refer to the contents of that paragraph or block of information.
The instructor presents information using foils.

G
The foils follow the sequence of the student material but contain only key points. A page number on the upper left corner of the foil indicates the corresponding page in your course guide.
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Introduction to the Course (continued)

Practices and Labs You will be given two types of exercises.
G G
Practice: Reinforces material for general knowledge building. Lab: Reinforces material directly related to a job task.
Acknowledgments
Special thanks go to Phil Sandoval, who created the class that this one is based on. Also, thanks to all who helped with the content of this class: Brian Cyphert, Mark Drake, Barbara Drummer, Gell Gellman, Myrna Irwin, Brent Jensen, Mary Kamprath, Lynn Olson, Manhaz Padash, Phil Sandoval, and Seema Shafajoo.
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Chapter 2: Introduction to CMOS 1
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Chapter Overview
Introduction This class covers the major job tasks for creating basic CMOS layout. Additional knowledge is presented to aid in the understanding of the layout design process. In this class, you will learn how to convert logic-level schematics to transistor-level schematics to layout drawings, and how to create layout drawings to design specications. The following topics are covered in this chapter: Topics Page
Objectives
Topics
What is an IC? .................................................................................. How Is an IC Designed? .................................................................. Basic Layout Design Tasks .............................................................. What Are the Design Data Representations? ...................................
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What is an IC?
Introduction Integrated Circuits (ICs) are used in millions of applications. Producing ICs is the primary business of Intel, which holds 75% of the marketplace. An IC is a single piece of silicon that performs various electronic functions. Examples of ICs, along with their applications, include the following:
Denition
Examples
Type of IC microprocessor/CPU memory micro-controller imbedded processor/controller computers
Use
data storage and retrieval communication between ICs printers, anti-lock brakes
CMOS Technology
Complementary Metal Oxide Semiconductor (CMOS) is the name of the technology used to create ICs. The graphic below shows a silicon wafer and one IC in the wafer.
Silicon Wafer IC
Example
Periphery: Connections are made to the periphery of the IC with wires.
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How Is an IC Designed?
Introduction Process There are many phases required in the creation of an IC. The following gure shows the IC design process, an example of each process step, and who implements that step:
Design Process Micro-Architecture Design and Verication
Example Dene the product
Who Implements Engineer
Logic Design and Verication
Describe product functions
Engineer
Circuit Design and Performance Verication
Implement product functions
Engineer
Layout Design and Verication
Represent functions physically
Mask Designer
Mask Generation
Transfer physical representation onto template
Vendor
Tapeout and Fabrication
Create the product from the template
Manufacturer
Tapeout and First Silicon
Create the rst sample of the actual product
Manufacturer
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Basic Layout Design Tasks

Introduction The basic layout design tasks are part of the layout design and verication stage of the IC design process. The mask designer takes the design from logic-level schematics to transistor-level schematics to drawn layout. The following gure shows how the basic layout design tasks t into the IC design process:
Design Process Micro-Architecture Design and Verication
Layout Design Tasks
Logic Design and Verication Basic Layout Design Tasks Interpret Logic-level Schematics
Circuit Design and Performance Verication
Layout Design and Verication
Convert Logic-level to Transistor-level Schematics Create Layout Drawings from Transistor-level Schematics
Mask Generation
Tapeout and Fabrication
Tapeout and First Silicon
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What Are the Design Data Representations?

Introduction There are different ways to represent the design of an integrated circuit. The design data representations are graphical ways of displaying the design data. As you progress through the layout design tasks, you will work with an increasing amount of design data detail. The gure below shows one electrical function an inverter in the logic-level schematic, transistor-level schematic, and layout representation.
Logic-level Schematic
Denition
Examples
Basic Layout Design Tasks
Interpret Logic-level Schematics
Transistor-level Schematic
Convert Logic-level to Transistor-level Schematics Create Layout Drawings from Transistor-level Schematics Layout Drawing
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Convert Logic-level to Transistor-level Schematic
Create Layout Drawing from Transistor-level Schematic
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Chapter Overview
Introduction Logic-level schematics are a standard way for the engineers to communicate the functions of an IC to other project members. In this chapter, you will learn to identify the parts of logic-level schematics and describe the function of the logic symbols. The following topics are covered in this chapter: Topic Page
Objective
Topics
Lesson 3-1: How to Identify the Parts of a Logic-level 3-3 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lesson 3-2: How to Describe the Function of a Logic Symbol 3-13 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
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Lesson 3-1 Overview

Introduction To accomplish the task of interpreting the logic-level schematic, you must be able to identify its parts. The logic-level schematic is the rst graphical data representation of the ICs function. In this lesson, you will learn to identify the parts of a logic-level schematic. The following topics are covered in this lesson: Topic Page
Objective
Topics
What Is a Logic-level Schematic? . . . . . . . . . . . . . . . . . . . . 3-5 Lab 3-1.a: Identify the Nodes of the Logic-level Schematic 3-6 Logic Symbols of the Basic Logic Functions . . . . . . . . . . . 3-8 Lab 3-1.b: Identify the Logic Symbols of the Logic-level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Logic-level Schematic Drawing Conventions . . . . . . . . . . . 3-10 Lesson 3-1: How to Identify the Parts of a Logic-level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
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What Is a Logic-level Schematic?

Introduction Mask designers must be able to identify the parts of a logic-level schematic in order to convert it into a transistor-level schematic. The logic-level schematic is a short-hand representation of the actual functions that make up the IC. Two main parts of logic-level schematics are logic symbols and nodes.
G
Denition
Logic symbol: a short-hand representation for basic or complex logic functions. Node: an electrical path between logic symbols or the inputs and output of the logic symbols. Nodes are drawn as lines. There are three types of nodes on a logic-level schematic, as follows: Input: Supply information to the logic symbol. Output: Carry information away from the logic symbol. Internal: Carry information between logic symbols.
Example 1
The following gure is a logic-level schematic containing a single logic symbol with the logic symbol and nodes labeled.
Logic Symbol
OUT
Nodes
Example 2
The following gure is a logic-level schematic containing two logic symbols with the logic symbols and nodes labeled.
Logic Symbols
A Input Nodes Internal Node Output Node B C
OUT
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Lab 3-1.a: Identify the Nodes of the Logic-level Schematic

Introduction Now that you know two of the main parts of a logic-level schematic, logic symbols and nodes, you will identify the logic symbols and nodes in a logic-level schematic.
Instructions for Lab 3-1.a 1. Given the following logic-level schematic, complete the exercises.
a. b. c. d. e. f.
How many logic symbols are in the logic-level schematic? Color each of the nodes in the logic-level schematic a different color. How many nodes are in the logic-level schematic? How many input nodes are in the logic-level schematic? How many internal nodes are in the logic-level schematic? How many output nodes are in the logic-level schematic?
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Instructions for Lab 3-1.a 2. Given the following logic-level schematic, complete the exercises.
a. b. c. d. e. f.
How many logic symbols are in the logic-level schematic? Color each of the nodes in the logic-level schematic a different color. How many nodes are in the logic-level schematic? How many input nodes are in the logic-level schematic? How many internal nodes are in the logic-level schematic? How many output nodes are in the logic-level schematic?
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Logic Symbols of the Basic Logic Functions

Introduction Following are the standard logic symbols used to represent the basic functions. A logic symbols is always drawn with its input and output nodes. The Inverter logic symbol is as follows:
A OUT
Inverter Logic Symbol
AND Logic Symbol
The AND logic symbol is as follows:

A B OUT
NAND Logic Symbol
By inverting the output of the AND logic symbol (represented by the bubble on the output node), the NAND logic symbol is created. The 2-input NAND logic symbol is as follows:
A B OUT
OR Logic Symbol
The OR logic symbol is as follows:

A B OUT
NOR Logic Symbol
By inverting the output of the OR logic symbol (represented by the bubble on the output node), the NOR logic symbol is created. The 2-input NOR logic symbol is as follows:
A B OUT
Number of Input Nodes
There can be more than two input nodes on the AND, NAND, OR, and NOR logic symbols. However, the inverter can only have one input node. There is only one output node on the basic logic symbols used in this class.
Number of Output Nodes
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Lab 3-1.b: Identify the Logic Symbols of the Logic-level Schematic

Introduction Now that you know the name of the function that each logic symbol represents, you will identify the function name and the number of inputs for each logic symbol in a logic-level schematic.
Instructions for Lab 3-1.b 1. Given the following logic-level schematic, ll in the table below with the names of logic symbols and the number of input nodes each logic symbol has.
5 4
Logic Symbol Number 1 2 3 4 5
Logic Symbol Function
Number of Input Nodes
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Logic-level Schematic Drawing Conventions

Introduction To draw and interpret logic-level schematics, you must follow a set of conventions. Each project has slightly different conventions. The following are the conventions for this class. The orientation of the logic symbol does not affect its functionality; the following inverter logic symbols are all equivalent.
Logic Symbol Orientation
Connecting Nodes
Nodes to be connected are drawn with a dot connecting the lines. When nodes cross without a dot, they are not connected. Connected Nodes:
A A
A A
Crossing Unconnected Nodes:

A B
Example: Connected and crossing nodes are drawn in a schematic as follows:

Nodes cross, but are not connected
Nodes are connected
continued...
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Logic-level Schematic Drawing Conventions (continued)

Supply Voltages
G
Vcc or Power is the logical high: 1

Vcc
Vss or Ground is the logical low: 0
Vss
Example: A NAND logic symbol with one input node connected to Vcc and the other input node connected to Vss.
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Lab 3-1.c: Identify the Parts of the Logic-level Schematic

Introduction Now that you know how to identify the function of the logic symbols, and the node drawing convention, you will identify the function of the logic symbols and the number of unique nodes in a logic-level schematic.
Instructions for Lab 3-1.c 1. Given the following logic-level schematic, complete the following exercises.
1 2
3 4
a.
List the function names of the logic symbols. 1. 2. 3. 4.
b.
How many unique nodes are in the logic-level schematic?
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Lesson 3-2 Overview

Introduction To really understand the function of a logic symbol, you must be able to describe its function. In this lesson, you will learn how to describe the logic function of the logic symbols with truth tables. The following topics are covered in this lesson: Topic Page
Objective
Topics
What Are the Standard Logic Functions? . . . . . . . . . . . . . . 3-15 Practice 3-2.a: Evaluate Boolean Algebra Equations . . . . . 3-18 What Are Truth Tables? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 How Is the Number of Rows for a Truth Table Determined? 3-20 Practice 3-2.b: Determine the Number of Columns and Rows for a Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 How Are Input Values for a Truth Table Filled In? . . . . . . . 3-23 Practice 3-2.c: Fill in the Input Values for a Truth Table . . . 3-26 Output Values of the Truth Tables . . . . . . . . . . . . . . . . . . . . 3-27 Practice 3-2.d: Describe Logic Functions with Truth Tables 3-29
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What Are the Standard Logic Functions?

Introduction Logic functions are the basis of dening the functionality that exists in an IC. Boolean algebra and truth tables are used to identify the relationship between the input and output values of the logic functions. A logic function is a denition of an output condition based on a set of input conditions. The input and output values are in one of two states, for example:
State 1 High 1 On Vcc State 2 Low 0 Off Vss
Denition
Logic Functions
The basic logic functions are dened by Boolean algebra. Boolean algebra uses the following symbols for the logic functions:
Boolean Symbol
Logic Function Name Inverse
* +
AND OR
continued...
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What Are the Standard Logic Functions? (continued)

Basic Functions The basic logic functions dened by Boolean algebra are as follows:
G
Inverse function: The Inverse function output is always a 0 when the input is a 1 and always a 1 when the input is a 0. A = OUT
Value A=0
Invert Value 0=1 1=0
INVERSE 0=1 1=0
A
G
OUT
A=1
AND function: the output is 1 only when all inputs are 1s.
A * B = OUT
A B OUT
AND 0*0=0 0*1=0 1*1=1
OR function: the output is 0 only when all inputs are 0s.
A + B = OUT
A B OUT
OR 0+0=0 0+1=1 1+1=1
continued...
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What Are the Standard Logic Functions? (continued)

Inverse Functions The Boolean Algebra is created by inverting the basic functions:
G
NAND function: the output is 0 only when all inputs are 1s.
A * B = OUT
A B OUT
AND 0*0=0 0*1=0 1*1=1
Invert AND 0*0=0=1 0*1=0=1 1*1=1=0
NAND 0*0=1 0*1=1 1*1=0
NOR function: the output is 1 only when all inputs are 0s.
A + B = OUT
A B OUT
OR 0+0=1 0+1=0 1+1=0
Invert OR 0 + 0 = 0 =1 0+1=1=0 1+1=1=0
NOR 0+0=1 0+1=0 1+1=0
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Practice 3-2.a: Evaluate Boolean Algebra Equations

Introduction Now that you know how to describe the denitions of the logic functions with Boolean algebra, you will evaluate the following Boolean algebra equations.
Instructions for Practice 3-2.a 1. For the following Boolean algebra equations, provide the name of the logic function and the output value.
Equation 1+1= 1+0= 0*1= 1*1= 1*0= 0+0= 0*0= 1*1= 1+1+1= 1+1+0= 0*0*0= 0*1*0= 1*1*1= 1+1+0= 0*0*1= 1+1+1+0= 0*0*0*1= Function Name Output Value
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What Are Truth Tables?

Introduction An easy way to display the Boolean algebra equations is with a truth table. A truth table is a chart of the output values of a logic function when all possible combinations of 1s and 0s are applied as inputs. To complete a truth table for a logic symbol, you need to know two things.
G G
Denition
Which logic function does the logic symbol represent? How many input nodes does the logic symbol have?
Parts of a Truth Table
The parts of the truth table are as follows. 1. Input/Output Rows: A row for each combination of input values and the output value. The maximum number of rows is equal to the maximum number of input combinations. 2. Input/Output Node Values: The value of the input or output node. The node values are either 0s or 1s. 3. Input Columns: A column for each input node. The number of input columns is equal to the number of input nodes of the logic symbol. 4. Output Column: A column for the output node. There is always one output column for a logic symbol.
3. Input Columns 4. Output Column
B 1. Input/Output Rows 2. Input/Output Node Values 0 0 1 1
A 0 1 0 1
OUT 0 0 0 1
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How Is the Number of Rows for a Truth Table Determined?

Introduction The number of rows that a truth table needs is dened by the maximum number of combinations for the input node values. There is one row in the truth table for each combination of input node values. Determine the number of rows for the truth table as follows:
Procedure
Step 1. 2.
Action Identify the number of input nodes for the logic symbol you are describing. Calculate the maximum number of combinations for the input nodes with the following formula: Maximum Combinations = 2(number of input nodes)
Examples
An example using the formula with a 2-input NAND logic symbol is as follows:
A B
OUT
Maximum Combinations = 22 = 2 * 2 = 4 An example using the formula with a 3-input NOR logic symbol is as follows:
A B C
OUT
Maximum Combinations = 23 = 2 * 2 * 2 = 8
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Practice 3-2.b: Determine the Number of Columns and Rows for a Truth Table
Introduction Now that you know how to determine the number of columns and rows that are needed to create a truth table, determine the number of columns and rows for the following logic symbols.
Instructions for Practice 3-2.b 1. For an Inverter, complete the following. a. Draw the logic symbol.
b. 2.
How many inputs columns does the truth table for this logic symbol have?
For a 4-input AND, complete the following. a. Draw the logic symbol.
b. 3.
How many input columns does the truth table for a 4-input logic symbol have?
For a 4-input OR, complete the following. a. Draw the logic symbol.
b.
Calculate the maximum number of input combinations for a 4-input logic symbol. Show your work.
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Instructions for Practice 3-2.b 4. For a 5-input NOR, complete the following. a. Draw the logic symbol.
b.
Calculate the maximum number of input combinations for a 5-input logic symbol. Show your work.
c.
Calculate the number of rows.
d.
Draw the truth table.
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How Are Input Values for a Truth Table Filled In?

Introduction It is important to list all possible input combinations in the truth table, so that the logic function can be completely described. Once all of the input combinations are lled into the truth table, the output values can be calculated. Determine all possible input combinations as follows:
Procedure
Step 1. 2. 3. 4.
Action Draw the truth table with the correct number of rows and columns. For the right-most input column, ll in each box down this column with alternating 0s and 1s. Start with a 0 in the top box. For the next column to the left, ll in this column with alternating groups of two 0s then two 1s. For each column to the left, continue to alternate between groups of 0s and 1s. In each column, double the number of 0s and 1s in each group.
continued...
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How Are Input Values for a Truth Table Filled In? (continued)
Example Using the above procedure ll in the input values for a 3-input NAND logic symbol.
Step 1. Action Draw the truth table with the correct number of rows and columns. Three inputs = three input columns 23 = 2 * 2 * 2 = 8 rows
OUT
2.
For the right-most input column, ll in each box down this column with alternating 0s and 1s. Start with a 0 in the top box.
A 0 1 0 1 0 1 0 1
OUT
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How Are Input Values for a Truth Table Filled In? (continued)
Example (continued)
Step 3. Action For the next column to the left, ll in this column with alternating groups of two 0s, then two 1s.
B 0 0 1 1 0 0 1 1
A 0 1 0 1 0 1 0 1
OUT
4.
For each column to the left, continue to alternate between groups of 0s and 1s. In each column, double the number of 0s and 1s in each group. For this column, there are four 0s and 1s in each group. If there was another column, there would be eight 0s and 1s in each group.
C 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
A 0 1 0 1 0 1 0 1
OUT
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Practice 3-2.c: Fill in the Input Values for a Truth Table

Introduction Now that you know the procedure to ll in the input values for a truth table, you will draw truth tables and ll in the input values.
Instructions for Practice 3-2.c 1. Complete the following steps to create a truth table for a 3-input logic symbol; the inputs are A, B, C, and the output is OUT. a. b. c. Calculate the number of rows for the truth table. Calculate the number of columns for the truth table. Draw the truth table.
d.
Fill in the input values; do not ll in the output column.
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Output Values of the Truth Tables

Introduction Using the input values of a truth table and the correct Boolean algebra equation, you can determine the output values. For the Inverter function, the output value is always the complement (inverse) of the input value.
G
Inverter Truth Table
The Inverter function truth table is as follows: A = OUT

A 1 0 OUT 0 1
OUT
1=0 0=1
AND Truth Table
For the AND function, if any of the inputs are 0, then the output is 0.
G
The 2-input AND function truth table is as follows:
B 0 1 0 1
OUT 0 0 0 1
A * B = OUT A B
0
OUT
0*0=0 0*1=0 1*1=1
0 1 1
OR Truth Table
For the OR function, if any of the inputs is 1, then the output is 1.

G
The 2-input OR function truth table are is as follows:
B 0 1 0 1
OUT 0 1 1 1
A + B = OUT A B
0
OUT
0+0=0 0+1=1 1+1=1
0 1 1
continued...
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Output Values of the Truth Tables (continued)

NAND Truth Table For the NAND function, if any of the inputs is 0, then the output is 1.
G
The 2-input NAND function truth table is as follows:
B 0 1 0 1
OUT 1 1 1 0
A * B = OUT A B
0
OUT
0*0=1 0*1=1 1*1=0
0 1 1
NOR Truth Table
For the NOR function, if any of the inputs is 1, then the output is 0.
G
The 2-input NOR function truth table is as follows:
B 0 1 0 1
OUT 1 0 0 0
A + B = OUT A B
0
OUT
0+0=1 0+1=0 1+1=0
0 1 1
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Practice 3-2.d: Describe Logic Functions with Truth Tables

Introduction Now that you know how to describe the logic functions with truth tables, you will create truth tables for different logic functions.
Instructions for Practice 3-2.d 1. Complete the following truth table for a room light that is controlled by two switches, one at each door. If either of the switches is on, then the light is on.
1 0
A 0
Switch A
Switch B
Light
a.
Does the above example describe an AND or an OR logic function?
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Instructions for Practice 3-2.d 2. Complete the following steps to create a truth table for a 3-input AND logic function. a. Draw the logic symbol.
b. c. d. e.
Write the Boolean algebra equation for the logic function. Determine the number of input columns. Determine the maximum number of rows. Draw the truth table. Fill in all input combinations and the output values.
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Instructions for Practice 3-2.d 3. Complete the following steps to create a truth table for a 3-input OR logic function. a. Draw the logic symbol.
b. c. d. e.
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Instructions for Practice 3-2.d 4. Complete the following steps to create a truth table for a 4-input AND logic function. a. Draw the logic symbol.
b. c. d. e.
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Instructions for Practice 3-2.d 5. Complete the following steps to create a truth table for a 4-input NAND logic function. a. Draw the logic symbol.
b. c. d. e.
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Instructions for Practice 3-2.d 6. Create a truth table for a 4-input NOR logic function.
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Instructions for Practice 3-2.d 7. Complete all missing input and output values in the following table.
A 0
B 0
C 0
INV A
NOR A, B
NOR A, B, C
NAND A, B
NAND A, B, C
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Chapter Summary
Introduction In this chapter, you learned how to identify the parts of logic-level schematics and to describe the functions of the logic symbols with Boolean algebra and truth tables. This is the rst task of basic layout design. In this chapter, you learned to,
G
Summary
identify the parts of the logic-level schematic. Logic symbol: short-hand representation for basic or complex logic functions. Node: electrical path between logic symbols or the inputs and output of the logic symbols. Nodes are drawn as lines.
describe the function of the logic symbols with Boolean algebra. Inverter: A = OUT AND: A * B = OUT OR: A + B = OUT NAND: A * B = OUT NOR: A + B = OUT create truth tables that chart the output values of a logic function when all possible combinations of 1s and 0s are applied as inputs. A summary of the logic functions is as follows:
B 0 0 1 1 A 0 1 0 1 A 1 0 1 0 A*B 0 0 0 1 A*B 1 1 1 0 A+B 0 1 1 1 A+B 1 0 0 0
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Create Layout Drawing from Transistor-level Schematics
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Chapter Overview
Introduction The layout designer needs more detail than the logic-level schematic provides, so the logic-level schematic must be converted into a transistor-level schematic. In this chapter, you will learn to convert a logic-level schematic to transistor-level schematic. The following topics are covered in this chapter: Lesson Page
Objective
Topics
Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
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Lesson 4-1 Overview

Introduction Before you can convert the logic-level schematic to a transistor schematic, you need to know the parts of the transistor-level schematic. In this lesson, you will learn to identify the parts of a transistor-level schematic. The following are covered in this lesson: Lesson Page
Objective
Topics
What Is a Transistor-level Schematic? . . . . . . . . . . . . . . . . . 4-5 What Is a Transistor? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Nodes of a Transistor-level Schematic . . . . . . . . . . . . . . . . . 4-9 Transistor Representations of the Logic-level Schematics . 4-10 Lab 4-1: Identify the Parts of Transistor-level Schematics . 4-12
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What Is a Transistor-level Schematic?

Introduction The transistor-level schematic has more details than the logic-level schematic; the shorthand symbols of the logic-level schematic are converted to the transistor-level schematic. The transistor-level schematic is a representation of the actual transistors and the connections that create the logic functions of the IC.
G G
Denition
Transistors: representation of the actual layout transistors. Node: an electrical path between transistors or the inputs and output of the transistors. Nodes are drawn as lines.
Example
The following gure is a transistor-level schematic of an inverter with the nodes labeled, and just the power supplies and transistors pulled apart.
Vcc Nodes
Transistors
Vss
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What Is a Transistor?
Introduction There are different types of technologies used to create transistors; Intel uses the Complementary Metal Oxide Semiconductor (CMOS) technology. The transistor is the basic building block of all functions on any IC. CMOS technology uses two types of Metal Oxide Semiconductor Field Effect Transistors (MOSFET)
G G
Denition
pFET (p-type) nFET (n-type)
Each type of MOSFET transistor has the following four elements.

G G G G
gate: input terminal source: terminal closest to Vcc or Vss drain: output terminal bulk: material that the transistor sits in
The complementary part of CMOS means that pairs of p-type and ntype transistors are used to create the functions of the logic symbols. Analogy The source, gate, and drain of a transistor are similar to the circuits in your home.
Transistor Source Gate Drain Your Home Power Company Light switch Lamp
continued...
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What Is a Transistor? (continued)

Example The p-type transistor and the n-type transistor are drawn as follows:
p-type Transistor Source Gate Bubble Bulk Gate Hole Flow Drain Source Gate Electron Flow Bulk n-type Transistor Drain
P-Type vs. N-Type Transistors
The p-type and n-type transistors differ as follows:

p-type Majority Current Carrier Gate Bubble Logical On Bulk hole yes 0 n-well n-type electron no 1 epitaxial
Orientation
The orientation of the transistor does not affect the performance or function of the transistor. All of the following n-type transistors are equivalent.
Source and Drain Regions
The source and drain regions are interchangeable and from this point on are referred to as source/drain (S/D). continued...
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What Is a Transistor? (continued)

Logical On A logical on is when a transistor is logically on, the current ows through the transistor. A hole is a mobile vacancy within a semi-conductor material created by the lack of an electron. A hole ows in the opposite direction as the current. An electron is the basic atomic particle orbiting an atom. An electron ows in the same direction as the current. Current is the movement of electrons through a circuit.
Hole
Electron
Current
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Nodes of a Transistor-level Schematic

Introduction It is important for you to be able to identify all of the nodes in a transistor-level schematic. The input and output nodes, the connections between two transistors, Vcc and Vss, are all nodes on a transistor-level schematic. A transistor-level schematic of an INVERTER has the following four nodes: 1. between the upper S/D region of the p-type transistor and Vcc 2. from the input node to the gate of both transistors 3. from the lower S/D region of the p-type transistor to the upper S/D region of the n-type transistor to the output node 4. between the lower S/D region of the n-type transistor and Vss
Logic-level Schematic A B 2 A B 3 Transistor-level Schematic 1
Nodes of a Transistorlevel Schematic
Internal Nodes
There will be times when a node is not an input, output, Vcc, or Vss node as follows.
Internal Node
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Transistor Representations of the Logic-level Schematics

Introduction The following are the logic symbol, truth table, and transistor-level representations of the logic symbols used in this class. The Inverter logic, transistor-level representation, and truth table are as follows:
A B
Inverter Representations
Logic-level A A 0 1 OUT 1 0 Transistor-level OUT
Truth Table
NAND Representations
The NAND logic, transistor-level representation, and truth table are as follows:
A B Logic-level A 0 0 1 1 B 0 1 0 1 OUT 1 1 1 0 A
C B OUT
Truth Table
Transistor-level
continued...
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Transistor Representations of the Logic-level Schematics (continued)

NOR Representations The NOR logic, transistor representation, and truth table are as follows:
A B Logic-level
C A
A 0 0 1 1
B 0 1 0 1 Truth Table
Out 1 0 0 0 Transistor-level B OUT
Logic Symbol Dots
A dot drawn on the logic symbol indicates how the series transistors are drawn. For this class, the convention is that the dot indicates which series transistor is drawn closest to the output node. The dot affects only the drawing of the series transistors. The placement of the dot is determined by the design engineer to address any timing issues. Logic symbols with dots drawn are as follows:
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Lab 4-1: Identify the Parts of Transistor-level Schematics

Introduction Now that you know the parts of the transistor-level schematic, you will identify the transistors and nodes in the following exercises.
Instructions for Lab 4-1 1. Given the following logic and transistor-level schematic, complete the exercises.
OUT
OUT
a. b. c. d. e.
How many nodes does the logic-level schematic have? Color each node of the transistor-level schematic with a different color. How many nodes does the transistor-level schematic have? How many p-type transistors does the transistor-level schematic have? How many n-type transistors does the transistor-level schematic have?
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B A A B OUT OUT
a. b. c. d. e. f.
What type of logic symbol is this? How many nodes does the logic-level schematic have? Color each node of the transistor-level schematic with a different color. How many nodes does the transistor-level schematic have? How many p-type transistors does the transistor-level schematic have? How many n-type transistors does the transistor-level schematic have?
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A B
OUT
OUT
a. b. c. d. e.
What type of logic symbol is this? Color each node of the transistor-level schematic with a different color. How many nodes does the transistor-level schematic have? How many p-type transistors does the transistor-level schematic have? How many n-type transistors does the transistor-level schematic have?
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OUT A B C 30 OUT 15 B
a. b. c. d. e.
What type of logic symbol is this? Color each node of the transistor-level schematic with a different color. How many nodes does the transistor-level schematic have? How many p-type transistors does the transistor-level schematic have? How many n-type transistors does the transistor-level schematic have?
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Lesson 4-2 Overview

Introduction Knowledge of how transistors work allows a better understanding of how the logic functions execute. In this lesson, you will learn to verify the input and output values of the truth table against how the transistors turn on and off to allow current to ow. The following are covered in this lesson: Topic Page
Objective
Topics
Values that Turn a Transistor On or Off . . . . . . . . . . . . . . . . 4-18 How Are Truth Table Values Veried? . . . . . . . . . . . . . . . . 4-19 Practice 4-2: Verify the Transistor-level Function of the Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
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Values that Turn a Transistor On or Off

Introduction You have seen the logic, the transistor representation, and the truth tables of the basic logic symbols. Now it is time to trace the nodes through the transistors from the input to the output. This will validate that the truth tables accurately represent the logic. Remember that when a transistor is logically on, the current is owing through the transistor. An analogy is a light switch in your home; when the light switch is turned on the current ows from the power company to the lamp.
P-Type Logical value to turn transistor on Logical value to turn transistor off Memory aid 0 1 Bubble N-Type 1 0 No Bubble
Turning a Transistor On or Off
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How Are Truth Table Values Veried?

Introduction By tracing the input values and their affect on the transistors, you can see how the output value is created. Verify the inputs and outputs against the truth table with the following steps:
Step 1. 2. 3. Action Apply the rst row of the truth table to the input nodes. Determine which transistor gates are on and off. Write on or off for each transistor. Trace a path through the transistors from Vss to the output node and from Vcc to the output node. Determine which path is complete.
G G
Procedure
If a path is found from Vss, then the output value is 0. If a path is found from Vcc, then the output value is 1.
4. 5.
Note that the value at the output node matches the truth table. Repeat for each row of the truth table.
Reminders
Remember the values that turn the p-type and n-type transistors on and off.
Remember that Vcc and Vss have the following logical values:
G G
Vcc = 1 Vss = 0 continued...
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How Are Truth Table Values Veried? (continued)

Inverter Example Using the transistor-level schematic and the truth table, complete the steps of the above procedure to verify the inputs and output values.
A A B 0 1
OUT 1 0
Use the procedure for the rst line of the truth table, as follows:
Step 1. 2. Action Apply the rst row of the truth table to the input nodes. Determine which transistor gates are on and off. Write on or off for each transistor. a. the p-type transistor is on b. the n-type transistor is off
on A=0 off B=0
3.
Trace a path through the transistors from Vss to the output node and from Vcc to the output node. Determine which path is complete.
G G
If a path is found from Vss, then the output value is 0. If a path is found from Vcc, then the output value is 1. A path is found from Vcc to the output node, so a logical 1 is at the output.
4.
Note that the value at the output node matches the truth table. The input of a logical 0 is inverted to a logical 1.
continued...
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How Are Truth Table Values Veried? (continued)

Inverter Example (continued) Use the same transistor-level schematic and truth table.
A A B 0 1
OUT 1 0
Repeat the procedure for the next line of the truth table, as follows:
Step 1. 2. Action Repeat for the next row of the truth table. Determine which transistor gates are on and off. Write on or off for each transistor. a. the p-type transistor is off b. the n-type transistor is on
off A=1 on B=0
3.
Trace a path through the transistors from Vss to the output node and from Vcc to the output node. Determine which path is complete.
G G
If a path is found from Vss, then the output value is 0. if a path is found from Vcc, then the output value is 1. A path is found from Vss to the output node, so a logical 0 is at the output.
4.
Note that the value at the output node matches the truth table. The input of a logical 1 is inverted to a logical 0.
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Practice 4-2: Verify the Transistor-level Function of the Logic Symbols

Introduction Now that you know what value turns on a p-type and an n-type transistor and how to verify the values of a truth table, you will verify the following transistor-level schematics and truth tables.
Instructions for Practice 4-2 1. Given the following 2-input NAND transistor-level schematic and truth table, use the outlined procedure to verify the truth table values, as directed.
B B A OUT 0 0 1 1 A 0 1 0 1 OUT 1 1 1 0
Step 1. 2. 3.
Action Apply the rst row of the truth table to the input nodes. Determine which transistor gates are on and off. Write ON or OFF for each transistor. Trace a path through the transistors from Vss to the output node and from Vcc to the output node. Determine which path is complete.
G G
If a path is found from Vss, then the output value is 0 if a path is found from Vcc, then the output value is 1
4. 5.
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Instructions for Practice 4-2 2. a. Apply the rst row of the truth table to the following transistor-level schematic.
B A OUT
b.
Apply the second row of the truth table to the following transistor-level schematic.
B A OUT
c.
Apply the third row of the truth table to the following transistor-level schematic.
B A OUT
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Instructions for Practice 4-2 3. d. Apply the fourth row of the truth table to the following transistor-level schematic.
B A OUT
4.
Given the following 2-input NOR transistor-level schematic and truth table, use the outlined procedure to verify the truth table values.
B A 0 0 B OUT 1 1 0 1 0 1 1 0 0 0 A OUT
Step 1. 2. 3.
Action Apply the rst row of the truth table to the input nodes. Determine which transistor gates are on and off. Write ON or OFF for each transistor. Trace a path through the transistors from Vss to the output node and from Vcc to the output node. Determine which path is complete.
G G
If a path is found from Vss, then the output value is 0 if a path is found from Vcc, then the output value is 1
4. 5.
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Instructions for Practice 4-2 5. a. Apply the rst row of the truth table to the following transistor-level schematic.
OUT
b.
Apply the second row of the truth table to the following transistor-level schematic.
OUT
c.
Apply the third row of the truth table to the following transistor-level schematic.
OUT
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Instructions for Practice 4-2 6. d. Apply the fourth row of the truth table to the following transistor-level schematic.
OUT
7.
For the 3-input NAND logic symbol, complete the following. a. b. c. Draw the transistor-level schematic. Draw and ll in the truth table. Using the same procedure as in the previous exercises, verify the truth table values.
8.
For the 3-input NOR logic symbol, complete the following. a. b. c. Draw the transistor-level schematic. Draw and ll in the truth table. Using the same procedure as in the previous exercises, verify the truth table values.
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Lesson 4-3 Overview

Introduction Up to this point, the transistor-level schematics have been given to you. However, you will need to know how to draw the transistorlevel schematics. The level of detail of the transistor-level schematic is needed to create the layout drawings. In this lesson you will learn to convert a logic-level schematic to a transistor-level schematic. The following are covered in this lesson: Topic Page
Objective
Topics
Logic Functions Dened with Transistors . . . . . . . . . . . . . . 4-29 How Is a Logic-level Schematic Converted to a Transistorlevel Schematic? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Practice 4-3: Convert a Logic-level Schematic to a Transistorlevel Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 What is Complex Logic? . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 Order of the Series Transistors . . . . . . . . . . . . . . . . . . . . . . . 4-34 How Is a Complex Logic-level Schematic Converted to NType Transistors? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 Lab 4-3.a: Convert Complex Logic-level Schematics to NType Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 How Is a Complex Logic-level Schematic Converted to PType Transistors? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 Lab 4-3.b: Convert Complex Logic-level Schematics to PType Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43 Lab 4-3.c: Convert Complex Logic-level Schematics to Transistor-level Schematics . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
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Logic Functions Dened with Transistors

Introduction Before converting a logic-level schematic to a transistor-level schematic, you need to understand how the transistors dene the logic of the function. The logical function of a logic symbol is always dened by the ntype transistors.
G
Logic Functions
NAND function based on the AND function n-type transistors are in series p-type transistors are parallel
parallel transistors A A B OUT series transistors
B OUT
NOR function based on the OR function n-type transistors are parallel p-type transistors are in series
series transistors A B OUT
OUT
parallel transistors
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How Is a Logic-level Schematic Converted to a Transistor-level Schematic?

Introduction The transistor-level schematic equivalent of a logic-level schematic is drawn with a straightforward procedure. The procedure of converting a logic-level schematic to a transistorlevel schematic is as follows:
Step 1. 2. Action Determine the logic function of the logic symbol: NAND or NOR. Calculate the number of transistors, as follows: # of transistors = 2 * (# of input nodes) For example, for a 2-input NAND logic symbol: # of transistors = 2 * (2) = 4 Half of the transistors are p-type transistors and half are n-type transistors. 3. 4. Draw the output node as a horizontal line. Create the n-type transistors according to the logic function of the logic symbol and label all transistor nodes according to the logic-level schematic. Add the p-type transistors as the complement to the n-type transistors and label all nodes according to the logic-level schematic. Remember:
Procedure
5.
If n-type transistors are... in series parallel
then p-type transistors are... parallel in series
6.
Connect all common nodes.
continued...
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How Is a Logic-level Schematic Converted to a Transistor-level Schematic? (continued)

Example Use the NAND logic symbol and the procedure outlined, as follows.
Step 1. Action Determine the logic function of the logic symbol: NAND or NOR. A B OUT
NAND; the n-type transistors are in series. 2. Draw the output node as a horizontal line. OUT 3. Create the n-type transistors according to the logic function of the logic symbol and label all transistor nodes according to the logic-level schematic. OUT A B
4.
Add the p-type transistors as the complement to the n-type transistors and label all nodes according to the logic-level schematic. OUT A B
5.
Connect all common nodes.
B OUT
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Practice 4-3: Convert a Logic-level Schematic to a Transistor-level Schematic

Introduction Now that you know how to convert logic symbols to transistor-level schematics, you will convert the following logic symbols.
Instructions for Practice 4-3 1. Using the described procedure, convert the following logic-level schematics to a transistor-level schematic. a.
A B OUT
b.
A B Out
c.
A B N1 OUT
d.
A N1 B OUT
e.
A B C D E F
N1 OUT N2
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What is Complex Logic?

Introduction Understanding the basic logic functions is not enough; you need to be able to a convert complex logic function into transistor-level schematic. Complex logic is the combination of non-inverted logic functions and an inverted logic function that produce a new function. The new function is drawn with fewer transistors and has increased performance. The non-inverted logic functions cannot be drawn directly with the CMOS process. Example A logic-level schematic of a complex logic symbol is as follows:
A B C D Inverted Function OUT
Denition
Non-Inverted Functions
Internal Nodes
There are internal nodes in complex logic where the logic symbols touch, as follows:
A B C D Internal Node OUT Internal Node
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Order of the Series Transistors

Introduction For the transistors drawn in series, the ordering is important for timing purposes and is communicated by the design engineer on the logic-level schematic. A dot drawn on the logic symbol indicates the transistor that is drawn closest to the output node. The dot affects the drawing of the series transistors and the series boxes of complex logic.
G G
Logic Symbol Dots
A dot on the parent indicated the box closest to the output node. A dot on the logic symbol in a box indicates the transistor of the logic symbol that must be closest to the output node.
A logic-level schematic with dots is drawn as follows:

A B OUT C D
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How Is a Complex Logic-level Schematic Converted to N-Type Transistors?

Introduction Converting a complex logic-level schematic is accomplished with the following procedure. Since the n-type transistors determine the logic function it is easier to draw them rst. In the next section, you will learn to add the p-type transistors. The procedure of converting a complex logic-level schematic to the n-type transistors is as follows:
Step 1. 2. 3. Action Identify the parts of the logic-level schematic; input, output, internal nodes, logic symbols. Identify the inverted logic function. Draw a box around the logic symbol the output node is connected to and call this parent. Identify the inputs to parent. Draw a box around each of the logic symbols and input nodes going into parent. Label each of these boxes; for example, Box1, Box2. Begin the transistor-level schematic. Draw a horizontal line to represent the output node and label it. Determine the logic function (NAND or NOR) of the n-type transistors of parent. Tip: Remember that the n-type transistors determine the logic function of the logic symbol (in series or parallel). 6. 7. Draw and connect the boxes, in series or parallel, to the output node and to Vss as dened by the function of parent. Draw the n-type transistors into the corresponding boxes for each logic symbol and label all the input nodes.
Procedure
4. 5.
continued...
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How Is a Complex Logic-level Schematic Converted to N-Type Transistors? (continued)

Example Using the following complex logic-level schematic:
A B C D
OUT
Complete the conversion procedure, as follows:

Step 1. 2. Action Identify the parts of the logic-level schematic; input, output, internal nodes, logic symbols. Identify the inverted logic function. Draw a box around the logic symbol the output node is connected to and call this parent. A B C D 3. Identify the inputs to parent. Draw a box around each of the logic symbols and input nodes going into parent. Label each of these boxes; for example, Box1, Box2. Box 1 A B C D Box 2 4. Begin the transistor-level schematic. Draw a horizontal line to represent the output node and label it. OUT 5. Determine the logic function (NAND or NOR) of the n-type transistors of parent. In this example, logic function of parent is the NAND function, so the n-type transistor boxes are drawn in series. parent OUT parent OUT
continued...
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How Is a Complex Logic-level Schematic Converted to NType Transistors? (continued)

Example (continued) The rest of the steps are as follows:
Step 6. Action Draw and connect the boxes, in series or parallel, to the output node and to Vss as dened by the function of parent. Since the n-type transistors of the NAND logic are in series, draw the boxes in series. OUT
Box 1
Box 2
7.
Draw the n-type transistors into the corresponding boxes for each logic symbol and label all the input nodes. Box 1: OR function. The transistors are parallel. Box 2: AND function. The transistors are in series. OUT
Box 1
C D Box 2
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Lab 4-3.a: Convert Complex Logic-level Schematics to N-Type Transistors

Introduction Now that you know how to convert a complex logic-level schematic to the n-type transistors and how to determine which transistors must be closest to the output node, you will draw the n-type transistors in the correct order for complex logic-level schematics.
Instructions for Lab 4-3.a Use a full page of paper for each drawing. Put the n-type transistors at the bottom of the page and leave room at the top to later add the p-type transistors. 1. Given the following logic-level schematic, complete the following.
A B OUT C D
a. b.
How many n-type transistors are needed? Draw the n-type transistors for the logic-level schematic; pay attention to the dot notation.
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Instructions for Lab 4-3.a 2. Given the following logic-level schematic, complete the following.
A B C D E F OUT
a. b. 3.
Given the following logic-level schematic, complete the following.

A B C OUT
a. b.
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How Is a Complex Logic-level Schematic Converted to P-Type Transistors?

Introduction You know how to draw the n-type transistors of the complex logic. Now you will add the p-type transistors. The procedure of converting a complex logic-level schematic to the p-type transistors is as follows:
Step 1. Action Draw and connect the boxes to hold the p-type transistors in a way that is complementary to the boxes holding the n-type transistors. Pay attention to which logic symbol is marked to be drawn nearest to the output node. 2. Draw the p-type transistors in the new boxes, connect the transistors to the output and Vcc nodes, and label the input nodes. Tip: Remember that the n-type and p-type transistors are complementary.
Procedure
If N-Type transistors are... in series parallel
then P-Type transistors are... parallel in series
3.
Connect the common nodes: A to A, etc.
continued...
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How Is a Complex Logic-level Schematic Converted to P-Type Transistors? (continued)

Example Use the same complex logic-level schematic used to draw the n-type transistors.
Box 1 A B C D Box 2 parent OUT
Add the p-type transistors using the procedure, as follows:

Step 1. Action Draw and connect the boxes to hold the p-type transistors in a way that is complementary to the boxes holding the n-type transistors. Pay attention to which logic symbol is marked to be drawn nearest to the output node. In this example, the n-type transistor boxes are in series, so the p-type transistor boxes are parallel. Box 1 Box 2
OUT
B Box 1
C D Box 2
continued...
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How Is a Complex Logic-level Schematic Converted to P-Type Transistors? (continued)

Example (continued) The rest of the steps are as follows:
Step 2. Action Draw the p-type transistors in the new boxes, connect the transistors to the output and Vcc nodes, and label the input nodes. Box 1: n-type transistors are parallel, so the p-type transistors are in series. Box 2: n-type transistors are in series, so the p-type transistors are parallel.
Box 2
Box 1 B A
OUT 3. Connect the common nodes: A to A, etc.
Box 2 C
Box 1 B A
OUT A
Box 1
D Box 2
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Lab 4-3.b: Convert Complex Logic-level Schematics to P-Type Transistors

Introduction Now that you know how to convert a complex logic-level schematic to the p-type transistors, you will add the p-type transistors in the correct order for the complex logic-level schematics you drew in the last practice.
Instructions for Lab 4-3.b Use the drawings you made in the previous lab and add the p-type transistors for the following exercises. 1. For the following logic-level schematic, add the p-type transistors to the transistor-level schematics you drew in the last practice.
A B OUT C D
2.
For the following logic-level schematic, add the p-type transistors to the transistor-level schematics you drew in the last practice.
A B C D E F OUT
3.
For the following logic-level schematic, add the p-type transistors to the transistor-level schematics you drew in the last practice.
A B C OUT
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Lab 4-3.c: Convert Complex Logic-level Schematics to Transistor-level Schematics

Introduction Now that you know how to convert a complex logic-level schematic to the n-type and p-type transistors, you will draw both the n-type and p-type transistors for complex logic-level schematics.
Instructions for Lab 4-3.c 1. For the following logic-level schematic, draw the transistor-level schematic.
A B C D OUT
2.
For the following logic-level schematic, draw the transistor-level schematic.

A B C D E F OUT
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Chapter Summary
Introduction In this chapter, you learned how to identify the parts of a transistorlevel schematic, how to verify the transistor-level function of the logic symbols, and how to convert logic-level schematics to transistor-level schematics. In this chapter, you learned to
G
Summary
identify the parts of the transistor-level schematic. Transistors: transistor-level schematic transistors represent the actual layout transistors. pFET (p-type) nFET (n-type) The p-type and n-type transistors differ as follows:
P-type Majority Current Carrier Gate Bubble Logical On Bulk hole yes 0 n-well N-type electron no 1 epitaxial
Node: an electrical path between transistors or the inputs and output of the transistors. Nodes are drawn as lines. The input and output nodes, the connections between two transistors, Vcc and Vss, are all nodes on a transistor-level schematic.
G
verify the transistor-level function of the logic symbols How to turn a transistor on:
continued...
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Chapter Summary (continued)

Summary (continued)
G
convert logic-level schematics to transistor-level schematics The logical function of a logic symbol is always dened by the n-type transistors. NAND symbols based on the AND function n-type transistors are in series p-type transistors are parallel
A B OUT A
B OUT
NOR symbol based on the OR function n-type transistors are parallel p-type transistors are in series
A B OUT A OUT
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Interpret Logic-level Schematic
Create Layout Drawing from a Transistor-level Schematic
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Chapter Overview
Introduction To create the masks for IC fabrication, the actual geometry size and spacing is needed. The transistor-level schematic must therefore be converted into a layout drawing. To convert a transistor-level schematic to a layout drawing. The following topics are covered in this chapter: Lesson Page
Objective Topics
Lesson 5-1: How to Identify a Transistor on the IC Cross Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Lesson 5-2: How to Identify Process Design Rules on the Transistor Cross Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Lesson 5-4: How to Get Better Layout Density with Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 Lesson 5-5: How to Estimate Area . . . . . . . . . . . . . . . . . . . . 5-39 Lesson 5-6: How to Calculate Resistance. . . . . . . . . . . . . . . 5-49 Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59 Lesson 5-8: How to Draw Layout with a Standard Cell Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-67 Lesson 5-9: How to Draw Layout to Meet Layout Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-73 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80
5-2
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Lesson 5-1 Overview

Introduction The objective of creating layout drawings is to create the die for the IC, so it is important to understand how your work affects the die. In this lesson, you will learn how your layout drawing affects the creation of the die for the IC. The following topics are covered in this lesson: Topic Page
Objective
Topics
What Is a Cross Section? . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Layers of the Transistor Cross Section . . . . . . . . . . . . . . . . 5-6 Layers of the Die Cross Section . . . . . . . . . . . . . . . . . . . . . . 5-7 What Is a Diode? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 How Is a Transistor Turned On or Off? . . . . . . . . . . . . . . . . 5-10
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What Is a Cross Section?

Introduction In order to understand how the p-type and n-type transistors function, it is necessary to look at the transistor cross section. A cross section is formed when you slice open an object and look at the cut edge. Think of a cake as the IC. When you look at the top of the cake you see only the top layer, the frosting. To see what makes up the cake, you have to slice it open. After slicing the cake open, you see that it is made up of many layers of different types of cake, lling, and frosting. The same is true when you slice an IC.
Cake Cake Cross Section
Denition
Analogy
The die is made up of many layers of different materials that are used to achieve the various functions an IC is capable of. The following is the cross section of an n-type and a p-type transistor.
n-type transistor p-type transistor
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Layers of the Transistor Cross Section

Introduction The p-type and n-type transistors are made of different diffusion material, so their cross section drawings are different. The layers of the p-type transistor are as follows:
P-Type Transistor
Gate Oxide S/D (Boron)
Polysilicon S/D (Boron) Nwell Tap (Arsenic)
Nwell Epitaxial Wafer
N-Type Transistor
The layers of the n-type transistor are as follows:
Gate Oxide S/D (Arsenic)
Polysilicon S/D (Arsenic) Substrate Tap (Boron)
Epitaxial Wafer
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Layers of the Die Cross Section

Introduction A complete IC is created by accurately fabricating many layers of materials. The process begins with a pure silicon ingot cylinder 8 inches in diameter and about 2-3 feet long. The ingot is sliced into thin wafers creating circular disks (like a CD). The wafers, also known as substrate, are the foundation of ICs. The layers on different die may vary with the fabrication process used to create the die. The following is a typical layering of the materials on a die. 1. Epitaxial: higher resistance than the substrate, or wafer 2. Nwell: provides a collection of electrons for the p-type transistors to sit in 3. Source/Drain: arsenic for n-diffusion S/D, and boron for p-diffusion S/D. 4. Gate Oxide (gox): thin layer below gates 5. Polysilicon: for the gates and minimal routing 6. Field Oxide (fox): thick layer to insulate different layers 7. Contact: hole in the eld oxide so the Metal1 can make a connection to polysilicon or diffusion 8. Metal1: rst layer of aluminum for interconnect 9. Field Oxide: same as above 10. Via 1: hole in the eld oxide so the Metal2 can make a connection to Metal1 11. Metal2: second layer of aluminum for interconnect 12. Field Oxide: same as above 13. Repeat 10-12 for each metal layer in the process 14. Passivation: oxide to insulate the die
Fabrication Process
Layers
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What Is a Diode?
Introduction Inherent in the fabrication of the CMOS transistor is the creation of a parasitic diode. A diode is a semiconductor device that allows current to ow in one direction only. A diode is created when the p-type and n-type diffusions physically touch. Diodes can be
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Denition
intentional: purposely added to the circuit to function as an Electro-static Discharge (ESD) device parasitic: occurring naturally when p-type and n-type materials touch
The normal operating condition of a diode in CMOS is reverse biased, which prevents electrical current from owing between opposite polarity diffusions when they are abutting. Parts of a Diode The terminals of a diode are the anode and the cathode.
G G
The anode is the p-type diffusion. The cathode is the n-type diffusion. ++ ++ ++
Anode
------Cathode
continued...
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What is a Diode? (continued)

Example In the reverse biased diode, current does not ow. However, in the forward biased diode, the current ows unrestricted.
Reverse Biased Diodes Forward Biased Diode
Parasitic Diodes in an Inverter
There are ve parasitic diodes in an inverter, as shown in the following diagram.
Nwell
Epitaxial
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How Is a Transistor Turned On or Off?

Introduction Applying a logical 1 to an n-type transistor, or a logical 0 to a p-type transistor, turns the transistor on and allows current to ow from the source to the drain. In a Field Effect Transistor (FET), the current never ows between the gate and the epitaxial layer. However, there is a predictable eld effect on the region immediately below the gate, between the source drain, so that current can be blocked or ow between the source and drain. Apply a logical 1 to the n-type and p-type transistors as follows:
Applying a Logical 1 N-Type A positive electrical charge is applied to the gate. The positive charge at the gate repels the positively charged ions in the epitaxial below the gate, creating an inversion layer. The current can now ow freely between the source and drain. 1 P-Type A positive electrical charge is applied to the gate. The positive charge at the gate attracts the negatively charged ions in the n-well below the gate, blocking the current ow. The current cannot ow between the source and drain.
Process
Nwell Epitaxial
continued...
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How Is a Transistor Turned On or Off? (continued)

Process (continued) Apply a logical 0 to the n-type and p-type transistors as follows:
Applying a Logical 0 N-Type A negative electrical charge is applied to the gate. The negative charge at the gate attracts the positively charged ions in the epitaxial, blocking the current ow. The current cannot ow between the source and drain. 0 P-Type A negative electrical charge is applied to the gate. The negative charge of the gate repels the negatively charged ions of the n-well below the gate, creating an inversion layer. The current can now ow freely between the source and drain.
Nwell
Epitaxial
Memory Aid
The positive and negative ions attract and repel as follows:

Ion Charge + + Ion Charge + Action Repel Attract Repel
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Lesson 5-2 Overview

Introduction To ensure that transistors on the die are fabricated correctly, a set of process-specic design rules must be followed. Your layout drawings directly affect the fabrication of the die. In this lesson, you will learn to identify some of the design rules on the IC cross section. The following are covered in this lesson: Topic Page
Objective
Topics
What Is a Design Rule? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Basic Process Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 How Are Process Design Rules Identied on the Transistor Cross Section? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
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What Is a Design Rule?

Introduction To avoid unwanted results in the fabrication of an IC, certain process-specic design rules must be followed when drawing layout. The process design rules are the minimum allowable drawn dimensions. These rules affect the x and y dimensions of layout not the depth/vertical dimension. The minimum dimensions are dened by
G
Denition
the smallest geometry and spacing that can accurately be fabricated the smallest geometry and spacing that maintains electrical isolation and/or functionality the minimum overlap of two materials
How to Avoid Design Violations
To avoid these process design violations, rules must be followed when drawing the layout. What you draw directly affects what is created on silicon.
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Basic Process Design Rules

1. N+ and P+ Diffusion A. Minimum Width S/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 B. Minimum Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 2. Polysilicon A. Minimum Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 B. Minimum Spacing of Stacked Gates . . . . . . . . . . . . . . . . 3.0 C. Field Polysilicon to Diffusion Separation . . . . . . . . . . . . 0.0 D. Polysilicon End Cap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 3. Metal Contacts A. Minimum Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 x 2.0 B. Minimum Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 C. Minimum Diffusion/Polysilicon Overlap . . . . . . . . . . . . 2.0 D. Minimum Spacing to Active Gate . . . . . . . . . . . . . . . . . . 2.0 4. Metal A. Minimum Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 B. Minimum Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 C. Minimum Metal Overlap of Contact . . . . . . . . . . . . . . . . 0.0 5. Nwell A. Nwell Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 B. Nwell Overlap of Diffusion . . . . . . . . . . . . . . . . . . . . . . 3.0 C. Nwell Spacing to Diffusion . . . . . . . . . . . . . . . . . . . . . . . 4.0 D. Minimum Nwell Width . . . . . . . . . . . . . . . . . . . . . . . . . 10.0
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How Are Process Design Rules Identied on the Transistor Cross Section?
Introduction Some of the basic process design rules can be identied in a cross section of the layout. In the following example, the following rules can be identied: 1. minimum metal overlap of contact 2. minimum polysilicon width 3. contact width 4. minimum S/D width 5. minimum diffusion spacing 6. minimum Nwell width
1. metal overlap of contact 2. min polysilicon width 4. min S/D width 5. min diffusion spacing
Example
3. contact width
6. min nwell width Nwell Epitaxial
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Lesson 5-3 Overview

Introduction Critical to a good design, is creating a good plan before drawing any layout. In this lesson, you will learn how to create a stick diagram for transistor placement and connections. The following topics are covered in this lesson: Topic Page
Objective
Topics
What Is a Stick Diagram? . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 Legend for a Stick Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Series and Parallel Transistors in a Stick Diagram . . . . . . . 5-23 How Is a Stick Diagram Created? . . . . . . . . . . . . . . . . . . . . 5-24 Lab 5-3.a: Create a Stick Diagram . . . . . . . . . . . . . . . . . . . . 5-26 How Is the Width of a Layout Drawing Estimated from a Stick Diagram? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 Lab 5-3.b: Estimate the Width of a Layout Drawing from a Stick Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
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What Is a Stick Diagram?

Introduction To help create an optimal layout, rst create a stick diagram. This diagram is a shorthand representation of what your layout will look like. This diagram helps you plan where to place transistors to achieve the maximum density and best performance. A stick diagram is a technique to generate a free-form, topological plan of a circuit for layout without regard to the actual geometry sizing or process design rules. Graphical symbols representing the transistors are drawn relative to each other and are connected together by other symbols representing the interconnect mask layers.
Denition
Parts of a Stick Diagram
Note: In layout, transistors are formed by crossing polysilicon and diffusion.
The stick diagram equivalents of a transistor-level schematic are as follows:

Transistor-level Schematic Stick Diagram
S/D (p-type)
Gate (polysilicon)
S/D (n-type)
Gate (polysilicon)
Practice
How many transistors are in the following stick diagram?
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Legend for a Stick Diagram

Introduction Stick diagrams are best drawn in color but can be drawn in black and white using different patterns for the lines. The legend for the different symbols is as follows:
Layer P Diffusion N Diffusion Polysilicon Metal Metal Contacts N-Well Symbol Color
Legend
Example
The INVERTER schematics and stick diagram are as follows:
OUT
Vcc A OUT
Vss
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Series and Parallel Transistors in a Stick Diagram

Introduction When converting transistor-level schematics to stick diagrams, transistors will often be drawn in series or parallel. Series transistors are drawn with one path from Vcc/Vss to the output node, as follows:
Vcc A N1 OUT
Series Transistors
OUT
Parallel Transistors
Parallel transistors are drawn with multiple paths from Vcc/Vss to the output node, as follows:
OUT Vss OUT Vss
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How Is a Stick Diagram Created?

Introduction There are some well-dened methods for creating stick drawings. By following the steps outlined below, you can achieve a good layout for simple schematics. Create a stick drawing as follows:
Step 1. Action Determine how many transistors are needed, from the logic-level schematic. # of transistors = 2 (# of inputs) 2. 3. Draw the transistor-level schematic of the logic-level schematic. Convert the transistor-level schematic. a. Draw horizontal lines for the p-type and n-type diffusion. For this class, plan to have the p-type devices above the n-type devices. b. c. d. Draw vertical polysilicon lines to create the correct number of gates. Label the gates. Trace the transistor-level schematic and label the stick diagram to match. Make sure that all S/D nodes of each transistor match between the transistor-level schematic and the stick diagram.
Procedure
Guidelines
When creating parallel transistors in the stick diagram, minimize the number of connections to the output node. Both S/D of a transistor cannot be connected to the same node. All common nodes must be connected. When polysilicon crosses diffusion a transistor is always created. Do not connect to S/D regions with polysilicon. All metal connections to polysilicon and diffusions must have at least one contact.
G G G G G
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How Is a Stick Diagram Created? (continued)

Example Use the procedure described and create a stick diagram for the Inverter.
Step 1. Action Determine how many transistors are needed, from the logic-level schematic. # of transistors = 2 (1) = 2 2. Draw the transistor-level schematic of the logic-level schematic.
OUT
3.
Convert the transistor-level schematic. a. Draw horizontal lines for the p-type and n-type diffusion. For this class, plan to have the p-type devices above the n-type devices.
b.
Draw vertical polysilicon lines to create the correct number of gates. Label the gates. A OUT
c.
Trace the transistor-level schematic and label the stick diagram to match. A Vcc OUT
Vss
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Lab 5-3.a: Create a Stick Diagram

Introduction Now that you know how to draw stick diagrams for transistor-level schematics, you will draw a stick diagram for the following exercises.
Instructions for Lab 5-3.a 1. Using the procedure described, create a stick diagram for a 2-input NOR function.
Step 1. Action Determine how many transistors are needed, from the logic-level schematic. # of transistors = 2 (# of inputs) 2. 3. Draw the transistor-level schematic of the logic-level schematic. Convert the transistor-level schematic. a. Draw horizontal lines for the the p-type and n-type diffusion. For this class, plan to have the p-type devices above the n-type devices. b. c. d. Draw vertical polysilicon lines to create the correct number of gates. Label the gates. Trace the transistor-level schematic and label the stick diagram to match. Make sure that all S/D nodes of each transistor match between the transistor-level schematic and the stick diagram.
2. 3. 4.
Using the procedure described, create a stick diagram for a 2-input NAND function. Using the procedure described, create a stick diagram for a 3-input NOR function. Using the procedure described, create a stick diagram for a 3-input NAND function.
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Instructions for Lab 5-3.a 5. Using the procedure described and the following logic-level schematic, draw the stick diagram.
A B C OUT
6.
Using the procedure described and the following logic-level schematic, draw the stick diagram.
A B OUT C D
7.
IN OUT
8.
A B OUT
9.
OUTB OUTA A B C
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Instructions for Lab 5-3.a 10. Using the procedure described and the following logic-level schematic, draw the stick diagram.
A B OUTA
OUTB
11.
A B C
OUT
12.
A B C OUT
13.
A OUT B C
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How Is the Width of a Layout Drawing Estimated from a Stick Diagram?

Introduction To be able to calculate an area estimation, you must be aware of the layout design rules, and you must have a stick diagram. Determine the width of your layout as follows:
Step 1. Action Starting at one end of the stick diagram, add up the minimum width and spacing requirements for all objects for the p-type transistors in the diagram. This gives you the width for the p-type transistors. Repeat the above step for all objects for the n-type transistors. This gives you the width of the n-type transistors. Compare the width of the p-type and n-type transistors. The larger value is the estimated width for the layout drawing.
Procedure
2. 3.
continued...
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How Is the Width of a Layout Drawing Estimated from a Stick Diagram? (continued)
Example Use the procedure to estimate the width of the Inverter layout drawing.
Step 1. Action Starting at one end of the stick diagram, add up the minimum width and spacing requirements for all objects for the p-type transistors in the diagram. This gives you the width for the p-type transistors. 2 2 2 2 2 2 2 2 Vcc A OUT 2
Vss 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 = 18 2. Repeat the above step for all objects for the n-type transistors. This gives you the width of the n-type transistors.
Vcc A OUT
Vss 2 2 2 2 2 2 2
2 + 2 + 2 + 2 + 2 + 2 + 2 = 14 3. Compare the width of the p-type and n-type transistors. The larger value is the estimated width for the layout drawing. Since 18 is larger than 14, this cell is 18 wide.
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Lab 5-3.b: Estimate the Width of a Layout Drawing from a Stick Diagram
Introduction Now that you know how to estimate the width of a layout drawing from a stick diagram, you will use your previous stick diagrams to estimate the layout drawing width and compare this value to the actual layout drawing width.
Instructions for Lab 5-3.b 1. Use the stick drawing and layout drawing you drew for the 2-input NOR and 3-input NAND. Complete the following exercises for both logic functions. a. Use your stick drawing and estimate the width of the layout drawing.
Step 1. Action Starting at one end of your stick diagram, add up the minimum width and spacing requirements for all of the objects for the p-type transistors in the diagram. This gives you the width for the p-type transistors. Repeat the above step for all of the objects for the n-type transistors. This gives you the width of the n-type transistors. Compare the width of the p-type and n-type transistors. The larger value is the width of your cell.
2. 3.
b.
Measure the actual width of the layout drawing. Compare the estimated value to actual value. Are the values close?
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Lesson 5-4 Overview

Introduction Arranging transistors so the common nodes share the same S/D diffusion region helps to gain better density and performance. In this lesson, you will learn to arrange the transistors so common nodes share the same S/D diffusion region whenever possible. The following topics are covered in this lesson: Topic Page
Objective
Topics
What Is Node Sharing? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 How Is Node Sharing Achieved? . . . . . . . . . . . . . . . . . . . . . 5-36 Lab 5-4: Use Node Sharing to Increase Density . . . . . . . . . 5-38
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What Is Node Sharing?

Introduction In the attempt to draw more transistors in less area, it is often necessary for common S/D nodes to share the same diffusion region. Node sharing is touching or overlapping of same-node S/D terminals from two different transistors. By touching or overlapping the common terminal, the two transistors take up less room than if the two transistor are spaced away from each other according to the diffusion to diffusion spacing process design rule. Two p-type transistors that share a common node can be drawn so that the common node of the transistors overlaps, thus taking up less room, as shown in the following graphic.
S/D Diffusion Terminals with Design Rule Spacing Vcc Vcc
Denition
Example
ZING Overlapping S/D Diffusion Terminals Vcc
ZANG
ZING
ZANG
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How Is Node Sharing Achieved?

Introduction Before creating a layout drawing, you can determine which transistors should share nodes and rearrange the transistors in the stick diagram. Find the nodes that can be shared, as follows:
Step 1. 2. Action Identify the internal nodes on the transistor-level schematic and label them with unique names. Identify the internal nodes on the stick diagram and label each internal node with the same name you gave it on the transistor-level schematic. Look at the n-type and the p-type transistors on the stick diagram and identify any common nodes that are not drawn next to each other. Try to rearrange the common nodes so that they are next to each other. This arrangement
G
Procedure
3.
4.
reduces the breaks in diffusion better density shorter wire lengths fewer routing lines minimizes routing
continued...
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How Is Node Sharing Achieved? (continued)

Example Use the procedure to achieve node sharing for the following logic-level schematic.
A B Step 1. OUT ZING
Action Identify the internal nodes on the transistor-level schematic and label them with unique names.
B A OUT ZING N1
2.
Identify the internal nodes on the stick diagram and able each internal node with the same name you gave it on the transistor-level schematic.
OUT B N1 A ZING
3.
Look at the n-type and the p-type transistors on the stick diagram and identify any common nodes that are not drawn next to each other. Try to rearrange the common nodes so that they are next to each other.
4.
OUT
N1
ZING
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Lab 5-4: Use Node Sharing to Increase Density

Introduction Now that you know how to achieve node sharing, you will use the node sharing procedure to draw the stick drawings for the following logic-level schematics.
Instructions for Lab 5-4 Use the node-sharing procedure to create a layout drawing for each of the following logic-level schematics. 1. a. A B Out
b.
N17 Do It PHZ
c.
C
Out
D E d.
BING BANG BOOM ZAP
e.
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Lesson 5-5 Overview

Introduction A very important aspect in the layout of any design is the area utilized by the transistors and the interconnect. In this lesson, you will learn to calculate area values. The following topics are covered in this lesson: Topic Page
Objective Topics
Area Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 Lab 5-5.a: Calculate Area . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 Units of Measure Conversion . . . . . . . . . . . . . . . . . . . . . . . 5-43 Lab 5-5.b: Convert Units of Measure . . . . . . . . . . . . . . . . . 5-44 Average Area per Transistor Calculation . . . . . . . . . . . . . . . 5-46 Lab 5-5.c: Calculate the Average Area per Transistor . . . . . 5-47
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Area Calculation
Introduction Area estimation is used to forecast the space needed for your circuit which is an important part of planning. Area is the actual space that the layout will occupy. There is a simple formula to determine area. The formula to calculate area is: area = width x length area = X * Y If X = 4 inches and Y = 2 inches, then the area is calculated as follows: Area = 4 in * 2 in = 8 in2
Calculation
X Area Units The units for area are square units. If the length and width are measured in microns (), then the area units are square microns (2).
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Lab 5-5.a: Calculate Area

Introduction Now that you know the formula to calculate area, you will complete the following area calculations.
Instructions for Lab 5-5.a

1.
Calculate the area, given the following width and length values. a. b. c. d. 20 x 100 = 85 x 34 = 56 x 135 = 97 x 210 =
2.
Given the area and one of the sides, calculate what the other side must be. a. b. c. 58 x ____ = 5626 2 13 x ____ = 312 2 56 x ____ = 1900 2
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Units of Measure Conversion

Introduction It is important to know how to convert between mils and microns and vice versa, because both units of measure are used in chip design. The micron is the unit of measure in a transistor layout. However, the mil is the unit of measure when dealing with the functional unit, unit, or chip level. The units of measure are as follows: micron () = 1,000,000th of a meter mil = 1,000th of an inch Conversion
G
Units of Measure
To convert mils to microns, multiply by 25.4 /mil mil * (25.4 /mil) = Example: 2 mil * (25.4 /mil) = 50.8
To convert microns to mils, divide by 25.4 mil/ / (25.4 mil/) = mil Example: 28 / (25.4 mil/) = 1.1 mil
To convert square mils (m2) to square microns (2), multiply by

645.16 2/m2
m2 * (645.16 2/m2) = 2 Example: 120 m2 * (645.16 2/m2) = 77419.22 Rounding All results must be rounded to two digits to the right of the decimal point.
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Lab 5-5.b: Convert Units of Measure

Introduction Now that you know how to convert the units of measure for layout drawings, you will complete the following unit conversions.
Instructions for Lab 5-5.b 1. Fill in the correct values for the micron column in the following table: mil
1 354 443 138
Conversion
* 25.4 * 25.4 * 25.4 * 25.4 = = = =
micron
2.
Fill in the correct values for the mil column in the following table: micron
25.4 5435 8943 138
Conversion
/ 25.4 / 25.4 / 25.4 / 25.4 = = = =
mil
3.
Fill in the correct values for the mil2 column in the following table: mil2
1 123 321 645
Conversion
* 645.16 * 645.16 * 645.16 * 645.16 = = = =
micron2
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Instructions for Lab 5-5.b 4. Fill in the correct values in the mil2 column in the following table: Device Area (mil2)
12 10.4 18.3 14.7 33
# of Devices
8 7 11 15 23 = = = = =
Area/Transistor
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Average Area per Transistor Calculation

Introduction The average area per transistor or density can be calculated with a simple formula. This information will be used in planning. The average area per transistor is a value used to compare different layout drawings; the smaller the values is the better. To calculate the area per transistor, you must rst determine the total area of the transistors. total_area = X * Y Next, use the total area value in the following formula to calculate the density. density = total_area / number_logic-level_trans Example If the layout of a circuit contains 25 transistors and is 100 by 100, then the total area and density values are calculated as follows: total_area = 100 * 100 = 100002 density = 100002 / 25 transistors = 4002/transistor
Calculation
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Lab 5-5.c: Calculate the Average Area per Transistor

Introduction Now that you know how to calculate the average area per transistor, or the density for layout drawings, you will complete the following density calculations.
Instructions for Lab 5-5.c 1. Given the following information, complete the calculation. a. If the layout of a circuit contains 20 transistors and is 100 by 90, then what are the total area and density values?
b.
If the layout of a circuit contains 75 transistors and is 100 by 90, then what are the total area and density values?
c.
If the total area of the layout of a circuit is 3502 and the average area per transistor is 502, then how many transistors are in the layout?
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Lesson 5-6 Overview

Introduction A very important aspect in the layout of any design is the resistance of the interconnect. In this lesson, you will learn to calculate resistance. The following topics are covered in this lesson: Topic Page
Objective Topics
What Is Resistance? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 Lab 5-6.a: Calculate Resistance Values . . . . . . . . . . . . . . . . 5-53 How Is Sheet Resistance Calculated? . . . . . . . . . . . . . . . . . 5-56 Lab 5-6.b: Calculate Sheet Resistance . . . . . . . . . . . . . . . . . 5-58
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What Is Resistance?
Introduction Resistance has a direct and measurable effect on the performance of a circuit. It can be either intentional or parasitic. You must be able to increase and decrease the resistance in a circuit to obtain the correct circuit functionality. Resistance is the opposition of current ow. Each material has a different resistive value that represents how much that material opposes current ow. The unit of measure for resistance is the ohm (). Resistors are drawn to show resistance. The orientation of the resistor does not affect the resistor.
Denition
The effects of resistance in series or parallel interconnect are described below. Series Resistance Calculation The current has only one path to follow, so the total current ows through all of the resistors (R1 and R2 ... and Rn). The total resistance is equal to the sum of the individual resistances. R Total = R 1 + R 2 + + R n
current current R1=20 R2=40 current
For the above resistors the total resistance is as follows: R Total = 20 + 40 = 60 continued...
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What Is Resistance? (continued)

Parallel Resistance Calculation With parallel resistors, the current has more than one path to follow, and it follows the path of least resistance: through the smallest resistor. The total resistance will be less than the smallest resistor. 1 R total = --------------------------------------------------------------1 1 1 1 ----- + ----- + ----- + + ----- R1 R2 R3 Rn In the following example, since R1 has less resistance then R2, more current will ow through R1 than R2.
R1=20
current current current current
R2=40
For the above resistors the total resistance is as follows: 1 R total = ---------------------------------- = 13.33 1 1 ---------- + ---------- 20 40
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Lab 5-6.a: Calculate Resistance Values

Introduction Now that you know how to calculate the total resistance, you will calculate the resistance in the following exercises.
Instructions for Lab 5-6.a 1. Given the following resistors, complete the exercises.
R1 = 30 R1 = 40 R1 = 50
a. b.
Are these resistors in series or parallel? Calculate the total resistance.
2.
Given the following resistors, complete the exercises.

R1 = 60
R2 = 65
R3 = 105
a. b.
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R1 = 85 R5 = 1000
R2 = 620
R3 = 330
R4 = 100
a. b.
4.

R1 = 10
R2 = 20
R3 = 30
a. b.
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R1 = 100
R2 = 100
a. b.
6.
R1 = 1000 R2 = 880
R3 = 316
a. b.
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How Is Sheet Resistance Calculated?

Introduction In order to determine if routing has met the engineering specications, it is often important to know how much resistance the routing has. To calculate this, you must know the ohms per square. The sheet resistance or ohms per square or RHO is the electrical resistance per square of a given material. Some examples of values are as follows:
G G G
Denition
S/D Diffusion Polysilicon Metal 1
30/square 25/square .03/square
The dimensions of a square can be 3 x 3 or 20 x 20, but each square of the same material will have the same amount of resistance. Each of the following shapes represent one square of diffusion, so both are 30 ohms.
3 x 3 30
20 x 20 30
Practice
Which of the above materials has the least resistance? continued...
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How Is Sheet Resistance Calculated? (continued)

Procedure Calculate the sheet resistance as follows.
Step 1. Action Calculate the number of squares. Number of squares = ST = length / width 2. Calculate the total resistance; multiply the number of squares by the sheet resistance. Total Resistance = RT = ST * Sheet Resistance
Example
A piece of polysilicon is 2 wide and 30 long. If polysilicon has a sheet resistance of 25/square, then how much resistance does this piece of polysilicon have?
2 30 Step 1. Action Calculate the number of squares. Number of squares = ST = 30 / 2 = 15 squares 2. Calculate the total resistance; multiply the number of squares by the sheet resistance. Total Resistance = RT = ST * Sheet Resistance 15 squares * 25/square = 375
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Lab 5-6.b: Calculate Sheet Resistance

Introduction Now that you know how to calculate sheet resistance, you will calculate the sheet resistance, width, and length in the following exercises.
Instructions for Lab 5-6.b 1. An engineer wants a 5000 diffusion resistor that is 10 wide. If diffusion has a sheet resistivity of 30/square, how long must the resistor be?
2.
If polysilicon has a sheet resistivity of 22.3/square, what is the total resistance of a polysilicon line that is 300 long and 2.5 wide?
3.
An inverter needs to have some delay added to its output. If polysilicon has a sheet resistivity of 30/square, how much polysilicon should be added if the polysilicon width is 20 and you need 30 of resistance?
4.
A Metal1 line is 2.4 wide and runs 44000 across the chip. If Metal1 has a sheet resistivity of 0.084/square, what is the total resistance of the node?
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Lesson 5-7 Overview

Introduction The nal step of the layout design process is actually create a layout drawing. In this lesson, you will learn how to convert the stick diagram, your plan, into a layout drawing. The following topics are covered in this lesson: Topic Page
Objective
Topics
What Is a Layout Drawing? . . . . . . . . . . . . . . . . . . . . . . . . . 5-61 What Is Transistor Size? . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 How Is a Stick Diagram Converted to a Layout Drawing? . 5-63 Lab 5-7.a: Convert a Stick Diagram to a Layout . . . . . . . . . 5-64 Visually Verifying a Layout Drawing . . . . . . . . . . . . . . . . . 5-65 Lab 5-7.b: Visually Verify a Layout Drawing . . . . . . . . . . . 5-66
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What Is a Layout Drawing?

Introduction All prior information in this class has prepared you to create a layout drawing. The stick drawing is your actual plan for drawing your layout. A layout drawing is the actual geometries that will create the transistors and routing on the IC die.
G
Denition
Transistors are created with diffusion for the source and drain regions and with polysilicon for the gate region. Routing is created with metal, polysilicon, and contacts.
Example
The following graphics illustrate the logic-level schematic, transistor-level schematic, stick diagram, and layout drawing of an Inverter.
Logic-level Schematic Transistor-level Schematic A
Stick Diagram Vcc A
OUT
OUT
Vss
Vcc
Layout Drawing
OUT
Vss
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What Is Transistor Size?

Introduction The transistor sizes are established by the engineering design specications. The transistor size is determined by the z/l ratio which is the gate width and length. The n-type transistors and p-type transistors have different z/l ratios.
G G
Denition
z = gate width l = gate length
The larger the ratio...

G G
the more energy the gate uses the more devices it can drive
The z/l values are drawn on the logic-level schematic as follows. When there is only one number, the l value is assumed to be the default for the design process. 16 8 Example 10/3
5/3
The following transistor layout shows the z and l dimensions.

Transistor-level Schematic polysilicon Layout Drawing
z= width
diffusion l = length
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How Is a Stick Diagram Converted to a Layout Drawing?

Introduction Once you have a stick diagram, the layout drawing can easily be created. The steps to convert a stick drawing to a layout drawing are as follows:
Step 1. Action Get an idea of what the layout will look like by fattening the lines on your stick diagram. Do this by creating rectangles of the correct minimum width for each material. Redraw the stick diagram as a layout drawing, labeling all nodes. At this time, do not be concerned about the spacing process design rules.
Procedure
2.
Example
Use the procedure to convert the Inverter stick diagram to a layout drawing.
Step 1. Action Get an idea of what the layout will look like by fattening the lines on your stick diagram. Do this by creating rectangles of the correct minimum width for each material.
Vcc Out Vss
2.
Redraw the stick diagram as a layout drawing, labeling all nodes.
Vcc A Vss OUT
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Lab 5-7.a: Convert a Stick Diagram to a Layout

Introduction Now that you know the process to convert a stick diagram to a layout drawing, use the stick diagrams you drew in lab 5-3.a to draw the layout drawing in the following exercises.
Instructions for Lab 5-7.a 1. Use a stick diagram and the following procedure to create the layout drawing that reects the following logic functions. Draw all materials to the correct minimum width process design rules, however do not be concerned about the spacing design rules at this time.
Step 1. Action Get an idea of what the layout will look like by fattening the lines on your stick diagram. Do this by creating rectangles of the correct minimum width for each material. Redraw the stick diagram as a layout drawing, labeling all nodes. At this time, do not be concerned about the spacing process design rules.
2.
a. b. c. d. 2.
2-input NOR 2-input NAND 3-input NOR 3-input NAND
Use the design rules provided by your instructor and draw the layout drawings for the following logic functions with the correct width and spacing design rules. a. b. c. d. 2-input NOR 2-input NAND 3-input NOR 3-input NAND
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Visually Verifying a Layout Drawing

Introduction To ensure that layout drawings meet the process design rule specications and template requirements, you must verify all layout drawings. To verify that a layout drawing meets the process design rules, complete the following checklist against your layout.
Check 1. 2. 3. 4. 5. 6. 7. 8. Polysilicon head minimum size: 6 x 6 Diffusion head minimum size: 6 x 6 Metal pitch: 5 End cap: 2 Tap density: 1/cell Contact to gate spacing: 2 Width and spacing process-specic design rules Template width and spacing requirements
Checklist
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Lab 5-7.b: Visually Verify a Layout Drawing

Introduction Now that you know how to visually verify a layout drawing with the simplied process design rule checklist, you are ready to verify your layout drawings.
Instructions for Lab 5-7.b 1. 2. Use the simplied process design rule checklist to verify the layout drawings your instructor provides. Use the simplied process design rule checklist to verify the layout drawings you drew in prior labs.
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Lesson 5-8 Overview

Introduction To easily combine a layout drawing with other layout drawings, you will use a standard cell template. In this lesson, you will learn to draw a standard cell layout drawing to the specications of a standard cell template. The following topics are covered in this lesson: Topic Page
Objective
Topics
What Is a Standard Cell Template? ....................................... 5-69 How Is a Layout Drawing Drawn with a Standard Cell Template? .............................................................................. 5-70 Lab 5-8: Draw a Layout Drawing with a Standard Cell Template ................................................................................ 5-71
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What Is a Standard Cell Template?

Introduction Standard cells are layout drawings that are drawn to a special set of layout requirements, reduce the drawing time and ensuring predictable performance. The requirements for standard cells are often communicated with a template. A standard cell template is a graphical guide that denes the layout design rules to create standard cells. Layout drawn to specications of a standard cell template can occupy a large area of an IC. A typical standard cell template is as follows:
Tap Region
Denition
Parts of a Standard Cell Template
Vcc
10 m
NWELL
Metal tracks for Interconnect
3 m 2 m
Vss
10 m
NAC Region
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How Is a Layout Drawing Drawn with a Standard Cell Template?

Introduction To make sure that a layout meets the design specications, you must follow the specications of a standard cell template. Create a layout drawing to the specications of a standard cell template as follows.
Step 1. 2. 3. Action Use the correct standard cell template. Transfer the template specications to your drawing. Add the layout to your drawing.
Procedure
Example
With your instructor, use the above procedure and the template provided to create a layout drawing for an Inverter.
10/2 IN 8/2 OUT
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Lab 5-8: Draw a Layout Drawing with a Standard Cell Template

Introduction Now that you know what a standard cell template is, you will use one to draw a standard cell layout.
Instructions for Lab 5-8 1. 2. Given the following logic-level schematics, calculate how many transistors are needed for each layout function. Use the template provided by your instructor to draw a standard cell layout drawing for the following logic functions. a. Inverter
10/2 IN 8/2 OUT
b.
2-input NOR
A B 12/1 OUT 6/1
c.
3-input NAND
C D E 12/1 OUT 6/1
d.
Complex logic
F G H J 12/1 OUT 8/1
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Lesson 5-9 Overview

Introduction It is often necessary to alter how a transistor is drawn due to process or area restrictions. In this lesson, you will learn to draw transistors with multiple legs and bent gates. The following topics are covered in this lesson: Topic Page
Objective
Topics
How Is a Transistor Drawn with Multiple Legs? . . . . . . . . . 5-75 How Is a Transistor Drawn with a Bent Gate? . . . . . . . . . . 5-77 Lab 5-9: Draw Layout to Meet Layout Restrictions . . . . . . 5-79
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How Is a Transistor Drawn with Multiple Legs?

Introduction When a transistor is too long to t into the given area or the transistor gate is too long for the maximum gate length of the process, the gate must be broken into multiple legs. A transistor with multiple legs is a set of parallel transistors with a total z value equivalent to the desired z value. For example, three parallel n-type transistors each with a z/l of 10/2 is equivalent to one n-type transistor with a z/l of 30/2.
10/2 10/2 10/2 30/2
Denition
parallel transistors equivalent to the single transistor
single transistor equivalent to the parallel transistors
continued...
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How Is a Transistor Drawn with Multiple Legs? (continued)

Procedure Drawing transistors with multiple legs consists of the following:
Step 1. Action Calculate the number of legs needed to replace a single leg transistor as follows: a. Divide the total z value by the maximum z value. L1 = (total z) / (maximum z) If L1 is a whole number, than this is the number of legs. If L1 is not a whole number, than continue to steps b and c. b. Round L1 up to the next whole number to get the actual number of legs. # of Legs = round(L1) c. Divide the total z value by the actual number of legs to get the length of each leg. New gate length = (total z) / (# of legs) 2. Draw the multiple legs of the transistor in parallel with the new gate length.
A OUT Vss
A Vss
A OUT
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Example 1
If z/l = 30/2 and the maximum z value is 10 then,

Number of legs = (total z) / (maximum z) = 30 / 10 = 3
Each leg is 30 / 3 = 10. Example 2 If z/l = 30/2 and the maximum z value is 8 then,
Number of legs = (total z) / (maximum z) = 30 / 8 = 3.75 Number of legs = round (3.75) = 4
Each leg is 30 / 4 = 7.5
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How Is a Transistor Drawn with a Bent Gate?

Introduction Some processes allow the gate of a transistor to be bent. Bending the transistor gates can increase the layout density. Symbolic editor CAD tools usually cannot draw bent gates; the polygon editor CAD tools can draw bent gates. Drawing layout with bent gates consists of the following:
Step 1. 2. Action Calculate the total z value of the gate. (See guidelines below.) Draw the layout with the bent gate. Note: For this class, draw bends at 90.
Procedure
Guidelines
When drawing bent gates in this class, determine the total z value of the gate as follows:
G G
Do not count corners when calculating the total z value. When both corners overlap, do not count the overlap.
Count length Overlapping corners Count length
Bent gate with overlapping corners
continued...
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How Is a Transistor Drawn with a Bent Gate? (continued)

Example The following bent gate provides a savings of 4 in the vertical dimension of the diffusion.
Gate length = 6 + 6 + 6 = 18 Diffusion height = 14 Diffusion height savings = 18 - 14 = 4
This bent gate provides an area savings of 4 in the vertical dimension.
Metal 1
Diffusion Contact 6
Bent Gate Corner
14
6 6
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Lab 5-9: Draw Layout to Meet Layout Restrictions

Introduction Now that you know how to draw layout to meet layout restrictions, use the template provided by your instructor to draw a standard cell layout drawing for the following logic functions. Draw each logic function twice; once with a bent gate and once with multiple leg devices. The maximum z value is 8.
Instructions for Lab 5-9 1. Inverter

20/2 IN 8/2 OUT
2.
2-input NOR
A B 12/2 OUT 10/2
3.
3-input NAND
C D E 20/2 OUT 12/2
4.
Complex logic
F G H J 12/2 OUT 8/2
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Chapter Summary
Introduction In this chapter, you learned how transistors are created in silicon, how to estimate area, how to calculate resistance, and how to create a layout drawing from a stick diagram. In this chapter, you learned to do the following:
G G G G G G G G G
Summary
identify a transistor and a diode on the IC cross section identify process design rules on the transistor cross section identify the parts of a stick diagram estimate area calculate resistance convert a stick diagram to a layout drawing get better layout density with node sharing draw layout with a standard cell template draw layout to meet layout restrictions
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Terms
Alternating Current (AC) Aluminum An electrical current that continuously changes in magnitude and in direction of ow. The metal most often used in semiconductor processing to form the interconnects between the devices on an integrated circuit chip. The unit of measurement for electrical current in coulombs per second. One ampere ows in a circuit that has one ohm resistance when one volt is applied to the circuit. A signal that varies in amplitude continuously and without interruption. Also called linear. Contrast with digital. The unit used to depict the wavelength of light or other electromagnetic radiation. Two hundred fty-four million angstroms equals one inch. Ten angstroms equals one nanometer. The p-type diffusion of a semiconductor diode. The n-type dopant commonly used for the source and drain of nchannel MOS integrated circuits. In a bipolar transistor, the terminal that controls the current ow. A source of electromotive force (voltage and current) obtained from chemical reaction in an assembly called a cell. The voltage produced by a fresh cell depends on the materials used, but it is usually between one and two volts. Cells are connected in a series to obtain a higher voltage or in parallel to obtain greater current capacity. A numbering system with only two digits, 0 and 1. A type of transistor where a ow of both conduction electrons and holes determines the device characteristics.
Ampere
Analog
Angstrom
Anode Arsenic
Base Battery
Binary Bipolar
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Bi-CMOS
A technology in which the advantages of bipolar transistors (speed) and of CMOS devices (low power consumption) are combined in the fabrication of a single IC. A square or rectangular area on the die that is used to attach the die to the package by wire bonding. A p-type dopant commonly used for the source and drain of pchannel MOS integrated circuits. A circuit element formed by placing an insulating layer between two conducting layers. This structure is often fabricated in the manufacturing of integrated circuits. The negative electrode of a semiconductor diode. 1. A complete path that allows electrical current from one terminal of a voltage source to the other terminal. 2. An interconnection of electrical or electronic components to accomplish a specic function.
Bonding Pads
Boron
Capacitor
Cathode Circuit
Complementary Metal Oxide Semiconductor (CMOS)
A semiconductor that has low power drain. It is produced by an integrated-circuit fabrication technique using both P-channel and N-channel MOS transistors. Each transistor is made of three elements: gate, drain, and source. A design technique (using a computer and special software) that can be used in the design of a product and in the verication of its performance by simulation. A measure of the ease of conducting current. The reciprocal of resistance in DC circuits or of the real part of impedance in AC circuits. Expressed in mho (ohm spelled backwards.) The inverse of resistivity. A substance through which electrons ow with relative ease.
Computer-AidedDesign (CAD)
Conductance
Conductivity Conductor
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Contact
A vertical hole cut into the eld oxide and allowing connection of two vertical materials of an IC. The movement of electrons through a circuit. Current is measured in amperes. A single piece of silicon cut from a wafer and containing the complete device. The insulating material between the plates of a capacitor. 1. Another name for the impurities implanted into silicon devices. 2. The movement of particles away from regions of high concentration (caused by the random thermal motion of atoms and molecules).
Current
Die
Dielectric Diffusion
Digital
Representing information in discrete or quantized form or in the form of pieces such as bits or digits. A semiconductor device made of n+ and p+ diffusions abutting. The diode is used to control current ow. Current that ows in only one direction, usually without change in magnitude. A process used to change the electrical characteristics of the wafer by ion implantation (diffusion). In a MOS transistor, the terminal to which the carriers ow. The basic atomic particle having a negative charge. The deposition of a single crystal layer on the silicon wafer. This is the rst layer added to the new wafer and usually has a higher resistance than the raw wafer.
Diode
Direct Current (DC)
Doping
Drain Electron Epitaxial (Epi)
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Gate Hole
In a MOS transistor, the terminal that controls the current ow. A vacancy within the valence band of a semiconductor material caused by the deciency of an electron. It appears as if it were a moving positive charge. A cylindrical crystal grown from polysilicon material that is sliced into wafers. A tiny slice or chip of material on which a complex electrical circuit is etched or imprinted. ICs are made from semiconductor material and work according to semiconductor physics. A process in which engineering schematics are transposed into graphic symbols that will by used to make a mask. A unit of length equal to one millionth of a meter. The central processor of a computer fabricated as an integrated circuit. It performs semi-intelligent functions based on software instructions. Fundamentally, a microprocessor is a hardware device that can be electrically rewired by using software instructions. It is considered the brain of a circuit or a computet. The unit of electrical resistance. A circuit component has a resistance of one ohm when one volt applied to the component produces a current of one ampere. The process of growing a layer of silicon dioxide onto the wafer. A process in which a thin layer of nitride is deposited over the metal layer to protect it. Current path that divides from a single source into two or more separate paths that will later rejoin.
Ingot
Integrated Circuit (IC)
Layout
Micron () Microprocessor
Ohm ()
Oxidation Passivation
Parallel Circuit
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Phosphorus
The n-type dopant commonly used for the emitter diffusion in standard bipolar integrated-circuit technology and for the n-channel source and drain of MOS integrated circuits. A light sensitive material used during the photolithography process. Silicon composed of many (poly) crystals. Raw silicon comes in ingots of poly prior to crystal growth. Polysilicon may be deposited accidentally during epitaxial deposition by depositing it too fast or at too low a temperature. Chemical vapor deposition (CVD) of polysilicon usually occurs on a layer of silicon dioxide. A type of electronically programmable semiconductor memory device which is programmed after manufacture, but whose contents are unalterable once programmed. In computer or digital systems, a memory system in which any memory location can be directly accessed as easily and as quickly as any other. The contents of random access memory can be readily changed. A semiconductor memory which is programmed during manufacture. The contents can be read but cannot be altered. The opposition to current ow. It results in loss of energy in a circuit and is dissipated as heat. A type of material, such as silicon, that exhibits characteristics between a good conductor and a poor conductor. Current that ows through one or more devices in a single path. A measurement (in ohms per square cm) that is frequently used to evaluate predispositions and drive-ins. It is related to the number of n-type donor, or p-type acceptor donor, or acceptor atoms in a semiconductor.
Photo Resist Polycrystalline Silicon (Polysilicon)
Programmable Read Only Memory (PROM)
Random Access Memory (RAM)
Read-Only Memory (ROM) Resistance
Semiconductor
Series Circuit Sheet Resistance (RHO)
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Silicon Dioxide
The oxide of silicon that is used (either deposited or thermally grown) in chip fabrication as an insulating layer and as a barrier to unwanted impurities. In a MOS transistor, the terminal from which the carriers ow. A three-terminal circuit element manufactured using semiconductor material. The transistor provides signal amplication. The process of creating an integrated circuit (IC) that contains 1000 - 10,000 transistors. The substrate, made usually from semiconductor material such as silicon, that is used as the foundation on which integrated circuits are built. Unused area on the die.
Source Transistor
Very Large Scale Integration (VLSI) Wafer
White Space
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Drawing CMOS Layout For IC Design (Crestopher Saint)

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Drawing CMOS Layout For IC Design (Crestopher Saint)

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CMOS 1 Drawing CMOS Layout for IC Design Beginning Level

CMOS 1 Drawing CMOS Layout for IC Design Beginning Level

Technical Publications and Training Design Technology

Technical information: Document comments:

Chapter 1: Introduction to the Course

Chapter 3: How to Interpret Logic-level Schematics

Lesson 3-1: How to Identify the Parts of a Logic-level Schematic

Lesson 3-2: How to Describe the Function of a Logic Symbol

Chapter 4: How to Convert a Logic-level Schematic to a Transistor-level Schematic

Lesson 4-1: How to Identify the Parts of a Transistor-level Schematic

Lesson 4-2: How to Verify the Transistor-level Function of a Logic Symbol

Lesson 4-3: How to Convert a Logic-level Schematic to a Transistor-level Schematic

Chapter 5: How to Create a Layout Drawing from a Transistor-level Schematic

Lesson 5-1: How to Identify a Transistor on the IC Cross Section

Lesson 5-3: How to Convert a Transistor-level Schematic to a Stick Diagram

Lesson 5-5: How to Estimate Area

Lesson 5-6: How to Calculate Resistance

Lesson 5-7: How to Convert a Stick Diagram to a Layout Drawing

Lesson 5-8: How to Draw Layout with a Standard Cell Template

Lesson 5-9: How to Draw Layout to Meet Layout Restrictions

Chapter 1: Introduction to the Course

Chapter 1: Introduction to the Course

Chapter 1: Introduction to the Course

Introduction to the Course

The instructor presents information using foils.

Chapter 1: Introduction to the Course

Introduction to the Course (continued)

Chapter 1: Introduction to the Course

Chapter 2: Introduction to CMOS 1

Chapter 2: Introduction to CMOS 1

Chapter 2: Introduction to CMOS 1

Chapter 2: Introduction to CMOS 1

Type of IC microprocessor/CPU memory micro-controller imbedded processor/controller computers

Periphery: Connections are made to the periphery of the IC with wires.

Chapter 2: Introduction to CMOS 1

Design Process Micro-Architecture Design and Verication

Example Dene the product

Who Implements Engineer

Logic Design and Verication

Describe product functions

Circuit Design and Performance Verication

Implement product functions

Layout Design and Verication

Represent functions physically

Transfer physical representation onto template

Tapeout and Fabrication

Create the product from the template

Tapeout and First Silicon

Create the rst sample of the actual product

Chapter 2: Introduction to CMOS 1

Basic Layout Design Tasks

Layout Design Tasks

Circuit Design and Performance Verication

Layout Design and Verication

Tapeout and Fabrication

Tapeout and First Silicon

Chapter 2: Introduction to CMOS 1

What Are the Design Data Representations?

Basic Layout Design Tasks

Interpret Logic-level Schematics

Chapter 3: How to Interpret Logic-level Schematics

Chapter 3: How to Interpret Logic-level Schematics

Interpret Logic-level Schematics

AND 00=0 01=0 1*1=1

AND 00=0 01=0 1*1=1

Invert AND 00=0=1 01=0=1 1*1=1=0

NAND 00=1 01=1 1*1=0