1.

Introduction
With technology scaling, impact of local interconnects on circuit starts to dominate [10]. Local interconnects introduce a significant delay which cannot be ignored any more. Transistors operate faster as their dimensions are scaled down. The wires on the chips, however, do not exhibit same benefit of scaling. The drive for faster chips with lower cost and greater functionality has transformed interconnects into what determines the performance and reliability of a nanometer-scale integrated circuit. Layout of logic circuits can be designed using approaches like full-custom design, standard-cells or automatic layout generation. Layouts using full custom design are highly dense and having high performance but due to high time to market constraints and high cost this approach is only used for most performance-critical modules of circuit. With continuous progress in designautomation arena, trend moves towards standard-cell approach. In standard cell design, a library of full custom cells are automatically placed and routed. However, the effects of interconnects and other parasitics are more significant in standard cell design. Impact of parasitics and interconnects is more severe on sequential circuits like D-latch which is basic building of any sequential circuit. Impact of interconnects and parasitics on latch would be amplified in entire circuit design, if they are not accounted for within the D-latch itself. Hence, need for a robust and parasitic tolerant D-latch is extremely essential.

Motivation: Two main concerns in VLSI technology are speed and area. With scaling of
technology, effect of local interconnects is increasing [10], especially in sequential circuits together with increase in clock frequency [1]. In standard-cell library D-latch is basic element of sequential circuits, we need to reduce timing constraints like setup time and hold time of D-latch by optimizing the design of D-latch against increasing parasitics and interconnects impact.

Objectives: The following objectives have been achieved in this report:

y y Development and characterization of D-latch standard cell library at 45nm technology. Study the effects of local interconnects on D-latch cell with varying finger width.

y Similar work is been done for D-flip-flops.

1

2. Standard Cell Library

A powerful concept of VLSI technology, Standard cell library, helps in creating efficient and dense layouts because they are easily abutted during the layout process. Standard cell layout simply means that all standard cells-NAND, NOR, D-latch etc. are designed with standard dimensions for heights, widths, active and wells, and have standard power (vdd!) and ground (gnd!) buses. Standard cell libraries are getting bigger in size, containing more than 500 cells. Generating, verifying and maintaining of these bigger libraries is a vital task. Moreover, cell library must be generated as the technology changes rapidly and getting diverse.

2.1 Standard cell: A standard cell consists of a set of transistors and their connections which
implement a Boolean logic or a storage function. This approach standardizes the design entry level at the logic gate. Although it is possible to generate any Boolean function using only NAND (or NOR) gates, but design will be more effective if other gates are also included in library. The elementary gates such as Buffer, Inverter, NAND, NOR and Latches are also found in library while rich library contain additional complex circuits like adders and multipliers. Initial design of standard cell begins with implementing functionality of cell at transistor level. The schematic view of a cell is used for this purpose. Schematic view consists of symbolic view which has inputs and outputs of cell as well as some text information. Standard cell libraries contain another view which is called layout. Designing layout view is compulsory since net list is useful for further simulation. Layout of cell represents what will be physically placed on a chip. Each layout consists of several layers which form structures of transistors and interconnects lines. Designed layout must be checked to ensure that no design rules are violated (Design Rule Check DRC). Then layout is being tested by Layout versus Schematic (LVS) to check compatibility of layout with corresponding schematic. Now post layout simulation is performed by parasitic extraction of layout using RCX (Resistance Capacitance eXtraction).

2.2 Approaches in IC Design: There are mainly four approaches for circuit design[8].
 Full Custom Design: In this approach, designer plans layout manually by sizing each transistor of design and optimized manually to meet desired constraints. It is used mainly for highly critical modules like PLL, Microprocessors where high performance and dense design is requirement. But, high cost and long time to market restricts its spread. Custom design refers to design of cell or standard cell using MOSFETS at lowest level.  Semi-Custom design: In semi-custom design, designer uses already designed logic blocks from cell library to construct circuit. In this approach, desired functionality is realized by placing set of simple or complex logic blocks (instead of transistors and interconnects in full custom design) over and over again in layout. It has advantage of small design time compare to full custom design. Chips designed, using this approach, are cheaper in small production volume. So, it is used for prototyping new designs. But, because of use of pre-developed blocks, fine tuning is not possible. In addition, performance is also degraded and library needs to be redesigned as the technology changes. So, in general, combination of both custom and semi custom design method is used.  Automatic Design: Automatic design is when a CAD tool creates layout automatically and uses standard library cells to realize circuit. Design is described in high-level hardware description language and then fed to CAD tool to create layout and optimize it. This method is fastest, but it suffers from less optimized layout as well as loss of control over the way that the layout is generated.  Gate array based design: This design is used where low volume and fast turnaround time are required and chip designers need know little to nothing about the actual implementation of circuits.

2.3 Library Specifications: This library has been implemented at 45nm standard CMOS
technology. It contains D-latches and D-flip-flops for different driving strengths. Height of layout of each cell is fixed and equals to 4.05m. Width of layout of cells varies between 1.2 and 36.905m. Width of each cell must be an integer multiple of horizontal grid spacing. Increase in width must be multiple of vertical grid, a large area stays unoccupied. Differential pins, also occupy a large area since they must be placed on intersections of adjacent grids.
3

2.4 Layout Strategies: All cells in library have power and ground pins in common and
hence corresponding rails must be placed in the same place in layout of cells. In addition, connections near borders of cells are spaced at least 0.15m from boundary to prevent DRC errors when cells are placed side by side. The body contact of PMOS should be spaced at least 0.24m from the borders. Pins must be placed on intersections of grids. Placing the pins on horizontal or vertical routing grids will ease routing of pins. Connections should be made by METAL1 and poly layers and sometimes with METAL2 layers.

2.5 Routing Grids and Pins: Routing grids routes pins over the cells. It is important to
choose grid spacing for different routing layers properly to simplify routing. The grids spacing is chosen 0.005 m in layout view of cells.

2.6 Power and Ground Rails: Power and ground pins do not need to be placed on
interconnections. So, power and gnd rails are drawn in layout such that they are automatically connected by placing cells side-by-side. Metal contacts are placed symmetrically on intersection of grids. Remaining space between contact and adjacent grids should be filled with metal layers to prevent DRC errors. Boundary of each cell is smaller than the overall layout since power and gnd rails are shared amongst adjacent cells.

To VDD

To ground

Fig .2.1(a) Layout of a standard cell frame [9]

(b) Layout of standard cell frames [9]

3. Sequential Circuits
Sequential circuits output depends on present inputs as well as previous inputs and outputs. Latches and Flip-flops are basic building blocks of sequential circuits. Figure 3.1 shows a block diagram of sequential system. The system below belongs to class of synchronous system since all flip-flops are under control of a clock signal.

Figure 3.1: Sequential System [8]

3.1 Timing Metrics for Sequential Circuits: There are mainly three timing constraints
associated with latches and flip-flops [8].

 Setup Time: This is the time that data input must be valid before the clock transition
It is denoted by tsu.

 Hold Time: It is the time that the data input must remain valid after a clock edge [8].
It is shown by tHold.

 Clock-to-Q delay: After meeting setup and hold time, data at input is copied to Q
output after worst case propagation delay(with reference to clock edges), denoted by tc-Q

Fig.3.2 Timing Constraints of D-Latch [8]

Once we know timing information for latch/FF and combinational blocks, we can derive system level timing constraints. In sequential circuits, switching occurs concurrently to clock stimulus. Result of operations awaits next clock transition before progressing to next stage. So, next cycle cannot begin unless all computations have completed. Clock period T, must accommodate longest delay of any stage in circuit.

3.2 Static Latch and Flip-Flops: A latch is level-sensitive circuit that passes D input to Y
output when clock signal is high called as transparent mode. When clock is low, input data sampled on falling edge of clock is held stable at output for entire phase, called as hold mode. Inputs must be stable for a short time around falling edge of clock to meet setup and hold time requirements. Positive latch operate under above conditions, for negative latch conditions get reverse i.e. pass D input in low clock and hold in high clock. Flip-Flops (FF) only sample the input on clock transition, 0->1 for positive edge triggered FF, and 1->0 for negative triggered FF. A more popular FF is Master Slave FF, which is made of cascading of positive and negative latch. Both latches and FF based on Bistability principle, which uses positive feedback. It has two stable states and one metastable state. Because of very high gain in metastable state, latches are very robust to noise [8].

3.3 Multiplexer Based Latches: Most popular implementation of D-latch is using

Transmission Gate (TG) multiplexer, since in this approach, sizing only affects performance not functionality. Figure 4.4 shows implementation of static positive latch using multiplexer.

Fig.3.3 D-Latch implementation using Transmission Gate [8] When clk is high, bottom TG is on and latch is transparent i.e. D input copies to Output Y. During this feedback loop is open since top TG is off. Feedback does not have to be overridden to write the output and hence sizing of transistors is not critical for functionality.

3.4 Timing Properties: Latches are characterized by three important parameters: setup time,
hold time and propagation delay. Assume that propagation delay of each inverter is tpd_inv, and propagation delay of TG is tpd_tx. Assume contamination delay is 0 and inverter delay to derive Negative CLK from CLK has a delay 0. Setup-time is time before the rising edge of CLK that input data D must become valid. For TG multiplexer latch, D input has to propagate through I1, T1, I2 and I3 before the rising edge of CLK. This is to ensure that both terminals of TG T2 have the same voltage value. Otherwise, metastability comes in to the picture. Thus setup time is equal to 3 * tpd_inv + tpd_tx. Hold time is time that data input must be stable after rising edge of CLK. In this case, T1 is off when CLK becomes high and therefore any changes in input after CLK getting high are not seen by output. So, hold time is ideally zero but due to skew in clock, it has some small value.

4. Characterization of Standard D- latch cells

We have developed a standard cell library containing D-latch and Flip-Flops (FFs).Every standard cell is sized for minimum delay, equal rise/fall transition time and minimum area. All cells are characterized for setup time, hold time and propagation delay. All outputs are taken with load capacitance of 1fF and all input signal have rise/fall time of 10 psecs.

4.1 Design rules at 45nm Technology node:

Following rules are being followed for design and characterization flow:
Min. oxide length Min. oxide width Min. area of oxide region Min. area of contact Min. poly interconnect width Min. distance of corresponding edge of poly from oxide edge Min. N-well width Min. N-well to N-well/P-well spacing for same potential Min. N-well spacing/Enclosure of N+/P+ active area Min. N+/P+ implant width Min. distance of corresponding edge of N+/P+ from oxide edge Min. and Max. contact width/length Min. contact to contact spacing Min. metal1 width Min. metal1 to metal2 spacing Min. metal1 to contact enclosure Min. metal1 to contact enclosure on opposite sides Min. and Max. via width 0.05u 0.12u 0.035u 0.04u 0.045u 0.1u 0.3u 0.3u 0.16u 0.12u 0.1u 0.06u 0.06u 0.06u 0.66u 0.00u 0.03u 0.07u

4.2 D-Latch Standard cells:

Most common and robust technique of latch implementation involves TG multiplexer. Figure 3.3 shows positive D-latch based on multiplexer. Library contains five D-latches of different sizes. In dlatch_120, NMOS size is 120nm and PMOS size is 170nm for equal rise and fall time. Size of NMOS of TG is taken as 120nm and size of PMOS of TG is 170nm for equal rise and fall time for a given load of two inverter at load (since logical effort of combination of inverter cascaded by TG comes as two).Then for the different size of latch, we change size of NMOS
8

from 120nm to 600nm and size of PMOS vary in same proportion. Input is a square pulse having period of 200psec. And rise/fall time of 10psec. for both clock and data input. vdd is given 1volt.

Fig.4.1 Characterization of D-Latch [8]

4.3 Simulation Results: Post-layout simulation has been done on D-latch. Simulation
results confirm functionality and performance. All simulation has been performed on spice for D-latch net list (Synopsis EDA) and Cadence. To obtain setup time constraint of latch, we progressively skew the input with clock edge until circuit gets fail. As the skew increases, clockto-output delay also increases. Td-c (offset) 65 66 67 68 69 70 71 72 72.50

(in psec.) Data-to-Q delay psec.) (in 37.87 38.00 38.17 38.58 39.08 39.68 40.42 42.46 47.48

Td-c (offset) (in psec.)

(a)

(b)

Fig.4.2 Setup time simulation

(a) at data-to-clock skew 70psec.

(b) at 71psec.

10

We can easily observe that at skew of 70ps, correct value of input D is transferred to output. While for a skew of 71ps, incorrect value propagates to output. Node Y starts to go high while output (of I2 input of TG T2) starts to fall. Since, clock is enabled before the two nodes across T2 settle to same value and therefore incorrect value gets transferred.

4.4 Setup time Calculation: As previously mentioned, increasing skew of data towards
clock, doesnt affect D-Q delay when data settles a long time before, but at an offset of 71 ps, DQ delay starts to rise. Latch operation gets failed at offset of 71 ps A 5 % increase in D-Q delay is observed at 67 ps. This time entered in library as setup time. It adds a margin of about 4ps to design. Similarly, setup time for different size is calculated. Size of single finger is 120nm.

Td-c (offset) (in sec.)

Fig.4.3 Setup time violation

11

Data _to _Q Delay (in sec.)

Td-c (offset) (in sec.)

Fig.4.4 Characterization of Data-to-Q Delay and Setup time

4.5 Importance of Local Interconnects:

After comparing schematic and layout time constraints, we observe that there is a significant change in setup time and C-to-Q delay, which can cause malfunctioning in sequential circuits. Difference is due to local interconnects and parasitics, which add an extra delay in circuit. So we have to take care of local interconnects in latches and FFs with scaling of technology for proper functioning of sequential circuits.

12

5. Conclusion:
In this work, design of a standard cell library at 45nm technology has been implemented. The implemented and characterized standard cells are working properly for various driving strength. Also, comparison between schematic and layout cells has been done. It shows increasing effect of local interconnects and parasitics due to technology scaling. All the sizing has been done using logical effort method which ensures minimum delay for design. The design is robust too. Logical effort also causes small size of transistor than expected due to which area of sequential circuits reduces dramatically. Although, library is good in terms of area and variety of cells still several modifications can be applied to make library more efficient. A new methodology can be used which uses weak inverter. Using this approach, its setup time, area and performance in terms of capacitive coupling have been observed to be better.

Future Scope: Although library is sufficiently rich, still it can be extended for wide variation
of cell sizes. This work can be implemented on other D-latch architecture like D-FF and master slave FF.

13

References
[1] C.R. Bachelu and M.C. Lefebvre, the effect of the use of local interconnects in CMOS leaf cell design, in proc. IEEE ISCAS, vol.3, pp.1258-1261, 1992. [2] Jian Zhou, Jin Liu and Dian Zhou, Reduced setup time static D flip-flop, Electronics Letter, vol.37, no.5, pp.279-280, 2001. [3] Ivan Sutherlands, Bob Sproull and David Harris, Logical effort: Designing fast CMOS circuits, Morgan Kaufmann Publications, 1999. [4] B. Schurmann, J. Altmeyer, "The effect of pin constraints on layout area," European Design and Test Conference, ED&TC , pp.480-485, 6-9 Mar 1995. [5] C.L.Portmann, T.H.Y. Meng , "Loading effects on metastable parameters of CMOS latches,", Digest of Technical Papers, Symposium on VLSI Circuits, pp. 21- 22, 19-21 May 1993. [6] C.L.Portmann, T.H.Y. Meng, "Metastability in CMOS library elements in reduced supply and technology scaled applications, IEEE Journal of Solid-State Circuits, vol.30, no.1, pp.3946, Jan 1995. [7] M.S Baghini, M.P.Desai, "Impact of technology scaling on metastability performance of CMOS synchronizing latches," Design Automation Conference, Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design, pp.317-322, 2002. [8] Jan M. Rabey, Anantha Chandrakasan and Borivoje Nicolic, Digital integrated circuits: A design perspective, Prentice Hall of India Private Limited, New Delhi, 2006. [9] R.Jacob Baker, CMOS CIRCUIT DESIGN, LAYOUT AND SIMULATION, WILEY India Edition, New Delhi, 2009. [10] Navin Shrivastava and Kaustav Banerjee, Interconnect challenges for nanoscale electronic circuits, JOM, vol. 56, no. 10, pp. 30-31, 2004.

14

APPENDIX A
Layout of D-Latch of minimum size

Layout of D-Latch using twice the minimum width

15