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# VLSI DESIGN QUESTION BANK

UNIT I Syllabus INTRODUCTION : Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies- Oxidation, Lithography, Diffusion, Ion implantation, Metallisation, Encapsulation, Probe testing, Integrated Resistors and Capacitors. Questions 1.With neat sketches, explain in detail, all the steps involved in electron lithography process. April 2010, Set No. 1 2.(a) What are the steps involved in the nMOS fabrication? (b) In what way PMOS fabrication is different from nMOS fabrication. (c) Which fabrication is preferred and why? Apr10 - Set No 2 3.Explain the following: (a) Thermal oxidation technique (b) Kinetics of thermal oxidation. Apr10 - Set No 4 4.With neat sketches explain BICMOS fabrication process in a P well. [16] Apr10 - Set No 3 5.Describe in detail, the diffusion process in IC fabrication. [16] Apr/May09 - Set No 2 6.(a) Define threshold voltage of a MOS device and explain its significance. (b) Explain the effect of threshold voltage on MOSFET current Equations. [8+8] Apr/May 2007, set 1 7.A MOS Transistor in the active region measured to have a drain current of 20A when VDS=Veff. When VDS is increased by 0.5V, ID increases to 23 A. Estimate the out impedance rds, and the out impedance constant . Apr/May 2007, set 2 8.(a) With neat sketches explain the formation of the inversion layer in P-channel Enhancement MOSFET. (b) An NMOS Transistor is operated in the triode region with the following parameters VGS = 4V ; Vtn = 1V ; VDS = 2V ; W/L = 100; nCox = 90 A/V 2 Find its drain current and drain source resistance. [8+8] Apr/May 2007, set 3 9. Describe in detail metallization process in IC technogly. [16] May/Jun 2009, set 1 10.With neat sketches necessary, explain the oxidation process in the IC fabrication process. [16] May/Jun 2009, set 2 11.(a)Discuss fabrication differences between NMOS and CMOS technologies. Which fabrication is preferred and why? (b) Explain the various steps in PMOS fabrication. May/Jun 2009, set 3 12.Distinguish between thin film resistors and thin film capacitors in all aspects. [16] May/Jun 2009, set 4 13. Explain the following terms related to the fabrication of IC (a) Diffusion (b) Oxidation (c) Lithography (d) Metallization. [4+4+4+4] November 2008, set 1 14. Briefly discuss the steps involved in the manufacturing process of an IC. [16] November 2008, set2 15. Describe Ion implantation mechanism in IC fabrication. [16] November 2008, set 3 16.(a) What are the advantages of BICMOS Technology over CMOS Technology? (b) Explain how a bipolar NPN transistor is included in N well CMOS processing Draw the cross section of BICMOS transistor. [4+12] November 2008, set 4 17. Describe different methods for fabricating integrated resistors. [16] Apr/May09 - Set No 1 18. Mention different growth technologies of thin oxides and describe any one technique in detail. [16] Apr/May09 - Set No 3 19. Describe probe testing in VLSI design process. [16] Apr/May09 - Set No 4

UNIT II Syllabus BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds relationships, o; Pass transistor, MOS transistor threshold Voltage, gm, gds, figure of merit NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters. Questions 1.(a) What is body affect? Discuss different parameters on which threshold voltage depends? (b) Determine Zpu to Zpd ratio for nMOS inverter driven through one or more pass transistor? [8+8] November 2008, set 4 2.(a) Discuss the gate source and gate drain capacitance of an nFET. (b) Calculate the gate capacitance of an nFET with following parameter. W=8m, L=0.5m, Cox = 3.45 107F/cm2. November 2008, set 3 3.(a) Clearly explain the body effect of a MOS FET. (b) Clearly explain channel length modulation of a MOS FET. November 2008, set2 4.(a) With neat sketches, explain the transfer characteristic of a CMOS inverter. (b) Derive an equation for Ids of an n-channel enhancement MOSFET operating in saturation region. November 2008, set1 5.(a) Explain the operation of BiCMOS inverter? Clearly specify its characteristics. (b) Explain how the BiCMOS inverter performance can be improved. Apr10 - Set No 4 6.(a) A CMOS inverter is built in a process where kn=100A/V2, Vtn=+0.7V, k'p =42 A/V2 , Vtp=-0.8V, and a power supply of VDD =3.33V is used .Find mid point voltage VM if (W/L)n =10 and (W/L)p= 14.

(b) Discuss the CMOS invertors transfer characteristics. [8+8] Apr/May09 - Set No 2 7.(a) Find gm for an n-channel transistor with Vgs=1.2V: Vtn =0.8V; (W/L) = 10; nCox = 92A/V2. (b) Define the term threshold voltage of MOSFET and explain its significance. Apr10 - Set No 3 8. (a) Derive an equation for Transconductance of an n channel enhancement MOS-FET operating in active region. (b) A PMOS transistor is operated in triode region with the following parameters. VGS= - 4.5V, Vtp= -1V; VDS=-2.2 V, (W/L) =95, nCox =95A/V2. Find its drain current and drain source resistance. Apr10 - Set No 2 9.(a) Derive an equation for Ids of an n channel enhancement MOSFET operating in saturation region. (b) An n MOS transistor is operating in saturation region with the following parameters.Vgs=5V, Vtn =1.2V, (W/L) =10: ncox=110A/V 2. Find transconductance of the device. May/Jun 2009, set1 10.(a) Why resistor pull up is not used in MOS circuits? (b) Discuss different forms of pull up, mentioning merits and demerits of each form.[4+12] . May/Jun 2009, set2 11.(a) Explain briefly about MOS transistor switch. (b) Discuss the square law model of FET. May/Jun 2009, set3 12. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16] Apr/May 2007, set 1 13. With neat sketches explain how Diodes and Resistors are fabricated in pMOS process. [16] Apr/May 2007, set2 14.(a) Compare between CMOS and bipolar technologies. (b) With neat sketches explain nMOS fabrication process. Apr/May 2007, set4 15.(a) Define the threshold voltage of a MOS device and explains its significance. (b) Explain the effect of threshold voltage on MOSFET current equation. April 2010, Set No. 1 16.(a) Find gm and rds for an n channel transistor with Vgs =1.2V,Vtn =0.8V,(W/L) =10; nCox =92 A/V2 and Vds =Veff+0.5V, the output impedance constant = 95.3 10-3/V-1. (b) Explain figure of merit of MOS transistor. [8+8] Apr/May09 - Set No 1 17.(a) Derive the nMOS inverter transfer characteristics. Apr/May09 - Set No 3 (b) Explain the possibility of using a CMOS inverter as an amplifier. [8+8] 18. (a) Derive the relationship between drain to source current Ids and drain to source voltage Vds in non saturation and saturation region (b) Sketch the Ids versus Vds graph for enhancement mode device. [10+6] Apr/May09 - Set No 4

UNIT III Syllabus VLSI CIRCUIT DESIGN PROCESSES : VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 m CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits, Limitations of Scaling. Questions 1.Design a stick diagram for two input n-MOS NAND and NOR gates. Apr/May 2007, set1 2.What is a stick diagram and explain about different symbols used for components in stick diagram. Apr/May 2007,set4 3. Draw the stick diagram and layout for (a) NMOS inverter. (b) P-Well CMOS inverter. April 2010, Set No. 1 4. Draw the stick diagram and layout for (a) NMOS inverter. (b) P-Well CMOS inverter. Apr10 - Set No 2 5.(a) Draw the following transistors using lambda based design rules i. NMOS enhancement ii. NMOS depletion iii. PMOS enhancement. (b) Discuss the design rules for wires (both NMOS and CMOS) using lambda based design rules. Apr10 - Set No 4 6. Design a stick diagram and layout diagram for the CMOS logic shown below ___________ Y = (A + B) (C + D). Apr10 - Set No 3 7. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS inverter. (b) What are the effects of scaling on Vt? (c) What are design rules? Why is metal- metal spacing larger than poly -poly spacing. [8+4+4] Apr/May09 - Set No 2 8.(a) what is a stick diagram? Draw the stick diagram and layout for a CMOS inverter. (b) What are the effects of scaling on Vt? (c) What are design rules? Why is metal- metal spacing larger than poly poly spacing. May/Jun 2009, set1 9. Explain the following (a) Double metal MOS process rules. (b) Design rules for P- well CMOS process May/Jun 2009, set2 10. (a) Discuss the rule for n well and VDD and Vss contacts (2m CMOS). (b) Discuss the rule for pad and over glass geometry (2m CMOS). May/Jun 2009, set3 11. Implement following logic functions using CMOS logic

November 2008, set1 12. Design a stick diagram for the N MOS logic shown below. Draw the circuit diagram and layout. November 2008, set2 13. (a) Distinguish between RTL Simulation and RTLSynthesis. (b) Explain the place and route tools used in VLSI design flow. November 2008, set3 14. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS inverter. (b) What are the effects of scaling on Vt? (c) What are design rules? Why is metal- metal spacing larger than poly -poly spacing. [8+4+4] Apr/May09 - Set No 1 15. Draw the CMOS representation stick diagram and layout for a two Input EX-NOR gate. [16] Apr/May09 - Set No 3 16. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS inverter. (b) What are the effects of scaling on Vt? (c) What are design rules? Why is metal- metal spacing larger than poly -poly spacing. [8+4+4] Apr/May09 - Set No 4 UNIT IV Syllabus GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Basic circuit concepts, Sheet Resistance RS and its concept to MOS, Area Capacitance - Delays, Driving large Capacitive Loads, Wiring Units, Calculations Capacitances, Fan-in and fan-out, Choice of layers Questions 1. Calculate on resistance of the circuit shown in the figure 4 from VDD to GND. If n- channel sheet resistance Rsn=104 and P-channel sheet resistance Rsp = 3.5 104 per square. April 2010, Set No. 1 2. Design a layout diagram for two input nMOS NAND gate Apr/May 2007, set1 3. (a) What do you mean by layout of a component. (b) Draw neat layout diagrams for NMOS and PMOS transistor. Apr/May 2007, set2 4. Design a layout diagram for the PMOS logic shown below per square

Apr/May 2007, set3 5. Explain with suitable examples how design the layout of a gate to maximize performance and minimize area. Apr/May 2007,set4 6. (a) Differentiate between nMOS inverter pair delay and CMOS inverter pair delay. (b) Derive the expressions for rise and fall time of CMOS inverter delay. (c) What is the total input capacitance value offered by the inverter to achieve symmetrical operation? May/Jun 2009, set2 7. Calculate ON resistance of the circuit shown in figure 4. From VDD to ground. If n channel resistance is Rsn = 104 per square. May/Jun 2009, set3

8.Calculate on resistance of the circuit shown in the figure 4 from VDD to GND. If n- channel sheet resistance Rsn=104 per square and P-channel sheet resistance Rsp = 3.5 104 per square.

May/Jun 2009, set4 9. Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the performance of a VLSI circuit. Apr10 - Set No 4 10. (a) Explain the concept of sheet resistance and apply it to compute the ON resis-tance (VDD to GND) of an NMOS inverter having pull up to pull down ratio of 4:1, If n channel resistance is Rsn = 104 per square. (b) Calculate the gate capacitance value of 5m technology minimum size transistor with gate to channel capacitance value is 4 104pF/m2. [10+6] November 2008, set1 11. Describe three sources of wiring capacitances. Explain the effect of wiring capaci-tance on the performance of a VLSI circuit. November 2008, set2 12. Explain the following: (a) The delay unit. (b) Inverter delays. November 2008, set3 13. Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the performance of a VLSI circuit. Apr10 - Set No 2 14. (a) For a 5m technology, the standard unit of capacitances for metal 1,polysilicon and n-diffusion are 0.0075 ?Cg, 0.1 ?Cg and 0.25 ?Cg respectively. Calculate the capacitances for area shown in figure 4. Consider same area for calculation. i. metal ii. polysilicon iii. n-diffusion. (b) Implement a 3-input NOR gate in dynamic logic and explain its operation. Apr10 - Set No 3 15(a) Describe the following briefly cascaded inverters as drivers. (b) Super buffers. (c) BiCMOS drivers. [8+4+4] Apr/May09 - Set No 2 16. (a) For a 5m technology,the standard unit of capacitances for metal 1,polysilicon and n-diffusion are 0.0075 Cg, 0.1 Cg and 0.25 Cg respectively. Calculate the capacitances for area shown in figure 4. Consider same area for calculation. i. metal ii. polysilicon iii. n-diffusion. (b) Impliment a 3-input NOR gate in dynamic logic and explain its operation. [8+8]Apr/May09 - Set No 1 17. Calculate the rise time and fall time of the CMOS inverter (W/L)n= 6 and (W/L)p=8, K'n =150 A/V2, Vtn =0.7V,K'p= 62 A/V2, Vtp=-0.85V , VDD =3.3V. Total output capacitance =150 fF. [16] Apr/May09 - Set No 3 18. Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the performance of a VLSI circuit. [16] Apr/May09 - Set No 4 UNIT V Syllabus SUBSYSTEM DESIGN : Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity generators, Comparators, Zero/One Detectors, Counters, High Density Memory Elements. Questions 1.(a) Draw and explain the schematic of Pseudo-nMOS comparator. (b) Draw and explain the structure of multiplier which computes the partial products in a radix-2 manner. April 2010, Set No. 1 2. Calculate the gate capacitance value of 1.2m Technology minimum sized transistor with gate to channel capacitance value is16 104pF/m Apr/May 2007, set3 3. Calculate ON resistance from VDD to GND for the given inverter circuit shown in Figure 5, if n-channel sheet resistance is 5 104 per square.