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VLSI DESIGN QUESTION BANK

UNIT I Syllabus INTRODUCTION : Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies- Oxidation, Lithography, Diffusion, Ion implantation, Metallisation, Encapsulation, Probe testing, Integrated Resistors and Capacitors. Questions 1.With neat sketches, explain in detail, all the steps involved in electron lithography process. April 2010, Set No. 1 2.(a) What are the steps involved in the nMOS fabrication? (b) In what way PMOS fabrication is different from nMOS fabrication. (c) Which fabrication is preferred and why? Apr10 - Set No 2 3.Explain the following: (a) Thermal oxidation technique (b) Kinetics of thermal oxidation. Apr10 - Set No 4 4.With neat sketches explain BICMOS fabrication process in a P well. [16] Apr10 - Set No 3 5.Describe in detail, the diffusion process in IC fabrication. [16] Apr/May09 - Set No 2 6.(a) Define threshold voltage of a MOS device and explain its significance. (b) Explain the effect of threshold voltage on MOSFET current Equations. [8+8] Apr/May 2007, set 1 7.A MOS Transistor in the active region measured to have a drain current of 20A when VDS=Veff. When VDS is increased by 0.5V, ID increases to 23 A. Estimate the out impedance rds, and the out impedance constant . Apr/May 2007, set 2 8.(a) With neat sketches explain the formation of the inversion layer in P-channel Enhancement MOSFET. (b) An NMOS Transistor is operated in the triode region with the following parameters VGS = 4V ; Vtn = 1V ; VDS = 2V ; W/L = 100; nCox = 90 A/V 2 Find its drain current and drain source resistance. [8+8] Apr/May 2007, set 3 9. Describe in detail metallization process in IC technogly. [16] May/Jun 2009, set 1 10.With neat sketches necessary, explain the oxidation process in the IC fabrication process. [16] May/Jun 2009, set 2 11.(a)Discuss fabrication differences between NMOS and CMOS technologies. Which fabrication is preferred and why? (b) Explain the various steps in PMOS fabrication. May/Jun 2009, set 3 12.Distinguish between thin film resistors and thin film capacitors in all aspects. [16] May/Jun 2009, set 4 13. Explain the following terms related to the fabrication of IC (a) Diffusion (b) Oxidation (c) Lithography (d) Metallization. [4+4+4+4] November 2008, set 1 14. Briefly discuss the steps involved in the manufacturing process of an IC. [16] November 2008, set2 15. Describe Ion implantation mechanism in IC fabrication. [16] November 2008, set 3 16.(a) What are the advantages of BICMOS Technology over CMOS Technology? (b) Explain how a bipolar NPN transistor is included in N well CMOS processing Draw the cross section of BICMOS transistor. [4+12] November 2008, set 4 17. Describe different methods for fabricating integrated resistors. [16] Apr/May09 - Set No 1 18. Mention different growth technologies of thin oxides and describe any one technique in detail. [16] Apr/May09 - Set No 3 19. Describe probe testing in VLSI design process. [16] Apr/May09 - Set No 4

UNIT II Syllabus BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds relationships, o; Pass transistor, MOS transistor threshold Voltage, gm, gds, figure of merit NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters. Questions 1.(a) What is body affect? Discuss different parameters on which threshold voltage depends? (b) Determine Zpu to Zpd ratio for nMOS inverter driven through one or more pass transistor? [8+8] November 2008, set 4 2.(a) Discuss the gate source and gate drain capacitance of an nFET. (b) Calculate the gate capacitance of an nFET with following parameter. W=8m, L=0.5m, Cox = 3.45 107F/cm2. November 2008, set 3 3.(a) Clearly explain the body effect of a MOS FET. (b) Clearly explain channel length modulation of a MOS FET. November 2008, set2 4.(a) With neat sketches, explain the transfer characteristic of a CMOS inverter. (b) Derive an equation for Ids of an n-channel enhancement MOSFET operating in saturation region. November 2008, set1 5.(a) Explain the operation of BiCMOS inverter? Clearly specify its characteristics. (b) Explain how the BiCMOS inverter performance can be improved. Apr10 - Set No 4 6.(a) A CMOS inverter is built in a process where kn=100A/V2, Vtn=+0.7V, k'p =42 A/V2 , Vtp=-0.8V, and a power supply of VDD =3.33V is used .Find mid point voltage VM if (W/L)n =10 and (W/L)p= 14.

(b) Discuss the CMOS invertors transfer characteristics. [8+8] Apr/May09 - Set No 2 7.(a) Find gm for an n-channel transistor with Vgs=1.2V: Vtn =0.8V; (W/L) = 10; nCox = 92A/V2. (b) Define the term threshold voltage of MOSFET and explain its significance. Apr10 - Set No 3 8. (a) Derive an equation for Transconductance of an n channel enhancement MOS-FET operating in active region. (b) A PMOS transistor is operated in triode region with the following parameters. VGS= - 4.5V, Vtp= -1V; VDS=-2.2 V, (W/L) =95, nCox =95A/V2. Find its drain current and drain source resistance. Apr10 - Set No 2 9.(a) Derive an equation for Ids of an n channel enhancement MOSFET operating in saturation region. (b) An n MOS transistor is operating in saturation region with the following parameters.Vgs=5V, Vtn =1.2V, (W/L) =10: ncox=110A/V 2. Find transconductance of the device. May/Jun 2009, set1 10.(a) Why resistor pull up is not used in MOS circuits? (b) Discuss different forms of pull up, mentioning merits and demerits of each form.[4+12] . May/Jun 2009, set2 11.(a) Explain briefly about MOS transistor switch. (b) Discuss the square law model of FET. May/Jun 2009, set3 12. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16] Apr/May 2007, set 1 13. With neat sketches explain how Diodes and Resistors are fabricated in pMOS process. [16] Apr/May 2007, set2 14.(a) Compare between CMOS and bipolar technologies. (b) With neat sketches explain nMOS fabrication process. Apr/May 2007, set4 15.(a) Define the threshold voltage of a MOS device and explains its significance. (b) Explain the effect of threshold voltage on MOSFET current equation. April 2010, Set No. 1 16.(a) Find gm and rds for an n channel transistor with Vgs =1.2V,Vtn =0.8V,(W/L) =10; nCox =92 A/V2 and Vds =Veff+0.5V, the output impedance constant = 95.3 10-3/V-1. (b) Explain figure of merit of MOS transistor. [8+8] Apr/May09 - Set No 1 17.(a) Derive the nMOS inverter transfer characteristics. Apr/May09 - Set No 3 (b) Explain the possibility of using a CMOS inverter as an amplifier. [8+8] 18. (a) Derive the relationship between drain to source current Ids and drain to source voltage Vds in non saturation and saturation region (b) Sketch the Ids versus Vds graph for enhancement mode device. [10+6] Apr/May09 - Set No 4

UNIT III Syllabus VLSI CIRCUIT DESIGN PROCESSES : VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 m CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits, Limitations of Scaling. Questions 1.Design a stick diagram for two input n-MOS NAND and NOR gates. Apr/May 2007, set1 2.What is a stick diagram and explain about different symbols used for components in stick diagram. Apr/May 2007,set4 3. Draw the stick diagram and layout for (a) NMOS inverter. (b) P-Well CMOS inverter. April 2010, Set No. 1 4. Draw the stick diagram and layout for (a) NMOS inverter. (b) P-Well CMOS inverter. Apr10 - Set No 2 5.(a) Draw the following transistors using lambda based design rules i. NMOS enhancement ii. NMOS depletion iii. PMOS enhancement. (b) Discuss the design rules for wires (both NMOS and CMOS) using lambda based design rules. Apr10 - Set No 4 6. Design a stick diagram and layout diagram for the CMOS logic shown below ___________ Y = (A + B) (C + D). Apr10 - Set No 3 7. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS inverter. (b) What are the effects of scaling on Vt? (c) What are design rules? Why is metal- metal spacing larger than poly -poly spacing. [8+4+4] Apr/May09 - Set No 2 8.(a) what is a stick diagram? Draw the stick diagram and layout for a CMOS inverter. (b) What are the effects of scaling on Vt? (c) What are design rules? Why is metal- metal spacing larger than poly poly spacing. May/Jun 2009, set1 9. Explain the following (a) Double metal MOS process rules. (b) Design rules for P- well CMOS process May/Jun 2009, set2 10. (a) Discuss the rule for n well and VDD and Vss contacts (2m CMOS). (b) Discuss the rule for pad and over glass geometry (2m CMOS). May/Jun 2009, set3 11. Implement following logic functions using CMOS logic

November 2008, set1 12. Design a stick diagram for the N MOS logic shown below. Draw the circuit diagram and layout. November 2008, set2 13. (a) Distinguish between RTL Simulation and RTLSynthesis. (b) Explain the place and route tools used in VLSI design flow. November 2008, set3 14. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS inverter. (b) What are the effects of scaling on Vt? (c) What are design rules? Why is metal- metal spacing larger than poly -poly spacing. [8+4+4] Apr/May09 - Set No 1 15. Draw the CMOS representation stick diagram and layout for a two Input EX-NOR gate. [16] Apr/May09 - Set No 3 16. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS inverter. (b) What are the effects of scaling on Vt? (c) What are design rules? Why is metal- metal spacing larger than poly -poly spacing. [8+4+4] Apr/May09 - Set No 4 UNIT IV Syllabus GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Basic circuit concepts, Sheet Resistance RS and its concept to MOS, Area Capacitance - Delays, Driving large Capacitive Loads, Wiring Units, Calculations Capacitances, Fan-in and fan-out, Choice of layers Questions 1. Calculate on resistance of the circuit shown in the figure 4 from VDD to GND. If n- channel sheet resistance Rsn=104 and P-channel sheet resistance Rsp = 3.5 104 per square. April 2010, Set No. 1 2. Design a layout diagram for two input nMOS NAND gate Apr/May 2007, set1 3. (a) What do you mean by layout of a component. (b) Draw neat layout diagrams for NMOS and PMOS transistor. Apr/May 2007, set2 4. Design a layout diagram for the PMOS logic shown below per square

Apr/May 2007, set3 5. Explain with suitable examples how design the layout of a gate to maximize performance and minimize area. Apr/May 2007,set4 6. (a) Differentiate between nMOS inverter pair delay and CMOS inverter pair delay. (b) Derive the expressions for rise and fall time of CMOS inverter delay. (c) What is the total input capacitance value offered by the inverter to achieve symmetrical operation? May/Jun 2009, set2 7. Calculate ON resistance of the circuit shown in figure 4. From VDD to ground. If n channel resistance is Rsn = 104 per square. May/Jun 2009, set3

8.Calculate on resistance of the circuit shown in the figure 4 from VDD to GND. If n- channel sheet resistance Rsn=104 per square and P-channel sheet resistance Rsp = 3.5 104 per square.

May/Jun 2009, set4 9. Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the performance of a VLSI circuit. Apr10 - Set No 4 10. (a) Explain the concept of sheet resistance and apply it to compute the ON resis-tance (VDD to GND) of an NMOS inverter having pull up to pull down ratio of 4:1, If n channel resistance is Rsn = 104 per square. (b) Calculate the gate capacitance value of 5m technology minimum size transistor with gate to channel capacitance value is 4 104pF/m2. [10+6] November 2008, set1 11. Describe three sources of wiring capacitances. Explain the effect of wiring capaci-tance on the performance of a VLSI circuit. November 2008, set2 12. Explain the following: (a) The delay unit. (b) Inverter delays. November 2008, set3 13. Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the performance of a VLSI circuit. Apr10 - Set No 2 14. (a) For a 5m technology, the standard unit of capacitances for metal 1,polysilicon and n-diffusion are 0.0075 ?Cg, 0.1 ?Cg and 0.25 ?Cg respectively. Calculate the capacitances for area shown in figure 4. Consider same area for calculation. i. metal ii. polysilicon iii. n-diffusion. (b) Implement a 3-input NOR gate in dynamic logic and explain its operation. Apr10 - Set No 3 15(a) Describe the following briefly cascaded inverters as drivers. (b) Super buffers. (c) BiCMOS drivers. [8+4+4] Apr/May09 - Set No 2 16. (a) For a 5m technology,the standard unit of capacitances for metal 1,polysilicon and n-diffusion are 0.0075 Cg, 0.1 Cg and 0.25 Cg respectively. Calculate the capacitances for area shown in figure 4. Consider same area for calculation. i. metal ii. polysilicon iii. n-diffusion. (b) Impliment a 3-input NOR gate in dynamic logic and explain its operation. [8+8]Apr/May09 - Set No 1 17. Calculate the rise time and fall time of the CMOS inverter (W/L)n= 6 and (W/L)p=8, K'n =150 A/V2, Vtn =0.7V,K'p= 62 A/V2, Vtp=-0.85V , VDD =3.3V. Total output capacitance =150 fF. [16] Apr/May09 - Set No 3 18. Describe three sources of wiring capacitances. Explain the effect of wiring capacitance on the performance of a VLSI circuit. [16] Apr/May09 - Set No 4 UNIT V Syllabus SUBSYSTEM DESIGN : Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity generators, Comparators, Zero/One Detectors, Counters, High Density Memory Elements. Questions 1.(a) Draw and explain the schematic of Pseudo-nMOS comparator. (b) Draw and explain the structure of multiplier which computes the partial products in a radix-2 manner. April 2010, Set No. 1 2. Calculate the gate capacitance value of 1.2m Technology minimum sized transistor with gate to channel capacitance value is16 104pF/m Apr/May 2007, set3 3. Calculate ON resistance from VDD to GND for the given inverter circuit shown in Figure 5, if n-channel sheet resistance is 5 104 per square.

Apr/May 2007, set4 4.(a) Explain how the transistor might be sized to optimize the delay through the carry stage in parallel adder. (b) Design a two input XOR using a ROM. May/Jun 2009, set1 5. Develop a model of word line decoder delay for a RAM with 2n rows and 2m columns. Assume true and complementary inputs are available and that the input capacitance equals the capacitance of one of the columns of H=2m. Use static CMOS gates and express result in terms of n and m. May/Jun 2009, set2 6.(a) Explain how the transistor might be sized to optimize the delay through the carry stage in parallel adder. (b) Design a two input XOR using a ROM. May/Jun 2009, set3 7. Draw the logic diagram for a ripple-carry binary counter using T registers and ex-plain its operation with the help of truth table and also compare it with synchronous counters. Draw the schematic for T register. May/Jun 2009, set4 8. (a) Draw the multiplier array using a square array and explain the operation of multiplication. Apr10 - Set No 4 (b) How is the parity generator designed as a linear column of XOR gates with a tree routing channel and draw the layout of it. 9. (a) Compare different types of CMOS subsystem Adders. (b) Draw the mask layout for 6 transistors static RAM used in ASIC memories. November 2008, set1 10. (a) Draw the schematic for Transmission gate adder and explain its operation with truth table. (b) Show the basic one row and one column RAM architecture and explain its operation. November 2008, set2 11.(a) Design a comparator using XNOR and AND gate and draw its schematic. (b) Design a zero/one detector and draw its schematic and also calculate its delay. November 2008, set3 12. Develop a model of word line decoder delay for a RAM with 2n rows and 2mcolumns. Assume true and complementary inputs are available and that the input capacitance equals the capacitance of one of the columns of H=2m. Use staticCMOS gates and express result in terms of n and m. November 2008, set4 13.(a) Design a magnitude comparator based on the data path operators. (b) Draw the Schematic and mask layout of array adder used in Booth Multiplier and explain the principle of multiplication in Booth Multiplier. Apr10 - Set No 2 14. (a) Explain how the transistor might be sized to optimize the delay through the carry stage in parallel adder. (b) Design a two input XOR using a ROM. Apr10 - Set No 3 15. (a) Explain the CMOS system design based on the control structures with suitable example. (b) What are the different types of Memory elements? Compare them with respect to CMOS design. [8+8] Apr/May09 - Set No 1 16. (a) Explain the CMOS system design based on the data path operators with a suitable example. (b) Draw and explain the basic Memory- chip architecture. [8+8] Apr/May09 - Set No 2 17. (a) Draw and explain the Booth decode cell used for Booth multiplier. (b) Compare different types of CMOS subsystem shifters. [8+8] Apr/May09 - Set No 3 18. (a) Explain how the partial products are independently computed in parallel multiplier. (b) Draw the circuit and layout for ROM and explain how the dynamic power dissipation is minimized. [8+8] Apr/May09 - Set No 4 UNIT VI Syllabus SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN : PLAs, FPGAs, CPLDs, Standard Cells, Programmable Array Logic, Design Approach Questions 1.(a) Explain the methods of programming of PAL CMOS device. (b) Draw and explain the architecture of an FPGA April 2010, Set No. 1 2.(a) What are different classes of Programmable CMOS devices? Explain them briefly. (b) What is the basis for standard-cell? What are basic classes of circuits for Library cells? Apr10 - Set No 4 3.(a) What are the advantages and disadvantages of the reconfiguration. (b) Mention different advantages of Anti fuse Technology. [8+8] Apr/May 2007, set1 4. Using PLA Implement Full-adder circuit. Apr/May 2007, set2 5. (a) Compare the Antifuse and Vialink programmable interconnections for PAL devices. (b) What are different typically available SSI Standard-cell types and compare them. [8+8] Apr/May09 - Set No 2 6.(a) Draw the diagram of programmed I/O pad and explain how the antifuses are used in this. (b) Draw and explain the AND/OR representation of PLA. May/Jun 2009, set1

7(a) what are the differences between a gate array chip and standard-cell chip? What benefits does each implementation style have? (b) Write the equations for a full adder in SOP form. Sketch a 3-input, 2- output PLA implementing this logic.. May/Jun 2009, set3 8.(a) Draw the typical architecture of PAL and explain the operation of it. (b) What is CPLD? Draw its basic structure and give its applications. May/Jun 2009, set4 9.(a) Draw and explain the Antifuse Structure for programming the PAL device. (b) Explain how the I/O pad is programmed in FPGA. November 2008, set1 10.(a) What are different classes of Programmable CMOS devices? Explain them briefly. (b) What is the basis for standard-cell? What are basic classes of circuits for Library cells? November 2008, set2 11.(a) Draw the typical standard-cell structure showing regular-power cell and explain it. (b) Draw and explain the pseudo-nMOS PLA schematic for full adder and what are the advantages and disadvantages of it. Apr10 Set No 2 12.(a) What are the characteristics of 22V10 PAL CMOS device and draw its I/O structure. (b)Explain any one chip architecture that used the antifuse and give its advantages. Apr10 - Set No 3 13.(a) Draw a self timed dynamic PLA and what are the advantages of it compared to footed dynamic PLA. (b) Explain the tradeoffs between using a transmission gate or a tristate buffer to implement an FPGA routing block. [8+8] Apr/May09 - Set No 1 14.Draw the structure, explain the function and write the applications characteristics of the following programmable CMOS devices: [16] (a) PLA (b) PAL (c) FPGA (d) CPLD. Apr/May09 - Set No 3 15.(a) Draw the typical standard-cell structure showing low-power cell and explain it. (b) Sketch a diagram for two input XOR using PLA and explain its operation with the help of truth table. [8+8] Apr/May09 - Set No 4 UNIT VII Syllabus VHDL SYNTHESIS : VHDL Synthesis, Circuit Design Flow, Circuit Synthesis, Simulation, Layout, Design capture tools, Design Verification Tools, Test Principles. Questions 1.(a) Explain how VHDL is developed and where it was used initially. (b) What are the different design capture tools? Explain them briefly. April 2010, Set No. 1 2.(a) What is the goal of VHDL synthesis step in design flow? (b) Explain how register transfer level description provides optimized synthesis netlist. Apr/May 2007, set1 3.What is need for RTL simulation? Clearly explain RTL simulation flow in the ASIC design flow and also mention few leading simulation tools. Apr/May 2007,set2 4.What is need for RTL simulation? Clearly explain RTL simulation flow in the ASIC design flow and also mention few leading simulation tools. Apr/May 2007, set3 5. What are the different report files that are provided by the place and route tool and discuss clearly about each report file. Apr/May 2007, set4 6.(a) Write a VHDL program in behavioral modeling with concurrent signal assignment. (b) Explain the method of switch-level simulation for CMOS circuits and name such a simulators. May/Jun 2009, set 1 7.(a) What is the importance of operator precedence in VHDL? Is the AND operation takes place before OR operation? (b) What is mean by Hierarchy in VHDL?Write a program for 4 input multiplexer from 2 input multiplexers. May/Jun 2009, set2 8. (a) Compare the Concurrent signal assignments, sequential signal assignments and process statements. (b) Why resettable registers are preferable and what is the difference between Synchronous and Asynchronous resets? May/Jun 2009, set3 9.(a) Explain how a FSM model is described in VHDL with suitable program. (b) What is the difference between Design capture tools and design verification tools? Give some examples of each. May/Jun 2009, set4 10.(a) How to avoid floating nodes in a multiplexer and write corresponding VHDL program. (b) Draw a typical schematic and schematic icon for a module and what are additional operations are added to the electrical nature of it. November 2008 set 1 11.(a) Compare the Hardware and Software Languages. (b) Draw the basic design flow through typical CMOS VLSI tools and give some names of corresponding tools. November 2008 set 2 12.(a) Write a VHDL program for 7-sengment display decoder. (b) What are the basic sources of errors in CMOS circuits and how these are tested? Give name of such a simulator. November 2008 set 3 13.(a) Write a VHDL program in behavioral modeling with concurrent signal assignment. (b) Explain the method of switch-level simulation for CMOS circuits and name such a simulators. November 2008 set 4 14.(a) What are the advantages of Hardware Description Languages and give some examples? (b) Explain the different types of simulators used to predict and verify the performance of given circuit. Apr10 - Set No 2 15.(a) Explain how VHDL is used to simulate and synthesise a CMOS circuit. (b) Write a VHDL program for a Multiplexer with parameterized bit width. Apr10 - Set No 4 16.(a) What are basic design units of VHDL? Explain them with suitable examples. (b) Compare the circuit-level and logic-level simulations for CMOS circuits. Apr10 - Set No 3 17.(a) Write a VHDL program for 7-segment display decoder.

(b) What are the basic sources of errors in CMOS circuits and how these are tested? Give name of such a simulator. [8+8] Apr/May09 - Set No 1 18.(a) What are the design styles of VHDL and explain them with suitable examples? (b) Explain the method of Timing simulation for CMOS circuits and name such simulators. [8+8] Apr/May09 - Set No 2 19. (a) Explain how a FSM model is described in VHDL with suitable program. (b) What is the difference between Design capture tools and design verification tools? Give some examples of each. [8+8] Apr/May09 - Set No 3 20. (a) What is the importance of operator precedence in VHDL? Is the AND operation takes place before OR operation? (b) What is mean by Hierarchy in VHDL? Write a program for 4 input multiplexer from 2 input multiplexers. [8+8] Apr/May09 Set No 4 UNIT VIII Syllabus CMOS TESTING : CMOS Testing, Need for testing, Test Principles, Design Strategies for test, Chiplevel Test Techniques, Systemlevel Test Techniques, Layout Design for improved Testability. Questions 1.(a) Mention the properties of the twin oxide. (b) Clearly explain about ION implantation step in IC fabrication. Apr/May 2007 set 1 2. Explain about the following two oxidation methods. (a) High pressure oxidation. (b) Plasma oxidation. Apr/May 2007 set 2 3.With neat sketches explain Atmospheric-pressure chemical vapor deposition method.Apr/May 2007 set3 4. Explain about the following Die bandings. (a) Eutectic die bonding. (b) Epoxy die bonding. Apr/May 2007 set 4 5. (a) Explain different fault models in detail. (b) Draw the general view of the TAP data register and explain how a boundary scan register is used for testing. May/Jun 2009 set 1 6.(a) Explain how function of system can be tested. (b) Explain any one of the method of testing bridge faults. (c) What type of faults can be reduced by improving layout design? May/Jun 2009 set 2 7.(a) Why the chip testing is needed? At what levels testing a chip can occur? (b) What is the drawback of serial scan ? How to overcome this? (c) What is the percentage fault coverage? How it is calculated? May/Jun 2009 set 3 8.(a) Explain the gate level and function level of testing. (b) A sequential circuit with in? inputs and m storage devices. To test this circuit how many test vectors are required. (c) What is sequential fault grading? Explain how it is analyzed. May/Jun 2009 set 4 9. Explain the following with respect to CMOS testing: (a) ATPG (b) Fault simulation (c) Statistical Fault Analysis (d) Fault Sampling. . November 2008 set1 10.(a) Explain how the cost of chip can effect with the testing levels, (b) Explain how observability is used to test the output of a gate within a larger circuit. (c) How the Iterative Logic Array Testing can be reduced number of tests. November 2008 set2 12.(a) What type of defects are tested in manufacturing testing methods? (b) What is the Design for Autonomous Test and what is the basic device used in this? (c) What type of tests are used to check the noise margin for CMOS gates? November 2008 set3 13.(a) Explain the manufacturing test of a chip with suitable examples. (b) Explain how an Ad-hoc test technique used to test long counters. November 2008 set4 14.(a) Explain the gate level and function level of testing. (b) A sequential circuit with n inputs and m storage devices. To test this circuit how many test vectors are required? (c) What is sequential fault grading? Explain how it is analyzed. April 2010, Set No. 1 15.(a) Why stuck-at faults occur in CMOS circuits? Explain with suitable logical diagram and layout. (b) Draw a schematic for a CMOS edge-sensitive scan-register and also draw some circuit level diagrams of its implementation. Apr10 - Set No 2 16.(a) Explain how function of system can be tested. (b) Explain any one of the method of testing bridge faults. (c) What type of faults can be reduced by improving layout design? Apr10 - Set No 4 17.(a) Explain the functionality test of a chip with suitable examples. (b) What are the categories of Design for testability? Explain them briefly. Apr10 - Set No 3 18.(a) Explain the gate level and function level of testing. (b) A sequential circuit with ?n? inputs and m storage devices. To test this circuit how many test vectors are required. (c) What is sequential fault grading? Explain how it is analyzed. [6+4+6] Apr/May09 - Set No 1 19.(a) Explain the gate level and function level of testing. (b) A sequential circuit with ?n? inputs and m storage devices. To test this circuit how many test vectors are required. (c) What is sequential fault grading? Explain how it is analyzed. [6+4+6] Apr/May09 - Set No 2 20.(a) Explain how the cost of chip can effect with the testing levels, (b) Explain how observability is used to test the output of a gate within a larger circuit.

(c) How the Iterative Logic Array Testing can be reduced number of tests. [5+6+5] Apr/May09 -Set No 3 21.(a) Explain how the cost of chip can effect with the testing levels, (b) Explain how observability is used to test the output of a gate within a larger circuit. (c) How the Iterative Logic Array Testing can be reduced number of tests. [5+6+5] Apr/May09 - Set No 4