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KENNETH P. WADE kw114a646@westpost.net 6409 E. Kings Ave.

Scottsdale, Arizona 85254 Work 602-485-6312 Cell 602-323-6799 SUMMARY Specialization in process engineering, manufacturing engineering and mechanical engineering, in an ISO environment. 20 plus years as a process engineer/manufact uring engineer supporting and improving areas with mechanical design and impleme ntation of specialized equipment or modified equipment. Specialization in high v olume semi-conductor and aero space process engineering methods, DOE's, process optimization as well as mechanical design and proto-type creation from my home m echanical design center for any customer's application. Engineering department, team leader managing up to 8 engineers & technicians while performing my process engineering & mechanical development of equipment roles. * * * * * * Solid modeling/AutoCAD2007/Inventor/Solid works Process Engineering in test/probe/back grind Proto-type equipment development & implementation Probe Card Repair management/development Process implementation & process improvements Project engineering & team Leader

PROFESSIONAL EXPERIENCE STMICROELECTRONICS, INC. Phoenix, Arizona 1994 - 2011 5 th largest semi conductor company in the world manufacturing a diverse range o f transistors to microprocessors. STAFF ENGINEER I (Parametric Test Process Engineering Team Leader) 2003 - 201 1 Team leader of a process engineering team, performing test & prober program deve lopment, implementation, process improvements, management & disposition of mater ial functions for a parametric test probe and earlier test probe areas at the 20 0 mm wafer level. The parametric test area along with pack and ship processed up to 30,000 200mm wafers per month. * Designed & implemented proto-type machine to resolve an assembly lines down cr isis of two assembly sites. This one of a kind machine that provided the require d data to the chemical polish engineers to make adjustments in their programs. T his resolved the lines down crisis that IE estimated would have been $300,000/da y for both sites total. * Saved $200,000 annually using advanced probe card tip reconditioning and reduc tion processes. Also an increase of 28% in probe/test yield from the increased t rue position of this tip reduction process. This probe card tip reconditioning a nd reduction process was also implemented at Western Digital in late 2010 when S T sent me to their Fremont site. * Increased equipment up time by 20% and increase cycle time by 15% by resolutio n of downed or inaccurate probe/test equipment. Working with equipment engineeri ng we identified the components of the docking hardware, prober top plate & test head that rotated. Design, development & implementation of 3 unique fixtures el iminated these production issues entirely. * Record metrics for engineering disposition of hold rate for non-Si issues of l ess than 6 % and engineering team disposition 0 errors for a year.

* Elimination of inaccurate test/probe data due to process improvement of light sensitive product. Designed and implementation of a mechanical lid on the test h ead which is always closed except when the operator needs to open for set up. Th is eliminated any light sensitive material from going on hold making the process impossible not to follow correctly. This process improvement resulted in a 3% i ncrease of cycle time. * Start up member of the Phoenix site in 1994 & a shut down member of the Phoeni x site in 2011. ENGINEER III/IV (Process Engineer in Test/Final Probe and Back grind areas) 1 994 - 2003 Set up wafer final probe process which had an off-line inking network for wafer map storage, off-line inspection systems. Set up the back grind processes and th in wafer processes. * Responsible 24/7 for tester platforms for test program implementation & manage ment, product set up, correlation, sustaining, process control tools, data integ rity and system administration. Recorded up time of 98% on all tester platforms supported. Supported the HP83000, QT100 memory Schlumberger 9000 EXa/PX ASAP tes ter plat forms. * Set up software tools for yield monitoring in probe. Increased test/probe yiel ds by 12 %. * Increase vertical probe card life in touch downs with probe card fixture creat ion & process by 500%. * Designed & implemented zero movement off-line inker hardware reducing scrap of this to 0%. * Performed DOE's in back grind to optimize the process resulting in 7% less scr ap. Back grind equipment was (2) Disco 841/842 back grinders, (2) Nitto tape & d e-tapers & various inspection gauges (ADE, Halgenixs etc.) * Worked with back grind equipment engineering to set up PM schedules which decr ease down time by 10%. * Trained training and floor technicians to specifications in Test/Final Probe a nd Back grind areas. Manufacturing/Mechanical Engineer VLSI Technology, Inc., Tempe, AZ 1991 - 1994 Mechanical Engineer Precision Products Inc., Scottsdale, AZ 1987 - 1990 Manufacturing Engineer/Mechanical Engineer Allied Signal Inc., Tempe, AZ 1986 - 1987 EDUCATION * Bachelor's Degree Mechanical Engineering Technology, Purdue University, West Lafayette, IN * Advance Machine Design for Manufacturing course work @ Arizona State Universit y, Graduate School Additional Computer & Equipment Skills * AutoCAD, Autodesk Inventor solid modeling/FEA & detailed part/assembly BOM & G DT. * RVSI 2700 Lead scanner & Electroglas 4080 prober factory school trained.

* August Vision system & Applied Precision probe card analyzer factory school tr ained. * Catalyst, HP83000, QT100 memory Schlumberger 9000 EXa/PX ASAP, tester factory school trained. * C Programming, Solaris 8 (UNIX) systems administration, shell script writing & MS office. AWARDS * Corporate Award: STAR 2008 Team Bronze Award for "Resolution of Assembly Line Down Crisis at Muar and Shenzhen Assembly" * ST Microelectronics 2009 Corporate Recognition "Unit ID Tracing in T84" * Malcolm Baldrige Quality Award ST Microelectronics * 4 trade secrets, 2 quarterly achievement awards STM, 4 innovation awards VLSI Tech & worked on 2 US Patents.