1

Course Plan
Course Name Program Name Semester School Faculty Name : Microprocessor Systems : B Tech (IT) : VI : Amity School of Engineering : Sanjay Kumar Singh

Email: sksingh1@jpr.amity.edu Phone: +91-9887499590 Chamber Consultation Hours: 2 hrs per week (days will be decided as per time-table)

1. Instruction Details
Credits: 4 Course Duration: 44 sessions of 1 hr each. Course Code Class Room Days* Time*

* Indicative class schedule. Please check with the master timetable of the program for changes if any, for each semester. We may have few extra sessions also if required to accommodate guest lecture etc.

2. Course Details: 2a. Course Objectives:

1) To have an in knowledge of the architecture and programming of 8-bit and 16-bit Microprocessors, and to study how to interface various peripheral devices with them. 2) To study the architecture and Instruction set of 8085 and 8086 3) To develop assembly language programs in 8085. 4) To design and understand multiprocessor configurations. 5) To familiarize the Architecture of 8087 and Pentium Microprocessor.

2b. Learning Outcomes:

By the end of this course, students will be able to: 1) Understand the architecture of microprocessor system 2) Understand the assembly language 3) Write program the microprocessor (8085) using assembly language 4) Interface the microprocessor to peripheral devices such as 8251, 8253,8255,8257,8259 and memory. 5) Explain the function of the real time operating system in an embedded application & process control and instrumentation, home appliance, traffic light control etc.

2c. Prerequisites: --- Basics of Digital Design 2d. Instruction Methodology:

Lecture Tutorial Quiz Home Assignment

2e. Suggested Text Books and References

Text Book Ramesh S. Gaonkar, MicroprocessorArchitecture, Programming and applications with 8085, 5th ed.(2006), Penram International Publishing, New Delhi.

References: Douglash V Hall, Microprocessor and Interfacing, 2nd ed.(2006), Tata MC Graw-Hill Publishing. M.Rafiquzzman, Microprocessor Theory and Application, 10thed.(2006), Prentice-Hall of India. Daniel Tabak, Advance Microprocessors, 2nd ed.(1997), TataMCGraw-Hill Publishing

2f. Tentative Delivery Schedule

Session No. 1 2 3-4 5 6 7 8-9 10 11 12 13-14 15-16 17 18 19 20 20-21 22-23 24 25-26 27-28 Topic Introduction to microprocessor and microcomputer Study of 8 bit processor, 8085 pin configuration Internal Architecture and operation Tutorial 1 Interrupts Stack and Subroutines Various Data transfer schemes Tutorial 2 Introduction to 8085 instruction set Addressing mode Advance 8085 programming Counters and time delays Instruction Cycle, Machine Cycle T-States, timing diagram for 8085 instructions Tutorial 3 Mid-Term Exam Memory interfacing with 8085 Interfacing with I/O devices Cache memory system Study of 8255,8253 Study of 8257,8259,8251 III III III III III Module No. I I I I I I I I II II II II II II II H1 Remarks

4 29 30 31 32 33-34 Tutorial 4 Difference between 8085 & 8086, Block Diagram and Architecture of 8086 Pin configuration of 8086 Maximum mode and Minimum mode operation, Bus interfacing Unit Register Organization, Instruction Pointer Stack & Stack Pointer Tutorial 5 Merits of memory segmentation, Execution unit Internal Architecture of 8087 Operational overview of 8087 Introduction to 80186, 80286, 80386&80486 Tutorial 6 Pentium Processor (P-II, P-III, P-IV Quiz (Objective & Short answer) V V III IV IV IV IV

35 36 37 38 39-40 41 42-43 44

IV V V V V

H2

3. Academic Integrity Policy

Students are expected to follow Rules of Conduct and Academic Behavior Standards as detailed in the Student Regulations. Failure to comply with these rules may result in disciplinary actions as stipulated in the Students Regulations.

4. Evaluation Scheme

Continuous evaluation will be conducted for 30 marks. It is continuous and spread throughout the course. The details of the evaluation components are given below S. No 1. 2. 3. 4. 5. Evaluation Component
Home Assignments

Weight (%) 10 5 20 5 60 100

Date for Evaluation 5th,8th week 10th week

Learning Outcome Evaluated 1-5

Date of Completion of Evaluation Within a week Within a week Within a week Within 10 days

Quiz Class Test Attendance End-Semester Examination Total

7th week 1-3 Through out the semester As per university 1-5 schedule

Component 1: Home Assignments (10 Marks of the two assignments, viva would be conducted for evaluation) Component 2 Quiz (5 Marks) This is an individual activity to test students basic concepts and knowledge for each topic. Guidelines: 1. The objective type questions and short questions will be asked in quiz. 2. There will be no negative marking.