State Diagram Tutorial In general, a state diagram can be used to model the transition of a sequential machine.

The sequence is determined by the present state of the machine and the input(s) given. After completing this tutorial you should be able to create a state diagram in Xilinx, make I/O assignments, load your design on the FPGA, and test your design using the Read toWrite to software or using external hardware such as the proto box. As you may have seen, it is often desired to create a design in a CAD software such as Xilinx. Once the design is created, Xilinx can easily compile a VHDL source code for it that can in turn be program on a chip, the FPGA (Field Programmable Gate Array) . If I/O pin numbers were assigned while you were creating your state diagram, then the FPGA will be able to communicate with the outside world. This tutorial walks you through creating a two bit counter in order to help you become familiar with State CAD, the state diagram editor in the Xilinx ISE Tools. 1. Start a new project (make sure you specify XST VHDL for the design flow and Spartan 2 xc2s50-5tq144 for the part). 2. Right click in the sources pane and select New Source or choose New Source from the Project menu. 3. Select State Diagram as the source type and give a File Name (make this different than the name of your project as you do with all other sources used in ISE) 4. Click Next and then Finish 5. State CAD should launch automatically with a blank file open 6. The toolbar from State CAD is shown in the figure at left. You will need the first four tools at the top of the toolbar as well as the third tool from the bottom of the toolbar to construct a state diagram. The first tool is the selector which can be used to select, resize and move objects that are placed in the diagram. The second tool is the state drawing tool, the third is the state transition drawing tool and fourth is the reset drawing tool. Your diagram will consist of states drawn with the state drawing tool which are connected by transitions drawn with the state transition drawing tool. The yellow school bus is used to define vectors or buses. 7. Activate the state drawing tool by clicking its icon in the toolbar. Click once on the state diagram. A state similar to the one shown below appears.

8. You can draw more states by continuing to click on the diagram. It is recommend you rename the state. You can change the name of a state by switching back to the selector tool (the arrow) and double clicking the state whose name you want to

change. Like all other names in Xilinx a state name cannot begin with a number and cannot contain spaces. 9. Draw three more states and arrange them so that you diagram looks like the one shown below.

10. You now need to connect the states in your diagram with transitions. Change to the transition drawing tool and create a transition in each direction between sequential states (e.g. make a transition from STATE0 to STATE1 and from STATE1 to STATE0 but not from STATE0 to STATE2 or STATE3). You draw a transition by clicking on the state from which you want to transition and then clicking on the state to which you want to transition. When you are done you should have a total of eight transitions and your diagram should look similar to the one below.

11. If you do not like how State CAD places a transition you can easily change it using the selector tool. Simply click and drag the end black square on the head or tail of a transition to a different location. You do not need to select the transition you want to modify before dragging its end node, simply click and drag the node. If you accidentally disconnect a transition State CAD will warn you with a dialog box and it will not let you continue until you properly place the transition. 12. The goal of the state machine you are drawing is to count up or down through the binary sequence 00, 01, 10, 11. Before you can implement this behavior you need to define the inputs and outputs for your machine. There are several ways to do

this. One way is to place a vector on the diagram. You can define a variable to keep track of the count this way (it must be two bits wide so it is represented as a vector in VHDL). Change to the vector tool (yellow school bus) and click on the diagram. Double click the vector and change the name to CNT and the range to 1:0 (indicated 1 to 0 meaning there are two bits, CNT0 and CNT1, that compose the vector CNT). Click OK. By defining this vector you are enabling the values of CNT0 and CNT1 to appear on the output pins you will later set. In addition to creating the vector CNT you could also create a vector called SEGMENT with the range of 6:0. This will enable you to send outputs directly to a seven segment display where SEGMENT0SEGMENT6 represent segments ab, not respectively . Your vectors should look like the one below (if its oriented incorrectly, dont worry about it right now you will have a chance to fix it).

13. Another way to define variables is using the variables editor. Press Ctrl+E or select Variables from the Options menu. You need to define two more variables, UPCNT (single bit input) and RESET. UPCNT will be true (1) when the machine is counting up and false (0) when it is counting down. To do this, type UPCNT in the Name field, make sure the type is set to INPUT, and click the Add/Modify button. Do the same for RESET. Unfortunately, pressing enter at anytime in this dialog closes the window so you must always press a button to perform an action rather than pressing enter. While you are in the variables editor make sure that CNT is defined properly. Click the List Subbits check box to display your variable types (lower left in window). Make sure that CNT0 and CNT1 are both of type OUT:REG (indicates registered output as opposed to combinatorial output i.e. the output is associated with the state as in a Mealy machine). Also verify the elements in SEGMENT (SEGMENT0--SEGMENT6) which should be of type OUT:REG as well. If they are not click on each of them and change the type by clicking the type button until OUT:REG is displayed and then press the Add/Modify button. Also verify the states are of type NODE. If they are not, select the state and change their type by clicking on PIN/NODE. As with all variables in this tutorial, make sure the variables are all Active HIGH. There are some cases where Active LOW is desired but not here.

14. You will want to be able to determine the present count while the machine is running so each state needs an output indicating what the count is. To do this, double click each state and enter an output (CNT = 00; for STATE0, CNT = 01; for STATE1, etc). In addition to displaying the binary count, we will also output the values needed to light up the appropriate segments of the seven segment display. For State0 your screen should look like the figure below.

15. In order for the machine to determine which direction it should count you need to specify transition conditions for every transition in the diagram. Note that each transition assumes that you are in the state from which you will be transitioning and a clock has occurred. Thus, you should not ever need to include the clock in your transition condition. Double click each transition and add a transition condition. For transitions that result in the count being incremented make the condition UPCNT (1), for those that result in the count be decremented make the condition !UPCNT (0). Aside: If we happened to have a 4 bit input, say WXYZ, we could use the notation W&X&Y&Z for 1111 and !(W&X&Y&Z) for 0000 as our conditions. In addition !W&X&Y&Z represents 0111.

16. The last thing you need to do is create a reset. To do this, change to the reset drawing tool and click the diagram near STATE0. Next click STATE0. State CAD will ask you what type of reset you want, say No to specify synchronous. Your diagram should now look similar to the one below.

17. You will now want to test you state machine. To do this start State Bench by clicking on its icon in the button bar at the top of the State CAD window. To have State Bench exhaustively test the design, click the Automatic Testbench button (third button in the fifth group of buttons in the toolbar at the top of the State Bench window) and click the Begin button in the dialog that pops up. You can close the State CAD HDL Browser window that appears and then examine the operation of your machine. If you would like to test the operation in a particular way you can create your own State Bench waveform and run it. Note that State Bench asserted RESET at the start of the simulation, you must do this as well if you create your own test pattern. You may encounter several warning while trying to do this, but you can ignore them for now. Just because you receive warnings while using State Bench does not necessarily mean your circuit is flawed. Continue through this tutorial, and you will discover an easier and more familiar way to run a test waveform, but either way you test your design RESET must be asserted HIGH then taken LOW. 5

18. Save and exit State CAD. When you exit State CAD it will compile the diagram into VHDL. You now need to incorporate the VHDL representation of your state machine into your Xilinx ISE project. In project navigator right click in the sources pane and click Add Sourceor choose Add Source from the project menu. There should several files that have the name you specified for your state diagram source file but with different extensions. Double click the file that ends in .VHD. If you do not see the .VHD ext choose the notebook icon followed by your state diagram name (not state diagram name_TB). Choose VHDL Module in the dialog that pops up. Your project now includes your state machine, and the project window should look like the figure below. Be sure a shell file was created as shown.

19. Once a shell file is created we can create a symbol which represents the state diagram we just created. To do this highlight the shell_statename, then click on Create Schematic Symbol under Design Entry Utilities as shown below.

20. After completing step 19 create a schematic as you done in the past. On the right side of the screen you see the list of devices and under All Symbols you will see the directory where your newly created symbol was stored. Click on that path and you will see the shell_statename symbol. After selecting it you should see something very similar to the figure below.

21. At this point you should be able to assign the appropriate I/O ports by connecting I/O markers to the state diagram symbol. After doing so you will have to assign pin number to these I/Os. We are going to use the 7 Segment display mounted on the XC2S50 FPGA board to display out current count. Because the 7 Segment display is hard wired to the board certain pins have already been assigned to it. These pins are connected internally so you will not need to physically wire these connections. s0 s1 s2 s3 s4 s5 s6 p67 (d) p39 (c) p62 (e) p62 (g) p60 (b) p57 (f) p49 (a)

If the configuration of the 7-Segemnt displays seems ackward, thats because it is. If you look back at the figure in step 16 youll see SEGMENT=1110111 is used to display 0. Thats because of the relationship between s0..s6 and ag as shown

above. If you were connecting to an external 7-segment the figure below could be used directly.

22. In addition we must assign the Clear & Upcount inputs and the remaining outputs c0 & c1. We can use any of the available pins to assign these. The following can be used here. Clear Upcount c0 c1 clock p64 p66 p77 p83 p18

The pin assignments can be make by going to User Constraints > Edit Implementation Constraints (Constraints Editor) and selecting the Ports tab in the center of the screen as shown. The only additional pin assignment that must be made is p41 that you will need to tie to Vcc in your schematic. Note that pin 41 (Flash_CE) does not get physically connected by you, its an internal thing. To do this select and place the symbol Vcc in the schematic window and attach an output marker to it.

23. You should now be able to implement your design and generate a .bit file. Now, connect the FPGA to the DIO-32 so you can test the counter using Lab View. You could also use a proto box to test your circuit. In this case you would wire the inputs to toggle switches and the outputs to LEDS. If wiring to a proto box use the Pulse switch as the clock. 24. Load your .bit file into GXSLOAD as you have done in previous labs. Recall that if you make any changes to your design you must re-generate programming file and re-load it in GXSLOAD. 25. Finally test your design remembering to take RESET high then low. Recall that in order to transition from state to state the clock must be triggered. 26. If any changes to your state diagram need to be made simply go to your .dia file at the top of your project window. After making changes to the state diagram click on the Generate HDL icon to update your project (close any warnings that may pop up). As always you can verify your design by examining the waveform timing diagram. Below is an example of how your project window should look.

Be sure to save the entire project by going to File and selecting Save Project As...
October 1, 2003 using Xilinx 4.2i