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History of Computers: Mechanical Age

beads on rods to count and calculate

History of Computers: Mechanical Age

Slide Rule 1630

based on Napiers rules for logarithms

used until 1970s

History of Computers: Mechanical Age

Mechanical Calculator, Blaise Pascal, 1642 Analytical Engine, Charles Babbage & Augusta Ada Byron, 1823

1st practical geared mechanical computing machines

Stored 1000 20-digit decimal numbers Input to this engine was through punched cards

Joseph Jacquard, 1801

Punched Cards as inputs to weaving machine 1st stored program - for automating looms
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History of Computers: Electrical Age

Electric Motors were used in mechanical calculators in 1800s by Bomar, Monroe (4 function models) Herman Hollerith designed a real computing calculator, 1889

He founded Tabulated Machine Company; now IBM, Inc. 1st modern electromechanical computer Special-purpose computer for code breaking 1st general-purpose, programmable electronic computer system

Konrad Zuse created Z3, 1941

Alan Turing created Colossus,1943

ENIAC -Electronics Numerical Integrator & Calculator, 1946

17000 vacuum tubes, 500 miles of wire, 30 tons, 100,000 operations/sec

Further improvements due to technology in 1950s and 1960s eventually resulted in the Intel 4004 microprocessor

80x86 Evolution
4004 had 2,250 transistors

4-bit microprocessor 4KB main memory

45 instructions
PMOS technology 50 ,000 instructions/sec 8-bit version of 4004 16KB main memory

8008 - 1971

48 instructions
NMOS technology 20 s clock cycle time 8-bit microprocessor 64KB main memory 2 s clock cycle time; 500,000 instructions/sec 10X faster than 8008

8080 - 1973

Birth of Personal Computers

Released in 1974 256 byte memory Based on 2 MHz Intel 8080 chips Box with flashing lights

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80x86 Evolution
8085 - 1977

8-bit microprocessor - upgraded version of the 8080 64KB main memory 1.3 s clock cycle time; 769,230 instructions/sec 246 instructions Intel sold 200 million copies of this 8-bit microprocessor
4.77 MHz processing speed 16-bit microprocessor 256 K RAM 1MB main memory 1 or 2 floppy disk drives 2.5 MIPS (400 ns) 4- or 6-byte instruction cache Other improvements included more registers and additional instructions

8086 1978; 8088 - 1979

80286 - 1983

16-bit microprocessor very similar in instruction set to the 8086 16MB main memory. 4.0 MIPS (250 ns; 8MHz)
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80x86 Evolution
80386 - 1986

32-bit microprocessor 4GB main memory 12-33MHz Memory management unit added Variations: DX, EX, SL, SLC (cache) and SX. 80386SX: 16MB through a 16-bit data bus and 24 bit address bus Incorporated an 80386-like microprocessor, 80387-like floating point coprocessor and an 8K byte cache on one package About half of the instructions executed in 1 clock instead of 2 on the 386 32-bit microprocessor, 32-bit data bus and 32-bit address bus 4GB main memory 50 MIPs (25ns,50MHz ); Later at 66 and 100MHz (Memory transfers at 33MHz ) Variations: SX, DX2, DX4 DX2: Double clocked version DX4: Triple-clocked version

80486 - 1989

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80x86 Evolution
Pentium - 1993

32-bit microprocessor, 64-bit data bus and 32-bit address bus 4GB main memory 60, 66, 90MHz 1 clocked 100MHz version Double clocked 120 and 133MHz versions Fastest version is the 233MHz (3 clocked version) 16KB L1 cache (split instruction/data: 8KB each) Memory transfers at 66MHz (instead of 33MHz) Dual integer processors

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80x86 Evolution
Pentium Pro - 1995

32-bit microprocessor, 64-bit data bus and 36-bit address bus 64GB main memory Initial clock speed: 150 and 166MHz 16KB L1 cache (split instruction/data: 8KB each) 256KB L2 cache Memory transfers at 66MHz 3 integer processors

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80x86 Evolution
Pentium II - 1997

32-bit microprocessor, 64-bit data bus and 36-bit address bus 64GB main memory Starts at 266MHz 32KB split instruction/data L1 caches (16KB each) Module integrated 512KB L2 cache (133MHz) Memory transfers at 66MHz to 100MHz (1998)

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80x86 Evolution
Pentium III -1999

32-bit microprocessor, 64-bit data bus and 36-bit address bus 64GB main memory 800MHz and above 32KB split instruction/data L1 caches (16KB each) On-chip 256KB L2 cache (at clock speed) Memory transfers 100MHz to 133MHz Dual Independent Bus (simultaneous L2 and system memory access)

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Basic Bus Architecture

Address:

If I/O, a value between 0000H and FFFFH is issued. If memory, it depends on the architecture:

20-bits (8086/8088) 24-bits (80286/80386SX) 25-bits (80386SL/SLC/EX) 32-bits (80386DX/80486/Pentium) 36-bits (Pentium Pro/II/III)

Data:

8-bits (8088) 16-bits (8086/80286/80386SX/SL/SLC/EX) 32-bits (80386DX/80486/Pentium) 64-bits (Pentium/Pro/II/III) Most systems have at least 4 control bus connections (active low). MRDC (Memory ReaD Control), MWTC, IORC (I/O Read Control), IOWC.

Control:

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Microprocessor-Based System with Buses: Address, Data, and Control

The Pentium bus architecture is not this simple.

We will elaborate on this later.

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Basic Bus Architecture

Bus Standards ISA (Industry Standard Architecture): 8 MHz

8-bit (8086/8088) 16-bit (80286-Pentium) 32-bit (older 386 and 486 machines). 32-bit or 64-bit (Pentiums) New: PCI Express and PCI-X 533 MTS

EISA: 8 MHz

PCI (Peripheral Component Interconnect): 33 MHz

VESA (Video Electronic Standards Association): Runs at processor speed.

32-bit or 64-bit (Pentiums) Only disk and video. Competes with the PCI but is not popular.
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80x86 Evolution
Pentium IV- 2002

1.4 to 1.9GHz and the latest at 3.20 GHz and 3.46GHz (Hyper-Threading)! 1MB/512KB/256KB L2 cache 800 MHz (about 6.4GB/s)/533 MHz (4.3 GB/s)/ 400MHz (3.2 GB/s) system bus 1066 MHz front side bus Specialized for streaming video, game and DVD applications (144 new SIMD 128-bit instructions) 0.13um, more than 55 million transistors Newer ones are in 90nm transistors, >125 million possible 64-bit core and multiple cores Dual and Quad processing cores Up to 4MB L2 cache and 1066 MHz FSB 65 nm and 45 nm transistors (and lots of them!!!)
STOP

Pentium D, Core2 Duo, Core Duo, Core2 Extreme Edition - 2005-2008

For more details visit http://www.intel.com/design/

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Microprocessor Architecture
Basic Components

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Microprocessor Architecture
The MPU communicates with memory and I/O using the system bus consisting of:

Address bus: unidirectional and carries memory and I/O addresses Data bus: bidirectional; transfers binary data and instructions between MPU and memory and I/O Control lines: Read and Write timing signals asserted by MPU

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Basic Bus Architecture

Bus Standards USB (Universal Serial Bus): 1.5 Mbps,12 Mbps and now 480 Mbps.

Newest systems. Serial connection to microprocessor. For keyboards, the mouse, modems and sound cards. To reduce system cost through fewer wires. Newest systems. Fast parallel connection: Across 64-bits for 533MB/sec. For video cards. Latest AGP 3.0 with peak bandwidth of 2.1GB/s. To accommodate the new DVD (Digital Versatile Disk) players.

AGP (Advanced Graphics Port): 66MHz

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Basic Memory Architecture

Bank Layout

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Basic Memory Architecture

Bank Layout

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Basic Memory Architecture

Bank Layout

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Basic I/O Architecture

Interrupt Structure

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Interrupt Vectors (DOS PC)

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I/O Space
It is important to notice that these I/O addresses are NOT memorymapped addresses on the 80x86 machines

STOP Special instructions (IN/OUT) are used to communicate to the I/O devices

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CMPE 310 Systems Design and Programming

Chapter 2: The Microprocessor and Its Architecture

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Intel Register Architecture

Basic Architecture Outline Internal programmer visible architecture

Registers are used during programming applications Real Mode Memory: 00000H-FFFFFH (the first 1MB of main memory). All of memory (applicable to 80286 and later processors). Programmer invisible registers to control and operate the protected memory system (not directly addressable)

Real Mode Addressing:

Protected Mode Addressing: (covered later)

80x86 Memory Paging. (covered later)

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Programmer Visible Architecture

Programmer visible registers

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Programmer Visible Architecture

General Purpose Registers EAX: Accumulator: Referenced as EAX, AX, AL or AH. Used for mult, div, etc. & Used to hold an offset. EBX: Base Index: Addressable as EBX, BX, BL or BH. Used to hold the offset of a data pointer. ECX: Count: Addressable as ECX, CX, CL or CH. Used to hold the count for some instructions, REP and LOOP. Used to hold the offset of a data pointer. EDX: Data: Addressable as EDX, DX, DL or DH. Used to hold a portion of the result for mult, of the operand for div. Used to hold the offset of a data pointer. EBP: Base Pointer: Addressable as EBP or BP. Holds the base pointer for memory data transfers. EDI: Destination Index: Addressable as EDI or DI. Holds the base destination pointer for string instructions. ESI: Source Index: Use as ESI or SI. Holds the base source pointer for string instructions. General Purpose Registers

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Programmer Visible Architecture

Special Purpose Registers EIP: Instruction Pointer:

Points to the next instruction in a code segment. 16-bits (IP) in real mode and 32-bits (EIP) in protected mode. Used by the stack, call and return instructions. Store the state of various conditions in the microprocessor.

ESP: Stack Pointer:

EFLAGS:

The rightmost 5 flag bits and overflow change after many arithmetic and logic instructions execute. Data transfer and control instructions never change the flags.
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Programmer Visible Architecture

List of each Flag bit C (Carry):

Holds the carry out after addition or the borrow after subtraction. Also indicates error conditions. 0 for odd number of bits and 1 for even. Obsolete feature of the 80x86.
Used to hold half carry (or borrow) between bit positions 3& 4 Used by DAA and DAS instructions after BCD addition or subtraction.

P (Parity):

A (Auxiliary Carry):

Z (Zero):

1 if the result of an arithmetic or logic instruction is zero. 1 if the sign of the result of an arithmetic or logic instruction is negative/ set. Used for debugging, 1 Trap enable. The microprocessor interrupts the flow of instructions on conditions indicated by the debug and control registers. 9 4

S (Sign):

T (Trap):

Programmer Visible Architecture

List of each Flag bit I (Interrupt):

Controls the operation of the INTR (Interrupt request) pin. If 1, interrupts are enabled. Set by STI and CLI instructions. Selects the increment or decrement mode for the DI and/or SI registers during string instructions. If 1, registers are automatically decremented. Set by STD and CLD instructions. Set for addition and subtraction instructions. O=1, indicates an overflow

D (Direction):

O (Overflow):

80286 and up IOPL (I/O privilege level):

It holds the privilege level at which your code must be running in order to execute any I/O-related instructions. 00 (highest), 11 (lowest). Set when one system task has invoked another through a CALL instruction in protected mode.
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NT (Nested Task):

Programmer Visible Architecture

List of each Flag bit 80386 and up RF (Resume):

Used with debugging to resume regular execution after the next instruction When 0, the CPU can operate in Protected mode, Virtual 8086 mode or Real mode. When set, the CPU is converted to a high speed 8086. This allows for multiple 1M byte memory partitions to coexist for several DOS programs to execute simultaneously.

VM (Virtual Mode):

80486SX and up AC (Alignment Check):

AC=1 indicates if a word or dword is incorrectly aligned Specialized instruction for the 80486SX.

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Programmer Visible Architecture

List of each Flag bit Pentium and up: VIF (Virtual Interrupt Flag):

Copy of the interrupt flag bit. VIP=1 allows for virtual interrupts in multitasking environments (such as windows) and provides interrupt flags and pending interrupt information. Supports the CPUID instruction, which provides version number and manufacturer information about the microprocessor.

VIP (Virtual Interrupt Pending):

ID (Identification):

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Programmer Visible Architecture

Segment Registers CS (Code Segment):

In real mode, this specifies the start of a 64KB memory segment. In protected mode, it selects a descriptor that defines the starting point and length of code segment. The code segment is limited to 64KB in the x86-x286 and 4GB in the x386+. Similar to the CS except this segment holds most data used by a program. Individual data addressed using DS + offset address Length is limited to 64 K (x86-x286) and 4G (x386+) Data segment used by some string instructions to hold destination data. Similar to the CS except this segment holds the stack. ESP and EBP hold offsets into this segment. Allows two additional memory segments to be defined.
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DS (Data Segment):

ES (Extra Segment):

SS (Stack Segment):

FS and GS: 80386 and up.

Real Mode Memory Addressing

Only mode available to the 8086 and 8088.

Allow the processor to address only the first 1MB of memory (real memory or real conventional memory). DOS requires real mode.

80286+ can operate in both real & protected mode Default microprocessor mode for all intel family is real mode Segments and Offsets:

All real mode memory addresses comprise of a segment address + offset address Segment Address: located in segment registers, defines the beginning address of any 64K-byte memory segment Offset Address: selects any location within the 64K-byte memory segment

Note: All segments in real mode have a fixed length of 64K-bytes

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Real Mode Memory Addressing

Segments and offsets Effective address = Segment address + an offset.

Syntax is usually given as seg_addr:offset, e.g. 1000:F000 specifies 1F000H. Implicit combinations of segment registers and offsets are defined for memory references.
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Real Mode Memory Addressing

Segments & Offsets

For some assembly statements, the offset address may be computed to be a sum of two 16 bit registers.

In this case the sum can be larger than 64K bytes. However in this case the carry is ignored so that the segment boundary is not violated 4000:F000+3000 (assume H as default). Now F000+3000 = 12000H > 10000H, but the leftmost 1 is dropped and the address is decoded as 4000:2000

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Real Mode Memory Addressing

Segments and offsets For example, the code segment (CS) is always used with the instruction pointer (IP for real mode or EIP for protected mode). CS:EIP SS:ESP, SS:EBP DS:EAX, DS:EBX, DS:ECX, DS:EDX, DS:EDI, DS:ESI, DS:8bit_literal, DS:32- bit_literal ES:EDI FS and GS have no default. It is illegal to place an offset larger than FFFF into the 80386 32-bit registers operating in Real Mode.

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Real Mode Memory Addressing

Segments and offsets

Segmented addressing allows relocation of data and code. OS can assign the segment addresses at run time.

STOP

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ERROR: undefined OFFENDING COMMAND: STACK: